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Commit 32eafc13 authored by Louis Adrien Dufrene's avatar Louis Adrien Dufrene
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Some format before testing locally

parent 57a5a26e
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Showing with 134 additions and 123 deletions
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
View file @ 32eafc13
...@@ -3254,11 +3254,15 @@ nfapi_ul_config_request_pdu_t *has_ul_grant(module_id_t module_idP, ...@@ -3254,11 +3254,15 @@ nfapi_ul_config_request_pdu_t *has_ul_grant(module_id_t module_idP,
return (NULL); // no ul grant at all for this UE return (NULL); // no ul grant at all for this UE
} }
//-----------------------------------------------------------------------------
boolean_t boolean_t
CCE_allocation_infeasible(int module_idP, CCE_allocation_infeasible(int module_idP,
int CC_idP, int CC_idP,
int format_flag, int format_flag,
int subframe, int aggregation, int rnti) int subframe,
int aggregation,
int rnti)
//-----------------------------------------------------------------------------
{ {
nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_idP]->DL_req[CC_idP].dl_config_request_body; nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_idP]->DL_req[CC_idP].dl_config_request_body;
nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu];
...@@ -3269,9 +3273,12 @@ CCE_allocation_infeasible(int module_idP, ...@@ -3269,9 +3273,12 @@ CCE_allocation_infeasible(int module_idP,
if (format_flag != 2) { // DL DCI if (format_flag != 2) { // DL DCI
if (DL_req->number_pdu == MAX_NUM_DL_PDU) { if (DL_req->number_pdu == MAX_NUM_DL_PDU) {
LOG_W(MAC, LOG_W(MAC, "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n",
"Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", subframe,
subframe, rnti); rnti);
res = TRUE;
} else { } else {
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG;
dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE;
...@@ -3279,22 +3286,29 @@ CCE_allocation_infeasible(int module_idP, ...@@ -3279,22 +3286,29 @@ CCE_allocation_infeasible(int module_idP,
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation;
DL_req->number_pdu++; DL_req->number_pdu++;
LOG_D(MAC,
"Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n", LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) \n",
subframe, format_flag, rnti, aggregation, subframe,
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti, format_flag,
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8. rnti,
aggregation_level, aggregation);
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type);
ret = allocate_CCEs(module_idP, CC_idP, 0, subframe, 0); ret = allocate_CCEs(module_idP, CC_idP, 0, subframe, 0);
if (ret == -1) res = TRUE;
if (ret == -1) {
res = TRUE;
}
DL_req->number_pdu--; DL_req->number_pdu--;
} }
} else { // ue-specific UL DCI } else { // ue-specific UL DCI
if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) { if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) {
LOG_W(MAC, LOG_W(MAC, "Subframe %d: FAPI UL structure is full, skip scheduling UE %d\n",
"Subframe %d: FAPI UL structure is full, skip scheduling UE %d\n", subframe,
subframe, rnti); rnti);
res = TRUE;
} else { } else {
hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE; hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE;
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG;
...@@ -3302,13 +3316,18 @@ CCE_allocation_infeasible(int module_idP, ...@@ -3302,13 +3316,18 @@ CCE_allocation_infeasible(int module_idP,
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation;
HI_DCI0_req->number_of_dci++; HI_DCI0_req->number_of_dci++;
ret = allocate_CCEs(module_idP, CC_idP, 0, subframe, 0); ret = allocate_CCEs(module_idP, CC_idP, 0, subframe, 0);
if (ret == -1) res = TRUE;
if (ret == -1) {
res = TRUE;
}
HI_DCI0_req->number_of_dci--; HI_DCI0_req->number_of_dci--;
} }
} }
return res; return res;
} }
void get_retransmission_timing(LTE_TDD_Config_t *tdd_Config, frame_t *frameP, void get_retransmission_timing(LTE_TDD_Config_t *tdd_Config, frame_t *frameP,
sub_frame_t *subframeP) sub_frame_t *subframeP)
{ {
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @ 32eafc13
...@@ -1145,12 +1145,8 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1145,12 +1145,8 @@ schedule_ulsch_rnti(module_id_t module_idP,
int32_t normalized_rx_power = 0; int32_t normalized_rx_power = 0;
int32_t target_rx_power = 0; int32_t target_rx_power = 0;
static int32_t tpc_accumulated = 0; static int32_t tpc_accumulated = 0;
int UE_id = -1;
int n = 0;
int CC_id = 0;
int drop_ue = 0;
int n_rb_ul_val = 0;
int sched_frame = 0; int sched_frame = 0;
int CC_id = 0;
eNB_MAC_INST *mac = NULL; eNB_MAC_INST *mac = NULL;
COMMON_channels_t *cc = NULL; COMMON_channels_t *cc = NULL;
UE_list_t *UE_list = NULL; UE_list_t *UE_list = NULL;
...@@ -1159,6 +1155,7 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1159,6 +1155,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
UE_sched_ctrl *UE_sched_ctrl_ptr = NULL; UE_sched_ctrl *UE_sched_ctrl_ptr = NULL;
int rvidx_tab[4] = {0, 2, 3, 1}; int rvidx_tab[4] = {0, 2, 3, 1};
int first_rb_slice[NFAPI_CC_MAX]; int first_rb_slice[NFAPI_CC_MAX];
int n_rb_ul_tab[NFAPI_CC_MAX];
/* Init */ /* Init */
mac = RC.mac[module_idP]; mac = RC.mac[module_idP];
...@@ -1166,6 +1163,7 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1166,6 +1163,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
UE_list = &(mac->UE_list); UE_list = &(mac->UE_list);
sli = &(mac->slice_info); sli = &(mac->slice_info);
memset(first_rb_slice, 0, NFAPI_CC_MAX * sizeof(int)); memset(first_rb_slice, 0, NFAPI_CC_MAX * sizeof(int));
memset(n_rb_ul_tab, 0, NFAPI_CC_MAX * sizeof(int));
sched_frame = frameP; sched_frame = frameP;
if (sched_subframeP < subframeP) { if (sched_subframeP < subframeP) {
...@@ -1180,138 +1178,132 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1180,138 +1178,132 @@ schedule_ulsch_rnti(module_id_t module_idP,
nfapi_ul_config_request_body_t *ul_req_tmp_body = &(ul_req_tmp->ul_config_request_body); nfapi_ul_config_request_body_t *ul_req_tmp_body = &(ul_req_tmp->ul_config_request_body);
nfapi_ul_config_ulsch_harq_information *ulsch_harq_information; nfapi_ul_config_ulsch_harq_information *ulsch_harq_information;
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; ++CC_id) { hi_dci0_req->sfn_sf = (frameP << 4) + subframeP;
n_rb_ul_val = to_prb(cc[CC_id].ul_Bandwidth);
UE_list->first_rb_offset[CC_id][slice_idx] = cmin(n_rb_ul_val, sli->ul[slice_idx].first_rb); /* Note: RC.nb_mac_CC[module_idP] should be lower than or equal to NFAPI_CC_MAX */
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) {
n_rb_ul_tab[CC_id] = to_prb(cc[CC_id].ul_Bandwidth);
UE_list->first_rb_offset[CC_id][slice_idx] = cmin(n_rb_ul_tab[CC_id], sli->ul[slice_idx].first_rb);
} }
//LOG_D(MAC, "entering ulsch preprocesor\n"); /* ULSCH preprocessor: set UE_template->
* pre_allocated_nb_rb_ul[slice_idx]
* pre_assigned_mcs_ul
* pre_allocated_rb_table_index_ul
*/
ulsch_scheduler_pre_processor(module_idP, slice_idx, frameP, subframeP, sched_subframeP, first_rb); ulsch_scheduler_pre_processor(module_idP, slice_idx, frameP, subframeP, sched_subframeP, first_rb);
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; ++CC_id) { for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) {
first_rb_slice[CC_id] = first_rb[CC_id] + UE_list->first_rb_offset[CC_id][slice_idx]; first_rb_slice[CC_id] = first_rb[CC_id] + UE_list->first_rb_offset[CC_id][slice_idx];
} }
//LOG_D(MAC, "exiting ulsch preprocesor\n");
hi_dci0_req->sfn_sf = (frameP << 4) + subframeP;
// loop over all active UEs // loop over all active UEs
for (UE_id = UE_list->head_ul; UE_id >= 0; for (int UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
UE_id = UE_list->next_ul[UE_id]) { if (!ue_ul_slice_membership(module_idP, UE_id, slice_idx)) {
if (!ue_ul_slice_membership(module_idP, UE_id, slice_idx))
continue; continue;
}
// don't schedule if Msg4 is not received yet // don't schedule if Msg4 is not received yet
if (UE_list->UE_template[UE_PCCID(module_idP, UE_id)][UE_id]. if (UE_list->UE_template[UE_PCCID(module_idP, UE_id)][UE_id].configured == FALSE) {
configured == FALSE) { LOG_D(MAC, "[eNB %d] frame %d, subframe %d, UE %d: not configured, skipping UE scheduling \n",
LOG_D(MAC, module_idP,
"[eNB %d] frame %d subfarme %d, UE %d: not configured, skipping UE scheduling \n", frameP,
module_idP, frameP, subframeP, UE_id); subframeP,
UE_id);
continue; continue;
} }
rnti = UE_RNTI(module_idP, UE_id); rnti = UE_RNTI(module_idP, UE_id);
if (rnti == NOT_A_RNTI) { if (rnti == NOT_A_RNTI) {
LOG_W(MAC, "[eNB %d] frame %d subfarme %d, UE %d: no RNTI \n", LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d: no RNTI \n",
module_idP, frameP, subframeP, UE_id); module_idP,
continue; frameP,
} subframeP,
UE_id);
drop_ue = 0;
/* let's drop the UE if get_eNB_UE_stats returns NULL when calling it with any of the UE's active UL CCs */
/* TODO: refine?
for (n=0; n<UE_list->numactiveULCCs[UE_id]; n++) {
CC_id = UE_list->ordered_ULCCids[n][UE_id];
if (mac_xface->get_eNB_UE_stats(module_idP,CC_id,rnti) == NULL) {
LOG_W(MAC,"[eNB %d] frame %d subframe %d, UE %d/%x CC %d: no PHY context\n", module_idP,frameP,subframeP,UE_id,rnti,CC_id);
drop_ue = 1;
break;
}
} */
if (drop_ue == 1) {
/* we can't come here, ulsch_scheduler_pre_processor won't put in the list a UE with no PHY context */
abort();
/* TODO: this is a hack. Sometimes the UE has no PHY context but
* is still present in the MAC with 'ul_failure_timer' = 0 and
* 'ul_out_of_sync' = 0. It seems wrong and the UE stays there forever. Let's
* start an UL out of sync procedure in this case.
* The root cause of this problem has to be found and corrected.
* In the meantime, this hack...
*/
if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer == 0 &&
UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 0) {
LOG_W(MAC,
"[eNB %d] frame %d subframe %d, UE %d/%x CC %d: UE in weird state, let's put it 'out of sync'\n",
module_idP, frameP, subframeP, UE_id, rnti, CC_id);
// inform RRC of failure and clear timer
mac_eNB_rrc_ul_failure(module_idP, CC_id, frameP,
subframeP, rnti);
UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync = 1;
}
continue; continue;
} }
// loop over all active UL CC_ids for this UE // loop over all active UL CC_ids for this UE
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) { for (int n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
// This is the actual CC_id in the list // This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id]; CC_id = UE_list->ordered_ULCCids[n][UE_id];
n_rb_ul_val = to_prb(cc[CC_id].ul_Bandwidth);
/* /* should format_flag be 2 in CCE_allocation_infeasible??? */
aggregation=get_aggregation(get_bw_index(module_idP,CC_id), /* this test seems to be way too long, can we provide an optimization? */
eNB_UE_stats->dl_cqi, if (CCE_allocation_infeasible(module_idP, CC_id, 1, subframeP, aggregation, rnti)) {
format0); LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d/%x CC %d: not enough CCE\n",
*/ module_idP,
frameP,
subframeP,
UE_id,
rnti,
CC_id);
if (CCE_allocation_infeasible continue;
(module_idP, CC_id, 1, subframeP, aggregation, rnti)) {
LOG_W(MAC,
"[eNB %d] frame %d subframe %d, UE %d/%x CC %d: not enough nCCE\n",
module_idP, frameP, subframeP, UE_id, rnti, CC_id);
continue; // break;
} }
/* be sure that there are some free RBs */ /* be sure that there are some free RBs */
if (first_rb_slice[CC_id] >= n_rb_ul_val - 1) { if (first_rb_slice[CC_id] >= n_rb_ul_tab[CC_id] - 1) {
LOG_W(MAC, LOG_W(MAC, "[eNB %d] frame %d, subframe %d, UE %d/%x CC %d: dropping, not enough RBs\n",
"[eNB %d] frame %d subframe %d, UE %d/%x CC %d: dropping, not enough RBs\n", module_idP,
module_idP, frameP, subframeP, UE_id, rnti, CC_id); frameP,
subframeP,
UE_id,
rnti,
CC_id);
continue; continue;
} }
// if (eNB_UE_stats->mode == PUSCH) { // ue has a ulsch channel UE_template_ptr = &(UE_list->UE_template[CC_id][UE_id]);
UE_template_ptr = &UE_list->UE_template[CC_id][UE_id]; UE_sched_ctrl_ptr = &(UE_list->UE_sched_ctrl[UE_id]);
UE_sched_ctrl_ptr = &UE_list->UE_sched_ctrl[UE_id];
harq_pid = subframe2harqpid(&cc[CC_id], sched_frame, sched_subframeP); harq_pid = subframe2harqpid(&cc[CC_id], sched_frame, sched_subframeP);
round_index = UE_sched_ctrl_ptr->round_UL[CC_id][harq_pid]; round_index = UE_sched_ctrl_ptr->round_UL[CC_id][harq_pid];
AssertFatal(round_index < 8, "round %d > 7 for UE %d/%x\n", round_index,
UE_id, rnti); AssertFatal(round_index < 8, "round %d > 7 for UE %d/%x\n",
LOG_D(MAC, round_index,
"[eNB %d] frame %d subframe %d (sched_frame %d, sched_subframe %d), Checking PUSCH %d for UE %d/%x CC %d : aggregation level %d, N_RB_UL %d\n", UE_id,
module_idP, frameP, subframeP, sched_frame, sched_subframeP, harq_pid, UE_id, rnti, rnti);
CC_id, aggregation, n_rb_ul_val);
LOG_D(MAC, "[eNB %d] frame %d subframe %d (sched_frame %d, sched_subframe %d), Checking PUSCH %d for UE %d/%x CC %d : aggregation level %d, N_RB_UL %d\n",
module_idP,
frameP,
subframeP,
sched_frame,
sched_subframeP,
harq_pid,
UE_id,
rnti,
CC_id,
aggregation,
n_rb_ul_tab[CC_id]);
RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP * 10) + subframeP] = UE_template_ptr->estimated_ul_buffer; RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP * 10) + subframeP] = UE_template_ptr->estimated_ul_buffer;
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO,RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP *
10) + VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO, RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP * 10) + subframeP]);
subframeP]);
if (UE_is_to_be_scheduled(module_idP, CC_id, UE_id) > 0 || round_index > 0) // || ((frameP%10)==0)) /*
// if there is information on bsr of DCCH, DTCH or if there is UL_SR, or if there is a packet to retransmit, or we want to schedule a periodic feedback every 10 frames * If there is information on bsr of DCCH, DTCH or if there is UL_SR,
* or if there is a packet to retransmit, or we want to schedule a periodic feedback
*/
if (UE_is_to_be_scheduled(module_idP, CC_id, UE_id) > 0 || round_index > 0)
{ {
LOG_D(MAC, LOG_D(MAC, "[eNB %d][PUSCH %d] Frame %d subframe %d Scheduling UE %d/%x in round %d(SR %d,UL_inactivity timer %d,UL_failure timer %d,cqi_req_timer %d)\n",
"[eNB %d][PUSCH %d] Frame %d subframe %d Scheduling UE %d/%x in round %d(SR %d,UL_inactivity timer %d,UL_failure timer %d,cqi_req_timer %d)\n", module_idP,
module_idP, harq_pid, frameP, subframeP, UE_id, rnti, harq_pid,
round_index, UE_template_ptr->ul_SR, frameP,
UE_sched_ctrl_ptr->ul_inactivity_timer, subframeP,
UE_sched_ctrl_ptr->ul_failure_timer, UE_id,
UE_sched_ctrl_ptr->cqi_req_timer); rnti,
round_index,
UE_template_ptr->ul_SR,
UE_sched_ctrl_ptr->ul_inactivity_timer,
UE_sched_ctrl_ptr->ul_failure_timer,
UE_sched_ctrl_ptr->cqi_req_timer);
// reset the scheduling request // reset the scheduling request
UE_template_ptr->ul_SR = 0; UE_template_ptr->ul_SR = 0;
status = mac_eNB_get_rrc_status(module_idP, rnti); status = mac_eNB_get_rrc_status(module_idP, rnti);
...@@ -1410,7 +1402,7 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1410,7 +1402,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = UE_template_ptr->mcs_UL[harq_pid]; UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = UE_template_ptr->mcs_UL[harq_pid];
// buffer_occupancy = UE_template_ptr->ul_total_buffer; // buffer_occupancy = UE_template_ptr->ul_total_buffer;
while (((rb_table[rb_table_index] > (n_rb_ul_val - first_rb_slice[CC_id])) while (((rb_table[rb_table_index] > (n_rb_ul_tab[CC_id] - first_rb_slice[CC_id]))
|| (rb_table[rb_table_index] > 45)) || (rb_table[rb_table_index] > 45))
&& (rb_table_index > 0)) { && (rb_table_index > 0)) {
rb_table_index--; rb_table_index--;
...@@ -1667,7 +1659,7 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1667,7 +1659,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
first_rb[CC_id],UE_template_ptr->nb_rb_ul[harq_pid], first_rb[CC_id],UE_template_ptr->nb_rb_ul[harq_pid],
harq_pid, round_index); harq_pid, round_index);
rballoc = mac_xface->computeRIV(frame_parms->n_rb_ul_val, rballoc = mac_xface->computeRIV(frame_parms->n_rb_ul_tab[CC_id],
first_rb[CC_id], first_rb[CC_id],
UE_template_ptr->nb_rb_ul[harq_pid]); UE_template_ptr->nb_rb_ul[harq_pid]);
first_rb[CC_id]+=UE_template_ptr->nb_rb_ul[harq_pid]; // increment for next UE allocation first_rb[CC_id]+=UE_template_ptr->nb_rb_ul[harq_pid]; // increment for next UE allocation
...@@ -1680,6 +1672,6 @@ schedule_ulsch_rnti(module_id_t module_idP, ...@@ -1680,6 +1672,6 @@ schedule_ulsch_rnti(module_id_t module_idP,
} }
*/ */
} // UE_is_to_be_scheduled } // UE_is_to_be_scheduled
} // loop over UE_id } // loop over all active CC_ids
} // loop of CC_id } // loop over UE_ids
} }
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