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ZhouShuya
OpenXG-RAN
Commits
8626f645
Commit
8626f645
authored
Dec 12, 2020
by
Robert Schmidt
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nr_schedule_ulsch(): only one PDCCH PDU per BWP and CORESET
parent
7785bb7b
Changes
1
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1 changed file
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24 additions
and
10 deletions
+24
-10
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+24
-10
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
8626f645
...
@@ -596,6 +596,15 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -596,6 +596,15 @@ void nr_schedule_ulsch(module_id_t module_id,
RC
.
nrmac
[
module_id
]
->
pre_processor_ul
(
RC
.
nrmac
[
module_id
]
->
pre_processor_ul
(
module_id
,
frame
,
slot
,
num_slots_per_tdd
,
ulsch_in_slot_bitmap
);
module_id
,
frame
,
slot
,
num_slots_per_tdd
,
ulsch_in_slot_bitmap
);
const
int
CC_id
=
0
;
nfapi_nr_ul_dci_request_t
*
ul_dci_req
=
&
RC
.
nrmac
[
module_id
]
->
UL_dci_req
[
CC_id
];
ul_dci_req
->
SFN
=
frame
;
ul_dci_req
->
Slot
=
slot
;
/* a PDCCH PDU groups DCIs per BWP and CORESET. Save a pointer to each
* allocated PDCCH so we can easily allocate UE's DCIs independent of any
* CORESET order */
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu_bwp_coreset
[
MAX_NUM_BWP
][
MAX_NUM_CORESET
]
=
{
0
};
NR_ServingCellConfigCommon_t
*
scc
=
RC
.
nrmac
[
module_id
]
->
common_channels
[
0
].
ServingCellConfigCommon
;
NR_ServingCellConfigCommon_t
*
scc
=
RC
.
nrmac
[
module_id
]
->
common_channels
[
0
].
ServingCellConfigCommon
;
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
module_id
]
->
UE_info
;
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
module_id
]
->
UE_info
;
const
NR_UE_list_t
*
UE_list
=
&
UE_info
->
list
;
const
NR_UE_list_t
*
UE_list
=
&
UE_info
->
list
;
...
@@ -761,16 +770,21 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -761,16 +770,21 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu
->
pdu_bit_map
&=
~
PUSCH_PDU_BITMAP_PUSCH_PTRS
;
// disable PUSCH PTRS
pusch_pdu
->
pdu_bit_map
&=
~
PUSCH_PDU_BITMAP_PUSCH_PTRS
;
// disable PUSCH PTRS
}
}
nfapi_nr_ul_dci_request_t
*
ul_dci_req
=
&
RC
.
nrmac
[
module_id
]
->
UL_dci_req
[
0
];
/* look up the PDCCH PDU for this BWP and CORESET. If it does not exist,
ul_dci_req
->
SFN
=
frame
;
* create it */
ul_dci_req
->
Slot
=
slot
;
const
int
bwpid
=
sched_ctrl
->
active_bwp
->
bwp_Id
;
const
int
coresetid
=
sched_ctrl
->
coreset
->
controlResourceSetId
;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu
=
pdcch_pdu_bwp_coreset
[
bwpid
][
coresetid
];
if
(
!
pdcch_pdu
)
{
nfapi_nr_ul_dci_request_pdus_t
*
ul_dci_request_pdu
=
&
ul_dci_req
->
ul_dci_pdu_list
[
ul_dci_req
->
numPdus
];
nfapi_nr_ul_dci_request_pdus_t
*
ul_dci_request_pdu
=
&
ul_dci_req
->
ul_dci_pdu_list
[
ul_dci_req
->
numPdus
];
memset
(
ul_dci_request_pdu
,
0
,
sizeof
(
nfapi_nr_ul_dci_request_pdus_t
));
memset
(
ul_dci_request_pdu
,
0
,
sizeof
(
nfapi_nr_ul_dci_request_pdus_t
));
ul_dci_request_pdu
->
PDUType
=
NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE
;
ul_dci_request_pdu
->
PDUType
=
NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE
;
ul_dci_request_pdu
->
PDUSize
=
(
uint8_t
)(
2
+
sizeof
(
nfapi_nr_dl_tti_pdcch_pdu
));
ul_dci_request_pdu
->
PDUSize
=
(
uint8_t
)(
2
+
sizeof
(
nfapi_nr_dl_tti_pdcch_pdu
));
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu
=
&
ul_dci_request_pdu
->
pdcch_pdu
.
pdcch_pdu_rel15
;
pdcch_pdu
=
&
ul_dci_request_pdu
->
pdcch_pdu
.
pdcch_pdu_rel15
;
ul_dci_req
->
numPdus
+=
1
;
ul_dci_req
->
numPdus
+=
1
;
nr_configure_pdcch
(
pdcch_pdu
,
sched_ctrl
->
search_space
,
sched_ctrl
->
coreset
,
scc
,
sched_ctrl
->
active_bwp
);
nr_configure_pdcch
(
pdcch_pdu
,
sched_ctrl
->
search_space
,
sched_ctrl
->
coreset
,
scc
,
sched_ctrl
->
active_bwp
);
pdcch_pdu_bwp_coreset
[
bwpid
][
coresetid
]
=
pdcch_pdu
;
}
LOG_D
(
MAC
,
"Configuring ULDCI/PDCCH in %d.%d
\n
"
,
frame
,
slot
);
LOG_D
(
MAC
,
"Configuring ULDCI/PDCCH in %d.%d
\n
"
,
frame
,
slot
);
...
...
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