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OpenXG-RAN
Commit 9b428e5e authored by Cedric Roux's avatar Cedric Roux
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bugfix: fix timing advance 

- re-use ta_timer
- when ta_timer is running:
  - no TA sent to UE
  - no TA from UE (for UE to have time to apply previous TA command)
- decrease ta_timer every TTI
- be careful to use correct value of ta_update (31 means no TA)

Maybe not correct, to be checked.
parent a9d6e04c
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Showing with 46 additions and 45 deletions
openair1/SCHED/phy_procedures_lte_eNb.c
View file @ 9b428e5e
......@@ -1525,12 +1525,8 @@ void init_te_thread(PHY_VARS_eNB *eNB,pthread_attr_t *attr_te) {
}
void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe) {
void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe)
{
nfapi_rx_indication_pdu_t *pdu;
int timing_advance_update;
......@@ -1551,50 +1547,36 @@ void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe) {
sync_pos = lte_est_timing_advance_pusch(eNB,UE_id);
timing_advance_update = sync_pos - eNB->frame_parms.nb_prefix_samples/4; //to check
// if (timing_advance_update > 10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
// if (timing_advance_update < -10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
switch (eNB->frame_parms.N_RB_DL) {
case 6:
pdu->rx_indication_rel8.timing_advance = timing_advance_update;
break;
case 15:
pdu->rx_indication_rel8.timing_advance = timing_advance_update/2;
break;
case 25:
pdu->rx_indication_rel8.timing_advance = timing_advance_update/4;
break;
case 50:
pdu->rx_indication_rel8.timing_advance = timing_advance_update/8;
break;
case 75:
pdu->rx_indication_rel8.timing_advance = timing_advance_update/12;
break;
case 100:
pdu->rx_indication_rel8.timing_advance = timing_advance_update/16;
break;
case 6: /* nothing to do */ break;
case 15: timing_advance_update /= 2; break;
case 25: timing_advance_update /= 4; break;
case 50: timing_advance_update /= 8; break;
case 75: timing_advance_update /= 12; break;
case 100: timing_advance_update /= 16; break;
default: abort();
}
// put timing advance command in 0..63 range
pdu->rx_indication_rel8.timing_advance += 31;
if (pdu->rx_indication_rel8.timing_advance < 0) pdu->rx_indication_rel8.timing_advance = 0;
if (pdu->rx_indication_rel8.timing_advance > 63) pdu->rx_indication_rel8.timing_advance = 63;
timing_advance_update += 31;
if (timing_advance_update < 0) timing_advance_update = 0;
if (timing_advance_update > 63) timing_advance_update = 63;
pdu->rx_indication_rel8.timing_advance = timing_advance_update;
// estimate UL_CQI for MAC (from antenna port 0 only)
int SNRtimes10 = dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_power[0]) - 200;//(10*eNB->measurements.n0_power_dB[0]);
if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0;
else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255;
else pdu->rx_indication_rel8.ul_cqi=(640+SNRtimes10)/5;
LOG_D(PHY,"[PUSCH %d] Filling RX_indication with SNR %d (%d), timing_advance %d (update %d)\n",
harq_pid,SNRtimes10,pdu->rx_indication_rel8.ul_cqi,pdu->rx_indication_rel8.timing_advance,
timing_advance_update);
eNB->UL_INFO.rx_ind.number_of_pdus++;
pthread_mutex_unlock(&eNB->UL_INFO_mutex);
}
void release_harq(PHY_VARS_eNB *eNB,int UE_id,int tb,uint16_t frame,uint8_t subframe,uint16_t mask) {
......
openair2/LAYER2/MAC/eNB_scheduler_RA.c
View file @ 9b428e5e
......@@ -749,7 +749,7 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
(unsigned short*)&rrc_sdu_length, //
&lcid, // sdu_lcid
255, // no drx
0, // no timing advance
31, // no timing advance
RA_template->cont_res_id, // contention res id
msg4_padding, // no padding
msg4_post_padding);
......@@ -913,7 +913,7 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
(unsigned short*)&rrc_sdu_length, //
&lcid, // sdu_lcid
255, // no drx
0, // no timing advance
31, // no timing advance
RA_template->cont_res_id, // contention res id
msg4_padding, // no padding
msg4_post_padding);
......
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
View file @ 9b428e5e
......@@ -169,7 +169,7 @@ generate_dlsch_header(
last_size=1;
}
if (timing_advance_cmd != 0) {
if (timing_advance_cmd != 31) {
if (first_element>0) {
mac_header_ptr->E = 1;
mac_header_ptr++;
......@@ -457,6 +457,7 @@ schedule_ue_spec(
nfapi_dl_config_request_body_t *dl_req;
nfapi_dl_config_request_pdu_t *dl_config_pdu;
int tdd_sfa;
int ta_update;
#if 0
if (UE_list->head==-1) {
......@@ -816,7 +817,18 @@ schedule_ue_spec(
// check first for RLC data on DCCH
// add the length for all the control elements (timing adv, drx, etc) : header + payload
ta_len = (ue_sched_ctl->ta_update!=0) ? 2 : 0;
if (ue_sched_ctl->ta_timer == 0) {
ta_update = ue_sched_ctl->ta_update;
/* if we send TA then set timer to not send it for a while */
if (ta_update != 31)
ue_sched_ctl->ta_timer = 20;
/* reset ta_update */
ue_sched_ctl->ta_update = 31;
} else {
ta_update = 31;
}
ta_len = (ta_update != 31) ? 2 : 0;
header_len_dcch = 2; // 2 bytes DCCH SDU subheader
......@@ -1094,17 +1106,17 @@ schedule_ue_spec(
sdu_lengths, //
sdu_lcids,
255, // no drx
ue_sched_ctl->ta_update, // timing advance
ta_update, // timing advance
NULL, // contention res id
padding,
post_padding);
//#ifdef DEBUG_eNB_SCHEDULER
if (ue_sched_ctl->ta_update) {
if (ta_update != 31) {
LOG_D(MAC,
"[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_dcch %d, header_dtch %d\n",
module_idP,frameP, UE_id, CC_id, sdu_length_total,num_sdus,sdu_lengths[0],sdu_lcids[0],offset,
ue_sched_ctl->ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
}
//#endif
#ifdef DEBUG_eNB_SCHEDULER
......@@ -1116,6 +1128,7 @@ schedule_ue_spec(
LOG_T(MAC,"\n");
#endif
// cycle through SDUs and place in dlsch_buffer
memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total);
// memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]);
......
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
View file @ 9b428e5e
......@@ -1724,6 +1724,8 @@ int add_new_ue(module_id_t mod_idP, int cc_idP, rnti_t rntiP,int harq_pidP
memset((void*)&UE_list->UE_sched_ctrl[UE_id],0,sizeof(UE_sched_ctrl));
memset((void*)&UE_list->eNB_UE_stats[cc_idP][UE_id],0,sizeof(eNB_UE_STATS));
UE_list->UE_sched_ctrl[UE_id].ta_update = 31;
for (j=0; j<8; j++) {
UE_list->UE_template[cc_idP][UE_id].oldNDI[j] = (j==0)?1:0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
UE_list->UE_template[cc_idP][UE_id].oldNDI_UL[j] = (j==harq_pidP)?0:1; // 1st transmission is with Msg3;
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @ 9b428e5e
......@@ -115,6 +115,8 @@ void rx_sdu(const module_id_t enb_mod_idP,
UE_list->UE_sched_ctrl[UE_id].ul_inactivity_timer = 0;
UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= (~(1<<harq_pid));
/* don't take into account TA if timer is running */
if (UE_list->UE_sched_ctrl[UE_id].ta_timer == 0)
UE_list->UE_sched_ctrl[UE_id].ta_update = timing_advance;
UE_list->UE_sched_ctrl[UE_id].ul_cqi = ul_cqi;
UE_list->UE_sched_ctrl[UE_id].ul_consecutive_errors = 0;
......
openair2/LAYER2/MAC/pre_processor.c
View file @ 9b428e5e
......@@ -894,6 +894,8 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
LOG_D(MAC,"Running preprocessor for UE %d (%x)\n",UE_id,rnti);
// initialize harq_pid and round
if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--;
/*
eNB_UE_stats *eNB_UE_stats;
......
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