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Commit aacf75b2 authored by rmagueta's avatar rmagueta
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Transmission and reception of a fake RA-Msg4

parent 48811d0f
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Showing with 756 additions and 35 deletions
openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
View file @ aacf75b2
......@@ -481,6 +481,7 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint
// start contention resolution timer
ra->RA_contention_resolution_cnt = (nr_rach_ConfigCommon->ra_ContentionResolutionTimer + 1) * 8;
ra->RA_contention_resolution_timer_active = 1;
ra->ra_state = WAIT_CONTENTION_RESOLUTION;
}
......@@ -536,7 +537,7 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources,
}
}
if (prach_resources->init_msg1) {
if (prach_resources->init_msg1 && ra->ra_state != RA_SUCCEEDED) {
if (ra->RA_active == 0) {
/* RA not active - checking if RRC is ready to initiate the RA procedure */
......@@ -625,7 +626,7 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources,
if (ra->RA_window_cnt >= 0 && ra->RA_RAPID_found == 1) {
// Reset RA_active flag: it disables Msg3 retransmission (8.3 of TS 38.213)
nr_ra_succeeded(mod_id, frame, nr_slot_tx);
//nr_ra_succeeded(mod_id, frame, nr_slot_tx);
} else if (ra->RA_window_cnt == 0 && !ra->RA_RAPID_found) {
......
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @ aacf75b2
......@@ -153,6 +153,16 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
case NR_RNTI_CS:
break;
case NR_RNTI_TC:
// we use the initial DL BWP
sps = initialDownlinkBWP->genericParameters.cyclicPrefix == NULL ? 14 : 12;
monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
rel15->rnti = ra->t_crnti;
//rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
//rel15->BWPStart = NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
rel15->dci_length_options[0] = nr_dci_size(scc, mac->scg, def_dci_pdu_rel15, rel15->dci_format_options[0], NR_RNTI_TC, rel15->BWPSize, bwp_id);
break;
case NR_RNTI_SP_CSI:
break;
......@@ -245,14 +255,18 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->ra_SearchSpace){
switch(ra->ra_state){
case WAIT_RAR:
LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space\n");
rel15->num_dci_options = 1;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
config_dci_pdu(mac, rel15, dl_config, NR_RNTI_RA, ss_id);
fill_dci_search_candidates(ss, rel15);
break;
LOG_D(NR_MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space (RA-Msg2)\n");
rel15->num_dci_options = 1;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
config_dci_pdu(mac, rel15, dl_config, NR_RNTI_RA, ss_id);
fill_dci_search_candidates(ss, rel15);
break;
case WAIT_CONTENTION_RESOLUTION:
LOG_E(MAC, "In %s: CB-RA not implemented yet. Should not have fallen in this case.\n", __FUNCTION__);
LOG_D(NR_MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space (RA-Msg4)\n");
rel15->num_dci_options = 1;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
config_dci_pdu(mac, rel15, dl_config, NR_RNTI_TC, ss_id);
fill_dci_search_candidates(ss, rel15);
break;
default:
break;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ aacf75b2
......@@ -73,10 +73,10 @@ int get_rnti_type(NR_UE_MAC_INST_t *mac, uint16_t rnti){
if (rnti == ra->ra_rnti) {
rnti_type = NR_RNTI_RA;
} else if (rnti == ra->t_crnti && ra->ra_state == WAIT_CONTENTION_RESOLUTION) {
rnti_type = NR_RNTI_TC;
} else if (rnti == mac->crnti) {
rnti_type = NR_RNTI_C;
} else if (rnti == ra->t_crnti) {
rnti_type = NR_RNTI_TC;
} else if (rnti == 0xFFFE) {
rnti_type = NR_RNTI_P;
} else if (rnti == 0xFFFF) {
......@@ -515,9 +515,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
// Config PUSCH PDU
ret = nr_config_pusch_pdu(mac, pusch_config_pdu, dci, NULL, rnti, &dci_format);
if (ret != -1 && ra->RA_active && mac->crnti){
nr_ra_succeeded(module_id, frame, slot);
}
//if (ret != -1 && ra->RA_active && mac->crnti){
// nr_ra_succeeded(module_id, frame, slot);
//}
}
......@@ -578,9 +578,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
// Config PUSCH PDU
ret = nr_config_pusch_pdu(mac, pusch_config_pdu, dci, NULL, rnti, &dci_format);
if (ret != -1 && ra->RA_active && mac->crnti){
nr_ra_succeeded(module_id, frame, slot);
}
//if (ret != -1 && ra->RA_active && mac->crnti){
// nr_ra_succeeded(module_id, frame, slot);
//}
}
......@@ -661,6 +661,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
dlsch_config_pdu_1_0->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing;
BWPSize = n_RB_DLBWP;
if(pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition == NULL)
pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition=calloc(1,sizeof(*pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition));
}
/* IDENTIFIER_DCI_FORMATS */
......@@ -770,6 +773,13 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
dl_config->number_pdus = dl_config->number_pdus + 1;
// FIXME: Remove this
if (ra->ra_state == WAIT_CONTENTION_RESOLUTION && rnti == ra->t_crnti){
LOG_I(NR_MAC,"RA-Msg4 was received\n");
nr_ra_succeeded(module_id, frame, slot);
}
break;
}
......@@ -1105,7 +1115,6 @@ int get_n_rb(NR_UE_MAC_INST_t *mac, int rnti_type){
int N_RB = 0, start_RB;
switch(rnti_type) {
case NR_RNTI_RA:
case NR_RNTI_TC:
case NR_RNTI_P: {
NR_BWP_Id_t dl_bwp_id = mac->DL_BWP_Id;
if (mac->DLbwp[dl_bwp_id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero) {
......@@ -1120,6 +1129,7 @@ int get_n_rb(NR_UE_MAC_INST_t *mac, int rnti_type){
case NR_RNTI_SI:
N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
break;
case NR_RNTI_TC:
case NR_RNTI_C:
N_RB = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
break;
......@@ -1392,39 +1402,71 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
break;
case NR_RNTI_TC:
// indicating a DL DCI format 1bit
// indicating a DL DCI format - 1 bit
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment 4 bit
// Time domain assignment - 4 bits
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
// VRB to PRB mapping 1 bit
// VRB to PRB mapping - 1 bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator 1bit
// New data indicator - 1 bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
// Redundancy version 2bit
// Redundancy version - 2 bits
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
// HARQ process number - 4 bits
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index  E2 bits
// Downlink assignment index - 2 bits
pos+=2;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
// TPC command for scheduled PUCCH  E2 bits
// TPC command for scheduled PUCCH - 2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// PDSCH-to-HARQ_feedback timing indicator  E3 bits
// PUCCH resource indicator - 3 bits
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&7;
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
pos+=3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7;
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->format_indicator = %i\n", dci_pdu_rel15->format_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->dai[0].val = %i\n", dci_pdu_rel15->dai[0].val);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->pucch_resource_indicator = %i\n", dci_pdu_rel15->pucch_resource_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = %i\n", dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val);
break;
}
break;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @ aacf75b2
......@@ -568,10 +568,10 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
nr_generate_Msg2(module_idP, CC_id, frameP, slotP);
break;
case Msg4:
//generate_Msg4(module_idP, CC_id, frameP, slotP);
nr_generate_Msg4(module_idP, CC_id, frameP, slotP);
break;
case WAIT_Msg4_ACK:
//check_Msg4_retransmission(module_idP, CC_id, frameP, slotP);
nr_check_Msg4_Ack(module_idP, CC_id, frameP, slotP);
break;
default:
break;
......@@ -1013,6 +1013,637 @@ void nr_generate_Msg2(module_id_t module_idP,
}
}
/*void nr_get_retransmission_timing(frame_t *frameP, sub_frame_t *subframeP) {
*frameP = (*frameP + 1) % 1024;
*subframeP = *subframeP;
return;
}*/
void nr_generate_Msg4(module_id_t module_idP,
int CC_id,
frame_t frameP,
sub_frame_t slotP) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_RA_t *ra = &cc->ra[0];
if (ra->Msg4_frame == frameP && ra->Msg4_slot == slotP ) {
int mcsIndex = 0;
int startSymbolAndLength = 0;
int StartSymbolIndex = -1;
int NrOfSymbols = 14;
int StartSymbolIndex_tmp = 0;
int NrOfSymbols_tmp = 0;
int x_Overhead = 0;
int time_domain_assignment = 0;
long locationAndBandwidth = 0;
uint8_t nr_of_candidates = 0;
uint8_t aggregation_level = 0;
NR_SearchSpace_t *ss = ra->ra_ss;
NR_BWP_Downlink_t *bwp = ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id - 1];
// check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD
// get the BW of the PDCCH for PDCCH size and Msg4 PDSCH size
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int dci10_bw;
if (ra->coreset0_configured == 1) {
AssertFatal(1==0,"This is a standalone condition\n");
}
else { // on configured BWP or initial LDBWP, bandwidth parameters in DCI correspond size of initialBWP
//locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth;
locationAndBandwidth = bwp->bwp_Common->genericParameters.locationAndBandwidth;
dci10_bw = NRRIV2BW(locationAndBandwidth, MAX_BWP_SIZE);
}
nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
// Checking if the DCI allocation is feasible in current subframe
if (dl_req->nPDUs > NFAPI_NR_MAX_DL_TTI_PDUS - 2) {
LOG_I(NR_MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, ra->rnti);
return;
}
find_aggregation_candidates(&aggregation_level, &nr_of_candidates, ss);
NR_ControlResourceSet_t *coreset = get_coreset(bwp, ss, 0 /* common */);
int CCEIndex = allocate_nr_CCEs(nr_mac,
bwp,
coreset,
aggregation_level,
0,
0,
nr_of_candidates);
if (CCEIndex < 0) {
LOG_E(NR_MAC, "%s(): cannot find free CCE for RNTI %04x!\n", __func__, ra->rnti);
return;
}
nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const int bwpid = bwp->bwp_Id;
const int coresetid = coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, bwp);
nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE;
dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu));
dl_req->nPDUs+=1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
LOG_I(NR_MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg4 DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state);
// This code from this point on will not work on initialBWP or CORESET0
AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n");
AssertFatal(ra->secondaryCellGroup, "no secondaryCellGroup for RNTI %04x\n", ra->rnti);
AssertFatal(ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
"downlinkBWP_ToAddModList has %d BWP!\n",
ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
LOG_I(NR_MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW %d\n", dci10_bw);
pdsch_pdu_rel15->pduBitmap = 0;
pdsch_pdu_rel15->rnti = ra->rnti;
// SCF222: PDU index incremented for each PDSCH PDU sent in TX control message. This is used to associate control
// information to data and is reset every slot.
const int pduindex = nr_mac->pdu_index[CC_id]++;
pdsch_pdu_rel15->pduIndex = pduindex;
pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == NULL) {
pdsch_pdu_rel15->mcsTable[0] = 0;
} else {
if (*bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == 0) {
pdsch_pdu_rel15->mcsTable[0] = 1;
} else {
pdsch_pdu_rel15->mcsTable[0] = 2;
}
}
pdsch_pdu_rel15->rvIndex[0] = 0;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
pdsch_pdu_rel15->nrOfLayers = 1;
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0;
pdsch_pdu_rel15->dmrsConfigType = 0;
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 2;
pdsch_pdu_rel15->dmrsPorts = 1;
pdsch_pdu_rel15->resourceAlloc = 1;
pdsch_pdu_rel15->rbStart = 0;
pdsch_pdu_rel15->rbSize = 6;
pdsch_pdu_rel15->VRBtoPRBMapping = 0;
for (int i=0; i<bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) {
startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &StartSymbolIndex_tmp, &NrOfSymbols_tmp);
if (NrOfSymbols_tmp < NrOfSymbols) {
NrOfSymbols = NrOfSymbols_tmp;
StartSymbolIndex = StartSymbolIndex_tmp;
time_domain_assignment = i; // this is short PDSCH added to the config to fit mixed slot
}
}
AssertFatal(StartSymbolIndex >= 0, "StartSymbolIndex is negative\n");
pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex;
pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols);
// Fill PDCCH DL DCI PDU
nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci];
pdcch_pdu_rel15->numDlDci++;
dci_pdu->RNTI = ra->rnti;
dci_pdu->ScramblingId = *scc->physCellId;
dci_pdu->ScramblingRNTI = 0;
dci_pdu->AggregationLevel = aggregation_level;
dci_pdu->CceIndex = CCEIndex;
dci_pdu->beta_PDCCH_1_0 = 0;
dci_pdu->powerControlOffsetSS = 1;
dci_pdu_rel15_t dci_payload;
dci_payload.frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
dci10_bw);
dci_payload.time_domain_assignment.val = time_domain_assignment;
dci_payload.vrb_to_prb_mapping.val = 0;
dci_payload.mcs = pdsch_pdu_rel15->mcsIndex[0];
dci_payload.tb_scaling = 0;
LOG_I(NR_MAC,
"[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n",
dci_payload.frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
dci10_bw,
dci_payload.time_domain_assignment.val,
dci_payload.vrb_to_prb_mapping.val,
dci_payload.mcs,
dci_payload.tb_scaling);
LOG_I(NR_MAC, "Frame %d: Subframe %d : Adding common DL DCI for RNTI %x\n", frameP, slotP, ra->rnti);
const int dci_format = NR_DL_DCI_FORMAT_1_0;
const int rnti_type = NR_RNTI_TC;
LOG_I(NR_MAC,
"[RAPROC] DCI params: rnti 0x%x, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
pdcch_pdu_rel15->dci_pdu[0].RNTI,
rnti_type,
dci_format,
(unsigned long long)pdcch_pdu_rel15->FreqDomainResource,
pdcch_pdu_rel15->StartSymbolIndex,
pdcch_pdu_rel15->DurationSymbols);
fill_dci_pdu_rel15(scc,
ra->secondaryCellGroup,
dci_pdu,
&dci_payload,
dci_format,
rnti_type,
dci10_bw,
ra->bwp_id);
x_Overhead = 0;
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_payload.tb_scaling);
uint8_t payload[] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08};
// DL TX request
tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0];
tx_req->PDU_index = pduindex;
tx_req->num_TLV = 1;
tx_req->TLVs[0].length = 8;
nr_mac->TX_req[CC_id].SFN = frameP;
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP;
memcpy(tx_req->TLVs[0].value.direct, payload, tx_req->TLVs[0].length);
// mark the corresponding RBs as used
uint16_t *vrb_map = cc[CC_id].vrb_map;
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) {
vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1;
}
ra->state = WAIT_Msg4_ACK;
/*
// PREPROCESSOR
NR_UE_info_t *UE_info = &nr_mac->UE_info;
int16_t rrc_sdu_length = 0;
uint16_t msg4_padding = 0;
uint16_t msg4_post_padding = 0;
uint16_t msg4_header = 0;
int UE_id = find_nr_UE_id(module_id, ra->rnti);
if (UE_id < 0) {
LOG_E(NR_MAC, "Can't find UE for t-crnti %x, kill RA procedure for this UE\n", ra->rnti);
nr_clear_ra_proc(module_id, CC_id, frame);
return;
}
nr_mac->pre_processor_dl(module_id, frame, slot);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
// POST processing
struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
AssertFatal(sched_ctrl->time_domain_allocation < tdaList->list.count,
"time_domain_allocation %d>=%d\n",
sched_ctrl->time_domain_allocation,
tdaList->list.count);
const int startSymbolAndLength = tdaList->list.array[sched_ctrl->time_domain_allocation]->startSymbolAndLength;
int startSymbolIndex;
int nrOfSymbols;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
long dmrsConfigType = sched_ctrl->active_bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
uint8_t N_PRB_DMRS = 0;
if (dmrsConfigType==NFAPI_NR_DMRS_TYPE1) {
N_PRB_DMRS = sched_ctrl->numDmrsCdmGrpsNoData * 6;
}
else {
N_PRB_DMRS = sched_ctrl->numDmrsCdmGrpsNoData * 4;
}
uint8_t N_DMRS_SLOT = get_num_dmrs_symbols(NULL,
RC.nrmac[module_id]->common_channels->ServingCellConfigCommon->dmrs_TypeA_Position ,
nrOfSymbols);
sched_ctrl->rbSize = 4;
const uint32_t TBS = nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
sched_ctrl->rbSize,
nrOfSymbols,
N_PRB_DMRS * N_DMRS_SLOT,
0,
0,
1) >> 3;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[sched_ctrl->dl_harq_pid];
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[0];
harq->feedback_slot = pucch->ul_slot;
harq->is_waiting = 1;
UE_info->mac_stats[UE_id].dlsch_rounds[harq->round]++;
ra->harq_pid = sched_ctrl->dl_harq_pid;
LOG_I(NR_MAC, "%4d.%2d RNTI %04x start %d RBS %d MCS %d TBS %d HARQ PID %d round %d NDI %d, feedback slot %d, iswaiting %d\n",
frame, slot, ra->rnti, sched_ctrl->rbStart, sched_ctrl->rbSize, sched_ctrl->mcs,
TBS, sched_ctrl->dl_harq_pid, harq->round, harq->ndi, harq->feedback_slot, harq->is_waiting);
nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu_rel15,
sched_ctrl->search_space,
sched_ctrl->coreset,
scc,
sched_ctrl->active_bwp);
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE;
dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu));
dl_req->nPDUs += 1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
pdcch_pdu_rel15->CoreSetType = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG;
pdsch_pdu_rel15->pduBitmap = 0;
pdsch_pdu_rel15->rnti = ra->rnti;
pdsch_pdu_rel15->pduIndex = nr_mac->pdu_index[0]++;
pdsch_pdu_rel15->BWPSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth,MAX_BWP_SIZE);
pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth,MAX_BWP_SIZE);
pdsch_pdu_rel15->SubcarrierSpacing = sched_ctrl->active_bwp->bwp_Common->genericParameters.subcarrierSpacing;
if (sched_ctrl->active_bwp->bwp_Common->genericParameters.cyclicPrefix) {
pdsch_pdu_rel15->CyclicPrefix = *sched_ctrl->active_bwp->bwp_Common->genericParameters.cyclicPrefix;
} else {
pdsch_pdu_rel15->CyclicPrefix = 0;
}
pdsch_pdu_rel15->NrOfCodewords = 1;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(sched_ctrl->mcs,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = sched_ctrl->mcs;
pdsch_pdu_rel15->mcsTable[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = nr_rv_round_map[0];
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
pdsch_pdu_rel15->nrOfLayers = 1;
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 1;
pdsch_pdu_rel15->dmrsConfigType = dmrsConfigType;
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = sched_ctrl->numDmrsCdmGrpsNoData;
pdsch_pdu_rel15->dmrsPorts = 1;
pdsch_pdu_rel15->resourceAlloc = 1;
pdsch_pdu_rel15->rbStart = sched_ctrl->rbStart;
pdsch_pdu_rel15->rbSize = sched_ctrl->rbSize;
pdsch_pdu_rel15->VRBtoPRBMapping = 0;
pdsch_pdu_rel15->qamModOrder[0] = nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx);
pdsch_pdu_rel15->TBSize[0] = TBS;
pdsch_pdu_rel15->mcsTable[0] = sched_ctrl->mcsTableIdx;
pdsch_pdu_rel15->StartSymbolIndex = startSymbolIndex;
pdsch_pdu_rel15->NrOfSymbols = nrOfSymbols;
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(sched_ctrl->active_bwp->bwp_Dedicated->pdsch_Config->choice.setup, scc->dmrs_TypeA_Position, pdsch_pdu_rel15->StartSymbolIndex+pdsch_pdu_rel15->NrOfSymbols);
LOG_D(NR_MAC,"dlDmrsSymbPos = 0x%x\n", pdsch_pdu_rel15->dlDmrsSymbPos);
// Fill PDCCH DL DCI PDU
nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci];
pdcch_pdu_rel15->numDlDci++;
dci_pdu->RNTI = ra->rnti;
dci_pdu->ScramblingId = *scc->physCellId;
dci_pdu->ScramblingRNTI = 0;
dci_pdu->AggregationLevel = sched_ctrl->aggregation_level;
dci_pdu->CceIndex = sched_ctrl->cce_index;
dci_pdu->beta_PDCCH_1_0 = 0;
dci_pdu->powerControlOffsetSS = 1;
// DCI payload
dci_pdu_rel15_t dci_payload;
memset(&dci_payload, 0, sizeof(dci_pdu_rel15_t));
dci_payload.bwp_indicator.val = sched_ctrl->active_bwp->bwp_Id;
// frequency domain assignment
dci_payload.frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(
pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->BWPSize);
dci_payload.time_domain_assignment.val = sched_ctrl->time_domain_allocation;
dci_payload.mcs = sched_ctrl->mcs;
dci_payload.rv = pdsch_pdu_rel15->rvIndex[0];
dci_payload.harq_pid = 0;
dci_payload.ndi = 0;
dci_payload.dai[0].val = 0;
dci_payload.tpc = 0; // table 7.2.1-1 in 38.213
dci_payload.pucch_resource_indicator = 0;
dci_payload.pdsch_to_harq_feedback_timing_indicator.val = 0;
dci_payload.antenna_ports.val = 0;
dci_payload.dmrs_sequence_initialization.val = pdsch_pdu_rel15->SCID;
fill_dci_pdu_rel15(scc,
ra->secondaryCellGroup,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
NR_DL_DCI_FORMAT_1_0,
NR_RNTI_TC,
pdsch_pdu_rel15->BWPSize,
sched_ctrl->active_bwp->bwp_Id);
LOG_D(NR_MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
LOG_D(NR_MAC,"BWPStart: %i\n", pdcch_pdu_rel15->BWPStart);
LOG_D(NR_MAC,"SubcarrierSpacing: %i\n", pdcch_pdu_rel15->SubcarrierSpacing);
LOG_D(NR_MAC,"CyclicPrefix: %i\n", pdcch_pdu_rel15->CyclicPrefix);
LOG_D(NR_MAC,"StartSymbolIndex: %i\n", pdcch_pdu_rel15->StartSymbolIndex);
LOG_D(NR_MAC,"DurationSymbols: %i\n", pdcch_pdu_rel15->DurationSymbols);
for(int n=0;n<6;n++) LOG_D(NR_MAC,"FreqDomainResource[%i]: %x\n",n, pdcch_pdu_rel15->FreqDomainResource[n]);
LOG_D(NR_MAC,"CceRegMappingType: %i\n", pdcch_pdu_rel15->CceRegMappingType);
LOG_D(NR_MAC,"RegBundleSize: %i\n", pdcch_pdu_rel15->RegBundleSize);
LOG_D(NR_MAC,"InterleaverSize: %i\n", pdcch_pdu_rel15->InterleaverSize);
LOG_D(NR_MAC,"CoreSetType: %i\n", pdcch_pdu_rel15->CoreSetType);
LOG_D(NR_MAC,"ShiftIndex: %i\n", pdcch_pdu_rel15->ShiftIndex);
LOG_D(NR_MAC,"precoderGranularity: %i\n", pdcch_pdu_rel15->precoderGranularity);
LOG_D(NR_MAC,"numDlDci: %i\n", pdcch_pdu_rel15->numDlDci);
NR_UE_ret_info_t *retInfo = &sched_ctrl->retInfo[sched_ctrl->dl_harq_pid];
if (harq->round != 0) { // retransmission
if (sched_ctrl->rbSize != retInfo->rbSize)
LOG_W(NR_MAC,
"retransmission uses different rbSize (%d vs. orig %d)\n",
sched_ctrl->rbSize,
retInfo->rbSize);
if (sched_ctrl->time_domain_allocation != retInfo->time_domain_allocation)
LOG_W(NR_MAC,
"retransmission uses different time_domain_allocation (%d vs. orig %d)\n",
sched_ctrl->time_domain_allocation,
retInfo->time_domain_allocation);
if (sched_ctrl->mcs != retInfo->mcs
|| sched_ctrl->mcsTableIdx != retInfo->mcsTableIdx
|| sched_ctrl->numDmrsCdmGrpsNoData != retInfo->numDmrsCdmGrpsNoData)
LOG_W(NR_MAC,
"retransmission uses different table/MCS/numDmrsCdmGrpsNoData (%d/%d/%d vs. orig %d/%d/%d)\n",
sched_ctrl->mcsTableIdx,
sched_ctrl->mcs,
sched_ctrl->numDmrsCdmGrpsNoData,
retInfo->mcsTableIdx,
retInfo->mcs,
retInfo->numDmrsCdmGrpsNoData);
// we do not have to do anything, since we do not require to get data
// from RLC, encode MAC CEs, or copy data to FAPI structures
LOG_W(NR_MAC, "%d.%2d retransmission UE %d/RNTI %04x\n", frame, slot, UE_id, ra->rnti);
LOG_W(NR_MAC,
"%d.%2d DL retransmission UE %d/RNTI %04x HARQ PID %d round %d NDI %d\n",
frame,
slot,
UE_id,
ra->rnti,
sched_ctrl->dl_harq_pid,
harq->round,
harq->ndi);
} else { // initial transmission
LOG_D(NR_MAC, "[%s] Initial HARQ transmission in %d.%d\n", __FUNCTION__, frame, slot);
// reserve space for timing advance of UE if necessary,
// nr_generate_dlsch_pdu() checks for ta_apply and add TA CE if necessary
const int cont_res_len = 1 + 6;
const int ta_len = (sched_ctrl->ta_apply) ? 2 : 0;
// Get RLC data TODO: remove random data retrieval
int header_length_total = 0;
int header_length_last = 0;
int sdu_length_total = 0;
int num_sdus = 0;
uint16_t sdu_lengths[NB_RB_MAX] = {0};
uint8_t mac_sdus[MAX_NR_DLSCH_PAYLOAD_BYTES];
unsigned char sdu_lcids[NB_RB_MAX] = {0};
const int lcid = DL_SCH_LCID_CCCH;
if (sched_ctrl->num_total_bytes > 0) {
LOG_I(NR_MAC,
"[gNB %d][MSG4] Frame %d : CCCH->DLSCH, Requesting "
"%d bytes from RLC (lcid %d total hdr len %d), TBS: %d \n \n",
module_id,
frame,
TBS - ta_len - header_length_total - sdu_length_total - 3,
lcid,
header_length_total,
TBS);
#if 0
// sdu_lengths[num_sdus] = mac_rrc_data_req(module_id, CC_idP, frameP, CCCH,
// UE_RNTI(module_idP,UE_id),1, // 1 transport block
// &cc[CC_idP].CCCH_pdu.payload[0], 1);
sdu_lengths[num_sdus] = mac_rrc_nr_data_req(module_id, CC_id, frame, CCCH, ra->rnti, 1, // 1 transport block
mac_sdus);
LOG_D(MAC,
"[gNB %d][USER-PLANE DEFAULT DRB] Got %d bytes for DTCH %d \n",
module_id,
sdu_lengths[num_sdus],
lcid);
sdu_lcids[num_sdus] = lcid;
sdu_length_total += sdu_lengths[num_sdus];
header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128);
header_length_total += header_length_last;
num_sdus++;
#else
LOG_I(NR_MAC, "Configuring DL_TX in %d.%d: random data\n", frame, slot);
// fill dlsch_buffer with random data
sdu_lcids[0] = lcid; // DRB
sdu_lengths[0] = 500;
for (int i = 0; i < sdu_lengths[0]; i++)
mac_sdus[i] = (unsigned char) (lrand48()&0xff);
sdu_length_total += sdu_lengths[0];
header_length_total += 2 + (sdu_lengths[0] >= 128);
num_sdus +=1;
#endif
//ue_sched_ctl->uplane_inactivity_timer = 0;
}
UE_info->mac_stats[UE_id].dlsch_total_bytes += TBS;
UE_info->mac_stats[UE_id].lc_bytes_tx[lcid] += sdu_length_total;
// Check if there is data from RLC or CE
const int post_padding = TBS > header_length_total + sdu_length_total + cont_res_len;
LOG_I(NR_MAC, "Configuring DL_TX in %d.%d: TBS %d, header_length_total %d, sdu_length_total %d,cont_res_len %d, post_padding %d \n", frame, slot,
TBS , header_length_total , sdu_length_total ,cont_res_len , post_padding );
// padding param currently not in use
//padding = TBS - header_length_total - sdu_length_total - ta_len - 1;
const int ntx_req = nr_mac->TX_req[CC_id].Number_of_PDUs;
nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[ntx_req];
// pointer to directly generate the PDU into the nFAPI structure
uint32_t *buf = tx_req->TLVs[0].value.direct;
const int offset = nr_write_ce_dlsch_pdu(module_id,
sched_ctrl,
(unsigned char *)buf,
255, // no drx
ra->cont_res_id);
// Padding: fill remainder of DLSCH with 0
if (post_padding > 0) {
for (int j = 0; j < TBS - offset; j++)
buf[offset + j] = 0;
}
// the buffer has been filled by nr_generate_dlsch_pdu(), below we simply
//fill the remaining information
tx_req->PDU_length = TBS;
tx_req->PDU_index = nr_mac->pdu_index[0]++;
tx_req->num_TLV = 1;
tx_req->TLVs[0].length = TBS + 2;
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].SFN = frame;
nr_mac->TX_req[CC_id].Slot = slot;
retInfo->rbSize = sched_ctrl->rbSize;
retInfo->time_domain_allocation = sched_ctrl->time_domain_allocation;
retInfo->mcsTableIdx = sched_ctrl->mcsTableIdx;
retInfo->mcs = sched_ctrl->mcs;
retInfo->numDmrsCdmGrpsNoData = sched_ctrl->numDmrsCdmGrpsNoData;
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
if (frame%100 == 0) {
LOG_I(MAC,
"%d.%d, first 10 payload bytes, TBS size: %d \n",
frame,
slot,
TBS);
for(int i = 0; i < 10; i++)
LOG_I(MAC, "byte %d: %x\n", i, ((uint8_t *) buf)[i]);
}
#endif
}
nr_get_retransmission_timing(&ra->Msg4_frame, &ra->Msg4_slot);
ra->state = WAIT_Msg4_ACK;
LOG_I(NR_MAC, "Retransmission time for Msg4 is %d %d\n", ra->Msg4_frame, ra->Msg4_slot);
*/
}
}
void nr_check_Msg4_Ack(module_id_t module_id,
int CC_id,
frame_t frame,
sub_frame_t slot) {
LOG_W(NR_MAC,"nr_check_Msg4_Ack() is not implemented yet!\n");
gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_RA_t *ra = &cc->ra[0];
ra->state = RA_IDLE;
/*
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
int UE_id = find_nr_UE_id_msg4(module_id, ra->rnti);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int current_harq_pid = ra->harq_pid;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
LOG_D(MAC, "ue %d, rnti %d, harq is waiting %d, round %d, frame %d %d, harq id %d\n", UE_id, ra->rnti, harq->is_waiting, harq->round, frame, slot, current_harq_pid);
if (harq->is_waiting == 0)
{
if ( harq->round == 0)
{
ra->state = IDLE;
UE_info->active[UE_id] = true;
free(ra->preambles.preamble_list);
LOG_I(MAC, "ue %d, rnti %d is active, frame %d %d\n", UE_id, ra->rnti, frame, slot);
}
else
{
ra->state = Msg4;
}
}
*/
}
void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){
NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[CC_id].ra[0];
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ aacf75b2
......@@ -1131,6 +1131,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
break;
case NR_RNTI_TC:
pos = 1;
// indicating a DL DCI format 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator & 1) << (dci_size - pos++);
// Freq domain assignment 0-16 bit
......@@ -1159,9 +1160,27 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
// TPC command for scheduled PUCCH – 2 bits
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc >> (1 - i)) & 1) << (dci_size - pos++);
// PUCCH resource indicator – 3 bits
for (int i = 0; i < 3; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pucch_resource_indicator >> (2 - i)) & 1) << (dci_size - pos++);
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i = 0; i < 3; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val >> (2 - i)) & 1) << (dci_size - pos++);
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->format_indicator = %i\n", dci_pdu_rel15->format_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->dai[0].val = %i\n", dci_pdu_rel15->dai[0].val);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = %i\n", dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val);
break;
}
break;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ aacf75b2
......@@ -490,12 +490,11 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
UE_info->UE_sched_ctrl[UE_id].ta_frame = frameP;
free(ra->preambles.preamble_list);
ra->state = RA_IDLE;
LOG_I(NR_MAC,
"reset RA state information for RA-RNTI %04x/index %d\n",
ra->rnti,
i);
ra->state = Msg4;
ra->Msg4_frame = ( frameP +2 ) % 1024;
ra->Msg4_slot = 1;
LOG_I(MAC, "set RA state to Msg4 for RA-RNTI %04x, msg4 frame %d %d\n", ra->rnti, ra->Msg4_frame, ra->Msg4_slot);
return;
}
}
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ aacf75b2
......@@ -347,12 +347,27 @@ void config_nr_mib(int Mod_idP,
int cellBarred,
int intraFreqReselection);
int nr_write_ce_dlsch_pdu(module_id_t module_idP,
const NR_UE_sched_ctrl_t *ue_sched_ctl,
unsigned char *mac_pdu,
unsigned char drx_cmd,
unsigned char *ue_cont_res_id);
void nr_generate_Msg2(module_id_t module_idP,
int CC_id,
frame_t frameP,
sub_frame_t slotP);
void nr_generate_Msg4(module_id_t module_idP,
int CC_id,
frame_t frameP,
sub_frame_t slotP);
void nr_check_Msg4_Ack(module_id_t module_id,
int CC_id,
frame_t frame,
sub_frame_t slot);
void nr_process_mac_pdu(
module_id_t module_idP,
rnti_t rnti,
......
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