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alex037yang
OpenXG-RAN
Commits
39fa3e00
Commit
39fa3e00
authored
6 years ago
by
Hongzhi Wang
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adding ldpc decoder code rate adaptation
parent
232efe78
dev
1
128-ues
256_QAM_demod
408-reworked
445-LDPC-implementation-on-GPU
459-pusch-based-ta-updates
464-ru_beamforming_in_gpu
464-ru_beamforming_in_gpu-CPUsubfunction
472-add-pusch-dmrs-modes
481-ldpc-decoder-on-gpu
5g_fapi_scf
Fix_SA_SIB1
LTE_TRX_on_single_port
NCTU_CS_ISIP
NCTU_CS_ISIP_CPU
NCTU_CS_ISIP_GPU
NCTU_OpinConnect_LDPC
NR-PHY-MAC-IF-multi-UE
NRPRACH_highSpeed_saankhya
NRUE_usedlschparallel
NR_10MHz
NR_CSI_reporting
NR_DCI_01
NR_DLUL_PF
NR_DLUL_PF_4UL
NR_DLUL_PF_rebased
NR_DL_MIMO
NR_DL_sched_fixes
NR_DL_scheduler
NR_FAPI_beamindex_SSB_RO
NR_FAPI_beamindex_SSB_RO_SEMPROJ
NR_FDD_FIX
NR_FR2_RA
NR_FR2_RRC_SSB
NR_FR2_initsync_fixes
NR_MAC_CE_GlobalEdge
NR_MAC_Multi_Rach_GlobalEdge
NR_MAC_Multi_Rach_GlobalEdge-old
NR_MAC_SSB
NR_MAC_SSB_RO_GlobalEdge
NR_MAC_SSB_RO_UE_IDCC
NR_MAC_SSB_RO_merge
NR_MAC_TCI_UCI_GlobalEdge
NR_MCS_BLER
NR_NGAP
NR_PDCP_noS1
NR_PUCCH_MultiUE
NR_RA_cleanup
NR_RA_updates
NR_RRCConfiguragion_FR2
NR_RRCConfiguration
NR_RRCConfiguration_FR2
NR_RRCConfiguration_S1U
NR_RRCConfiguration_merge_develop
NR_RRCConfiguration_sync_source
NR_RRCConfiguration_trx_thread
NR_RRC_CP_bugfix
NR_RRC_PDCP
NR_RRC_PRACH_procedures
NR_RRC_PRACH_procedures_todevelop
NR_RRC_PUSCH
NR_RRC_TA
NR_RRC_X2AP_AMBR_Change_Global_edge
NR_RRC_X2AP_RemoveHardcodings_GlobalEdge
NR_RRC_config_simplified
NR_RRC_harq
NR_RRC_harq_b
NR_RRC_harq_hacks
NR_RRC_harq_newdcipdu
NR_SA_F1AP_5GRECORDS
NR_SA_F1AP_5GRECORDS_lts
NR_SA_F1AP_RFSIMULATOR
NR_SA_F1AP_RFSIMULATOR2
NR_SA_F1AP_RFSIMULATOR2_SRB
NR_SA_F1AP_RFSIMULATOR3
NR_SA_F1AP_RFSIMULATOR3_tmp
NR_SA_F1AP_RFSIMULATOR3_wf
NR_SA_F1AP_RFSIMULATOR_w5GCN
NR_SA_F1AP_dev
NR_SA_NGAP_RRC
NR_SA_NGAP_RRC_wk42
NR_SA_itti_sim_wk48
NR_SA_itti_sim_wk48_hs
NR_SA_itti_sim_wk48_hs1
NR_SA_w5GCN_new_gtpu
NR_SCHED
NR_SCHED_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ_rebased
NR_SCHED_fixes
NR_SRB_Config
NR_TRX_on_single_port
NR_TRX_on_single_port2
NR_UE_CONFIG_REQ_FIXES
NR_UE_MAC_scheduler
NR_UE_RA_fixes
NR_UE_SA
NR_UE_UL_DCI_improvements
NR_UE_dlsch_bugfix
NR_UE_enable_parallelization
NR_UE_stability_fixes
NR_UL_FAPI_programming
NR_UL_SCFDMA_100MHz
NR_UL_scheduler
NR_UL_scheduler_rebased
NR_UL_scheduling
NR_Wireshark
NR_beam_simulation
NR_beamforming_test
NR_gNB_SCF_Indication
NR_ipaccess_testing
NR_mac_uci_functions_rework
NR_msg2_phytest
NR_scheduling_CSIRS
NR_scheduling_request
NR_scheduling_request2
NR_scheduling_request3
NR_test_S1U_RRC_PRACH_procedures
NR_ue_dlsch_dmrs_cdm
OpInConnect_ISIP
PBCHNRTCFIX
PUSCH_TA_update
RA_CI_test
RFquality
Saankhya_NRPRACH_HighSpeed
UE_DL_DCI_hotfix
add-dmrs-test
addoptions_nr_USRPdevice
bch-fixes-bitmap
benetel_5g_prach_fix
benetel_config_file_fix
benetel_driver_uldl_pf_merge
benetel_driver_update
benetel_fixes
benetel_phase_rotation
benetel_phase_rotation_old
bsr-fix
bugfix-free-ra-process
bugfix-minor-remove-wrong-log
bugfix-nr-bands
bugfix-nr-ldpc-post-processing
bugfix-nr-ldpc-size-typo
bugfix-nr-pdcp-sn-size
bugfix-nr-rate-matching-assertion
bugfix-nr-t-reordering
bugfix-x2-SgNBAdditionRequest
bupt-sa-merge
cce_indexing_fix
cce_indexing_fix2
ci-deploy-asterix
ci-deploy-docker-compose
ci-new-docker-pipeline
ci-rd-july-improvements
ci-reduce-nb-vms
ci-test
ci-ul-iperf-from-trf-container
ci_benetel_test
ci_phytest
ci_quectel_support
ci_test_ra_fr2
ci_vm_resource_fix
clean-5G-scope-round2
cleanup_softmodem_main
constant_power
debug_branch_init_sync
develop
develop-CBRA-v3
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-v3
develop-SA-CBRA
develop-SA-CBRA-CUDU
develop-SA-CBRA-Msg5
develop-SA-CBRA-lts
develop-SA-CBRA-ulsch-lts
develop-SA-RA
develop-SnT
develop-ci
develop-nr
develop-nr-fr2
develop-nr-fr2-rework
develop-nr_cppcheck
develop-oriecpriupdates
develop-sib1
develop-sib1-local
develop-sib1-lts
develop-sib1-update
develop-sib1-update-test1
develop-sib1-update-ue
develop_inria_ci_deployment
develop_inria_ci_deployment_gp
develop_integration_2020_w15
develop_integration_2020_w19
develop_integration_w08
develop_stable
dfts_alternatives
disable_CSI_measrep
dlsch-all-dlslots
dlsch_encode_mthread
dlsch_parallel
docker-improvements-2021-april
docker-no-cache-option
docupdate_tools
dongzhanyi-zte-develop
dongzhanyi-zte-develop2
dreibh/apt-auth-fix
dreibh/device-load-fix
dreibh/device-load-fix-develop-branch
dual-connectivity
edrx
enhance-rfsim
episys-merge
episys/nsa_development
extend_sharedlibusage
extend_sharedlibusage2
fapi_for_dmrs_and_ptrs
feat-mac-sock
feature-4g-sched
feature-nr-4g-nfapi-modifications
feature-support-clang-format
feature/make-s1-mme-port-configurable
feature/make-s1-mme-port-configurable-with-astyle-fixes
fembms-enb-ue
fft_bench_hotfix
finalize-oaicn-integration
firas
fix-ci-tun
fix-clock-source
fix-itti-segv
fix-l2-sim
fix-limeSDR-compile
fix-nr-pdcp-timer
fix-nr-rlc-range-nack
fix-quectel
fix-realtime
fix-softmodem-restart
fix-warnings
fix-x2-without-gnb
fix_NR_DLUL_PF
fix_NR_DLUL_PF_benchmark
fix_coreset_dmrs_idx
fix_do_ra_data
fix_pdsch_low_prb
fix_rb_corruption
fix_reestablishment
fix_rfsim_mimo
fix_rrc_x2_ticking
fixes-CE-RLC-PDU-size
fixes-mac-sched-nfapi
fixes-mac-sched-tun
fixes-tun
fixgtpu
flexran-apps
flexran-improvements
flexran-repair-mme-mgmt
fr2-hw-test
fujitsu_lte_contribution
fujitsu_lte_contribution-128
gNB-nrUE-USRP
generate_push_ptrs
git-dashboard
gnb-freerun-txru
gnb-n300-fixes
gnb-only-test
gnb-realtime-hotfix
gnb-realtime-quickfix
gnb-threadpool
hack-exit-gnb-when-no-enb-nsa
harq-hotfix
hotfix-minor-remove-nr-rlc-cppcheck-error
hotfix-nr-rlc-tick
hotfix-ocp-executable
hotfix-ue-musim-compilation
hotfix_usrp_lib
improve_build_nr_lte_merge
improve_nr_modulation
improve_ue_stability
integ-w13-test-rt-issue
integration-develop-nr-2019w45
integration_2020_wk15
integration_2020_wk40
integration_2020_wk41
integration_2020_wk42_2
integration_2020_wk45
integration_2020_wk45_2
integration_2020_wk46
integration_2020_wk46_2
integration_2020_wk47
integration_2020_wk48
integration_2020_wk48_2
integration_2020_wk49
integration_2020_wk50
integration_2020_wk50_1
integration_2020_wk51
integration_2020_wk51_2
integration_2021_wk02
integration_2021_wk02_wMR988
integration_2021_wk04
integration_2021_wk05
integration_2021_wk06
integration_2021_wk06_MR978
integration_2021_wk06_b
integration_2021_wk06_c
integration_2021_wk08
integration_2021_wk08_2
integration_2021_wk08_MR963
integration_2021_wk09
integration_2021_wk09_b
integration_2021_wk10
integration_2021_wk10_b
integration_2021_wk11
integration_2021_wk12
integration_2021_wk12_b
integration_2021_wk13_a
integration_2021_wk13_b
integration_2021_wk13_b_fix_tdas
integration_2021_wk13_b_fixed
integration_2021_wk13_c
integration_2021_wk14_a
integration_2021_wk15_a
integration_2021_wk16
integration_2021_wk17_a
integration_w5GC_CBRA_test
inter-RRU-final
inter-RRU-nr
inter-RRU-oairu
inter-rru-UE
interoperability-test
isip_nr
itti-enhancement
l2-fixes
ldpc-dec-layering
ldpc-decoder-codegen
ldpc-decoder-codegen2
ldpc-decoder-improvements
ldpc-offload
ldpc_short_codeword_fixes
load_gnb
lte-ulsch-bugfix
lte_uplink_improvement
mac-fixes-wk45_2
mbms-fix-develop-nr
merging-2019-w51-to-develop-nr
migrate-cpp-check-container
minor-fix-doc-basic-sim
mosaic5g-oai-ran
mosaic5g-oai-sim
msg4_phy_0303_lfq
multiple_ssb_sib1_bugfix
nasmesh_kernel_5.8
new-gtpu
new_rlc_2020
nfapi-bugfix
nfapi_nr_arch_mod
nfapi_nr_develop
nfapi_nr_develop_new
ngap-dlul
ngap-support
ngap-w48-merge2
ngap-wf
ngap-wf-1120
ngap-wf-1120-srb
ngap-wf-1120-srb-gtp
ngap-wf-1120-srb-gtp-hs
ngap-wf-1120-srb-gtp-hs1
ngap-wf-1120-srb-gtp-hs2
ngap-wf-1120-srb-gtp-yhz
ngap-wf-1203-yunsdr
ngap-wf-liuyu
ngap_lfq_1120
ngap_merge
noCore
nr-bsr-fix
nr-coreset-bug-fix
nr-dl-mimo-2layer
nr-dlsch-multi-thread
nr-dlsch-thread
nr-dmrs-fixes
nr-dual-connectivity
nr-interdigital-test
nr-ip-uplink-noS1
nr-mac-pdu-wireshark
nr-mac-remove-ue-list
nr-pdcp
nr-pdcp-improvements
nr-pdcp-nea2-security
nr-pdcp-nia2-integrity
nr-pdcp-srb-integrity
nr-pdsch-extraction-bugfix
nr-physim-update
nr-ra-fix
nr-rlc-am-bugfix-w44
nr-rlc-bugfix-w44
nr-ssb-measurements
nr-stats-print
nr-timing-measurement
nr-timing-measurement-merge
nr-ue-buffer-status
nr-uldci
nrPBCHTCFix
nrPbchTcFix
nrUE
nrUE-hs
nrUE-upper-layer
nr_beamforming
nr_bsr
nr_csi_newbranch
nr_demo_wsa2019
nr_dl_dmrs_type2
nr_dl_pf
nr_dl_pf2
nr_dl_ul_ptrs
nr_dlsch_parallel_measurements
nr_dlsim_plot
nr_fapi_for_push_tmp
nr_fdd_if_fix
nr_fix_easycppcheck
nr_flexible_NRBDL
nr_improve_build_procedures
nr_increase_tp
nr_pdcch_testing
nr_pdcch_updates
nr_polar_decoder_improvement
nr_power_measurement_fixes
nr_prach
nr_prach_fr2
nr_pucch
nr_pucch2
nr_segmentation_fixes
nr_sim_fix
nr_tdd_configuration
nr_ue_msg3
nr_ue_pdcp_fix
nr_ue_tti_cleanup
nr_ul_pf
nr_ul_scfdma
nr_vcd
nrue-multi-thread
nrue_msg2_reception
nsa-ue
nsa_remove_band_hardcodings
oai-sim
oai-ubuntu-docker
oai-ubuntu-docker-for-lmssdr
oairu
oairu-dockerfile-support
oc-docker-october-improvements
openxg/develop
pdcp-benchmark
pdsch-ch-est
physim-build-deploy
polar8
prb_based_dl_channel_estimation
ptrs_rrc_config
pusch-mthread-scaling-fix
pusch-retrans-fix-ue
ra-dl-ul
recursive-cmake
reduce_memory_footprint
remove-ci-workaround
remove_nos1_hack_pdcp
remove_x2_gnb_hardcoding
repair-TA
revert-f5c94279
revert_memcpy
rh-ci-add-ue-parallelization
rh_ci_add_runtime_stats
rh_ci_add_uldlharq_stats
rh_ci_fix_autoterminate
rh_ci_fr1_update
rh_ci_gsheet_rt_monitoring
rh_ci_nsa2jenkins
rh_ci_nsa_test_n310
rh_ci_oc
rh_ci_phy_test_improve
rh_ci_py
rh_ci_ra_fr2
rh_ci_rfsim_ra
rh_ci_ue_parallel
rh_doc_update_3
rh_fr1_newjenkins
rh_fr1_update
rh_gnb_compile_fix
rh_wk50_debug
rlc-v2-bugfix-status-reporting
rlc-v2-tick
rlc_v2_coverity_fixes
rohan_ulsim2RxFix
rrc-enb-phy-testmode
ru-parallel-beamforming
runel
runel-reverse-test
s1-subnormal_rewrite
s1_subnormal
s1_subnormal-robert
s1ap-bugfix-rab_setup
sa-demo
sa-demo-hs
sa-merge-rrc-srb
sa-msg4
sa-msg4-rrc
sa-msg4-rrc-yihz
sa-msg4-rrc-yihz-hs
sa_rrc_yihz
sanitize-address
sanitize-v1
sanitize-v1-tmp
sarma_pvnp_oai
sim-channels
small-bugfixes-w40
small-config-change
small_nr_bugfixes
smallcleanup
softmodem_cleanup
split73
t-gnb-tracer
test-panos
test-x310-perf
test_nsa_gtpu_fix
test_rt-fix_phy-test
testing_2symb_pdcch
testing_with_external_txdata
thread-pool
tools_5Gadapt
tp-ota-test
trx_thread_param
trx_write_thread
ue-csi
ue-dci-false-detection
ue-fixes
ue-fixes-ota
ue-pdsch-pusch-parallel
ue-race-fix
ue-updates-runel-test
ue_adjust_gain
ue_beam_selection
ue_dlsch-multi-threading
ue_dlsch_decoding_ldpc_offload
ue_nfapi_mch
uhd_priority_set_cleanup
ul-freq-iq-samps-to-file
ul_dl_dci_same_slot
ul_harq
ulsch_decode_mthread
ulsim_changes
update-to-2019-march-june-release
usrp_fix_adc_shift_and_pps_sync
usrp_gpio_test
usrp_x400
wf-sa-rrc
wireshark-T-hack-ueid
wireshark-log-scheduling-requests
wk11-with-phytest
x2-endc-processing
xiangwab
xiangwan
xw2
yihongzheng_srb
zzs
2021.wk14_a
2021.wk13_d
2021.wk13_c
2021.w16
2021.w15
2021.w14
2021.w13_a
2021.w12
2021.w11
2021.w10
2021.w09
2021.w08
2021.w06
2021.w05
2021.w04
2021.w02
2020.w51_2
2020.w51
2020.w50
2020.w49
2020.w48_2
2020.w48
2020.w47
2020.w46_2
2020.w46
2020.w45_2
2020.w45
2020.w44
2020.w42_2
2020.w42
2020.w41
2020.w39
2020.w38
2020.w37
2020.w36
2020.w34
2020.w33
2020.w31
2020.w30
2020.w29
2020.w28
2020.w26
2020.w25
2020.w24
2020.w23
2020.w22
2020.w19
2020.w17
2020.w16
2020.w15
2020.w11
2020.w09
2020.w06
2020.w05
2020.w04
2020.w03
nr-ip-over-lte
nr-ip-over-lte-v.1.5
nr-ip-over-lte-v.1.4
nr-ip-over-lte-v.1.3
nr-ip-over-lte-v.1.2
nr-ip-over-lte-v.1.1
nr-ip-over-lte-v.1.0
develop-nr-2020w03
develop-nr-2020w02
develop-nr-2019w51
develop-nr-2019w50
develop-nr-2019w48
develop-nr-2019w47
develop-nr-2019w45
develop-nr-2019w43
develop-nr-2019w42
develop-nr-2019w40
develop-nr-2019w28
develop-nr-2019w23
benetel_phase_rotation
benetel_gnb_rel_1.0
benetel_enb_rel_1.0
No related merge requests found
Changes
5
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Showing
5 changed files
with
70 additions
and
56 deletions
+70
-56
openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c
openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c
+1
-1
openair1/PHY/CODING/nr_rate_matching.c
openair1/PHY/CODING/nr_rate_matching.c
+2
-0
openair1/PHY/CODING/nr_segmentation.c
openair1/PHY/CODING/nr_segmentation.c
+1
-1
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+18
-7
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+48
-47
No files found.
openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.c
View file @
39fa3e00
...
@@ -54,7 +54,7 @@ int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t*
...
@@ -54,7 +54,7 @@ int32_t nrLDPC_decoder(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t*
t_nrLDPC_lut
lut
;
t_nrLDPC_lut
lut
;
t_nrLDPC_lut
*
p_lut
=
&
lut
;
t_nrLDPC_lut
*
p_lut
=
&
lut
;
printf
(
"p_procBuf->cnProcBuf = %p
\n
"
,
p_procBuf
->
cnProcBuf
);
//
printf("p_procBuf->cnProcBuf = %p\n", p_procBuf->cnProcBuf);
// Initialize decoder core(s) with correct LUTs
// Initialize decoder core(s) with correct LUTs
numLLR
=
nrLDPC_init
(
p_decParams
,
p_lut
);
numLLR
=
nrLDPC_init
(
p_decParams
,
p_lut
);
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/CODING/nr_rate_matching.c
View file @
39fa3e00
...
@@ -182,6 +182,7 @@ int nr_rate_matching_ldpc_rx(uint8_t Ilbrm,
...
@@ -182,6 +182,7 @@ int nr_rate_matching_ldpc_rx(uint8_t Ilbrm,
#endif
#endif
}
}
if
(
rvidx
!=
0
){
while
(
k
<
E
)
{
while
(
k
<
E
)
{
for
(
ind
=
0
;
(
ind
<
Ncb
)
&&
(
k
<
E
);
ind
++
)
{
for
(
ind
=
0
;
(
ind
<
Ncb
)
&&
(
k
<
E
);
ind
++
)
{
if
(
soft_input
[
ind
]
!=
NR_NULL
)
{
if
(
soft_input
[
ind
]
!=
NR_NULL
)
{
...
@@ -200,6 +201,7 @@ int nr_rate_matching_ldpc_rx(uint8_t Ilbrm,
...
@@ -200,6 +201,7 @@ int nr_rate_matching_ldpc_rx(uint8_t Ilbrm,
#endif
#endif
}
}
}
}
}
return
0
;
return
0
;
}
}
This diff is collapsed.
Click to expand it.
openair1/PHY/CODING/nr_segmentation.c
View file @
39fa3e00
...
@@ -156,7 +156,7 @@ else
...
@@ -156,7 +156,7 @@ else
if
(
*
F
>
0
)
{
if
(
*
F
>
0
)
{
for
(
k
=
Kprime
>>
3
;
k
<
(
*
K
)
>>
3
;
k
++
)
{
for
(
k
=
Kprime
>>
3
;
k
<
(
*
K
)
>>
3
;
k
++
)
{
output_buffers
[
r
][
k
]
=
NR_NULL
;
output_buffers
[
r
][
k
]
=
0
;
//printf("r %d filler bits [%d] = %d Kprime %d \n", r,k, output_buffers[r][k], Kprime);
//printf("r %d filler bits [%d] = %d Kprime %d \n", r,k, output_buffers[r][k], Kprime);
}
}
}
}
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
View file @
39fa3e00
...
@@ -277,17 +277,18 @@ int nr_dlsch_encoding(unsigned char *a,
...
@@ -277,17 +277,18 @@ int nr_dlsch_encoding(unsigned char *a,
nfapi_nr_dl_config_dlsch_pdu_rel15_t
rel15
=
dlsch
->
harq_processes
[
harq_pid
]
->
dlsch_pdu
.
dlsch_pdu_rel15
;
nfapi_nr_dl_config_dlsch_pdu_rel15_t
rel15
=
dlsch
->
harq_processes
[
harq_pid
]
->
dlsch_pdu
.
dlsch_pdu_rel15
;
uint16_t
nb_rb
=
rel15
.
n_prb
;
uint16_t
nb_rb
=
rel15
.
n_prb
;
uint8_t
nb_symb_sch
=
rel15
.
nb_symbols
;
uint8_t
nb_symb_sch
=
rel15
.
nb_symbols
;
uint32_t
A
,
Z
;
uint32_t
A
,
Z
,
F
=
0
;
uint32_t
*
pz
=
&
Z
;
uint32_t
*
pz
=
&
Z
;
uint8_t
mod_order
=
rel15
.
modulation_order
;
uint8_t
mod_order
=
rel15
.
modulation_order
;
uint16_t
Kr
=
0
,
r
,
r_offset
=
0
,
Kr_bytes
;
uint16_t
Kr
=
0
,
r
,
r_offset
=
0
,
Kr_bytes
;
uint8_t
*
d_tmp
[
MAX_NUM_DLSCH_SEGMENTS
];
uint8_t
*
d_tmp
[
MAX_NUM_DLSCH_SEGMENTS
];
uint8_t
kb
,
BG
=
1
;
uint8_t
BG
=
1
;
uint32_t
E
;
uint32_t
E
;
uint8_t
Ilbrm
=
0
;
uint8_t
Ilbrm
=
0
;
uint32_t
Tbslbrm
=
950984
;
//max tbs
uint32_t
Tbslbrm
=
950984
;
//max tbs
uint8_t
nb_re_dmrs
=
rel15
.
nb_re_dmrs
;
uint8_t
nb_re_dmrs
=
rel15
.
nb_re_dmrs
;
uint16_t
length_dmrs
=
1
;
uint16_t
length_dmrs
=
1
;
float
Coderate
=
0
.
0
;
/*
/*
uint8_t *channel_input[MAX_NUM_DLSCH_SEGMENTS]; //unsigned char
uint8_t *channel_input[MAX_NUM_DLSCH_SEGMENTS]; //unsigned char
...
@@ -337,18 +338,20 @@ int nr_dlsch_encoding(unsigned char *a,
...
@@ -337,18 +338,20 @@ int nr_dlsch_encoding(unsigned char *a,
pz
,
pz
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
F
);
&
dlsch
->
harq_processes
[
harq_pid
]
->
F
);
kb
=
dlsch
->
harq_processes
[
harq_pid
]
->
K
/
(
*
pz
);
F
=
dlsch
->
harq_processes
[
harq_pid
]
->
F
;
if
(
kb
==
22
){
Coderate
=
(
float
)
A
/
(
float
)
G
;
BG
=
1
;
if
((
A
<=
292
)
||
((
A
<=
3824
)
&&
(
Coderate
<=
0
.
6667
))
||
Coderate
<=
0
.
25
){
BG
=
2
;
}
}
else
{
else
{
BG
=
2
;
BG
=
1
;
}
}
Kr
=
dlsch
->
harq_processes
[
harq_pid
]
->
K
;
Kr
=
dlsch
->
harq_processes
[
harq_pid
]
->
K
;
Kr_bytes
=
Kr
>>
3
;
Kr_bytes
=
Kr
>>
3
;
//printf("segment Z %d k
b %d k %d Kr %d BG %d\n", *pz,kb
,dlsch->harq_processes[harq_pid]->K,Kr,BG);
//printf("segment Z %d k
%d Kr %d BG %d\n", *pz
,dlsch->harq_processes[harq_pid]->K,Kr,BG);
//start_meas(te_stats);
//start_meas(te_stats);
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
...
@@ -393,6 +396,14 @@ int nr_dlsch_encoding(unsigned char *a,
...
@@ -393,6 +396,14 @@ int nr_dlsch_encoding(unsigned char *a,
}
}
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
if
(
dlsch
->
harq_processes
[
harq_pid
]
->
F
>
0
)
{
for
(
int
k
=
(
Kr
-
F
-
2
*
(
*
pz
));
k
<
Kr
-
2
*
(
*
pz
);
k
++
)
{
dlsch
->
harq_processes
[
harq_pid
]
->
d
[
r
][
k
]
=
NR_NULL
;
//if (k<(Kr-F+8))
//printf("r %d filler bits [%d] = %d \n", r,k, dlsch->harq_processes[harq_pid]->d[r][k]);
}
}
#ifdef DEBUG_DLSCH_CODING
#ifdef DEBUG_DLSCH_CODING
printf
(
"Rate Matching, Code segment %d (coded bits (G) %d,unpunctured/repeated bits per code segment %d,mod_order %d, nb_rb %d)...
\n
"
,
printf
(
"Rate Matching, Code segment %d (coded bits (G) %d,unpunctured/repeated bits per code segment %d,mod_order %d, nb_rb %d)...
\n
"
,
r
,
r
,
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
View file @
39fa3e00
...
@@ -218,8 +218,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
...
@@ -218,8 +218,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint32_t
A
,
E
;
uint32_t
A
,
E
;
uint32_t
G
;
uint32_t
G
;
uint32_t
ret
,
offset
;
uint32_t
ret
,
offset
;
int32_t
no_iteration_ldpc
;
int32_t
no_iteration_ldpc
,
length_dec
;
//short dummy_w[MAX_NUM_DLSCH_SEGMENTS][3*(8448+64)];
uint32_t
r
,
r_offset
=
0
,
Kr
=
8424
,
Kr_bytes
,
K_bytes_F
,
err_flag
=
0
;
uint32_t
r
,
r_offset
=
0
,
Kr
=
8424
,
Kr_bytes
,
K_bytes_F
,
err_flag
=
0
;
uint8_t
crc_type
;
uint8_t
crc_type
;
int8_t
llrProcBuf
[
OAI_LDPC_MAX_NUM_LLR
]
__attribute__
((
aligned
(
32
)));
int8_t
llrProcBuf
[
OAI_LDPC_MAX_NUM_LLR
]
__attribute__
((
aligned
(
32
)));
...
@@ -233,17 +232,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
...
@@ -233,17 +232,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
int8_t
l
[
68
*
384
];
int8_t
l
[
68
*
384
];
//__m128i l;
//__m128i l;
int16_t
inv_d
[
68
*
384
];
int16_t
inv_d
[
68
*
384
];
// int16_t *p_invd =&inv_d;
uint8_t
kc
;
uint8_t
kb
,
kc
;
uint8_t
Ilbrm
=
0
;
uint8_t
Ilbrm
=
0
;
uint32_t
Tbslbrm
=
950984
;
uint32_t
Tbslbrm
=
950984
;
uint16_t
nb_rb
=
30
;
//to update
uint16_t
nb_rb
=
30
;
//to update
//uint16_t nb_symb_sch = 12;
uint8_t
nb_re_dmrs
=
6
;
uint8_t
nb_re_dmrs
=
6
;
uint16_t
length_dmrs
=
1
;
uint16_t
length_dmrs
=
1
;
double
Coderate
=
0
.
0
;
uint32_t
i
,
j
;
uint32_t
i
,
j
;
// uint32_t k;
__m128i
*
pv
=
(
__m128i
*
)
&
z
;
__m128i
*
pv
=
(
__m128i
*
)
&
z
;
__m128i
*
pl
=
(
__m128i
*
)
&
l
;
__m128i
*
pl
=
(
__m128i
*
)
&
l
;
...
@@ -322,21 +319,41 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
...
@@ -322,21 +319,41 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
printf
(
"K %d C %d Z %d nl %d
\n
"
,
harq_process
->
K
,
harq_process
->
C
,
p_decParams
->
Z
,
harq_process
->
Nl
);
printf
(
"K %d C %d Z %d nl %d
\n
"
,
harq_process
->
K
,
harq_process
->
C
,
p_decParams
->
Z
,
harq_process
->
Nl
);
#endif
#endif
}
}
Coderate
=
(
float
)
A
/
(
float
)
G
;
kb
=
harq_process
->
K
/
harq_process
->
Z
;
if
((
A
<=
292
)
||
((
A
<=
3824
)
&&
(
Coderate
<=
0
.
6667
))
||
Coderate
<=
0
.
25
){
if
(
kb
==
22
){
p_decParams
->
BG
=
2
;
p_decParams
->
BG
=
1
;
if
(
Coderate
<
0
.
3333
){
p_decParams
->
R
=
15
;
kc
=
52
;
}
else
if
(
Coderate
<
0
.
6667
){
p_decParams
->
R
=
13
;
p_decParams
->
R
=
13
;
kc
=
68
;
kc
=
32
;
}
else
{
p_decParams
->
R
=
23
;
kc
=
17
;
}
}
}
else
{
else
{
p_decParams
->
BG
=
2
;
p_decParams
->
BG
=
1
;
if
(
Coderate
<
0
.
6667
){
p_decParams
->
R
=
13
;
p_decParams
->
R
=
13
;
kc
=
52
;
kc
=
68
;
}
}
else
if
(
Coderate
<
0
.
8889
){
p_decParams
->
R
=
23
;
kc
=
35
;
}
else
{
p_decParams
->
R
=
89
;
kc
=
27
;
}
}
//printf("coderate %f kc %d \n", Coderate, kc);
p_decParams
->
numMaxIter
=
dlsch
->
max_ldpc_iterations
;
p_decParams
->
numMaxIter
=
dlsch
->
max_ldpc_iterations
;
Kr
=
p_decParams
->
Z
*
kb
;
p_decParams
->
outMode
=
0
;
p_decParams
->
outMode
=
0
;
...
@@ -453,54 +470,38 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
...
@@ -453,54 +470,38 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
memset
(
harq_process
->
c
[
r
],
0
,
Kr_bytes
);
memset
(
harq_process
->
c
[
r
],
0
,
Kr_bytes
);
// printf("done\n");
// printf("done\n");
if
(
harq_process
->
C
==
1
)
if
(
harq_process
->
C
==
1
)
{
crc_type
=
CRC24_A
;
crc_type
=
CRC24_A
;
else
length_dec
=
harq_process
->
B
;
}
else
{
crc_type
=
CRC24_B
;
crc_type
=
CRC24_B
;
length_dec
=
(
harq_process
->
B
+
24
*
harq_process
->
C
)
/
harq_process
->
C
;
}
if
(
err_flag
==
0
)
{
if
(
err_flag
==
0
)
{
/*
LOG_I(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS,
harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations);
*/
#if UE_TIMING_TRACE
#if UE_TIMING_TRACE
start_meas
(
dlsch_turbo_decoding_stats
);
start_meas
(
dlsch_turbo_decoding_stats
);
#endif
#endif
//LOG_E(PHY,"AbsSubframe %d.%d Start
turbo
segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A);
//LOG_E(PHY,"AbsSubframe %d.%d Start
LDPC
segment %d/%d A %d ",frame%1024,nr_tti_rx,r,harq_process->C-1, A);
//printf("harq process dr iteration %d\n", p_decParams->numMaxIter);
//printf("harq process dr iteration %d\n", p_decParams->numMaxIter);
for
(
int
cnt
=
0
;
cnt
<
(
kc
-
2
)
*
p_decParams
->
Z
;
cnt
++
){
inv_d
[
cnt
]
=
(
1
)
*
harq_process
->
d
[
r
][
cnt
];
}
/*for (int cnt =0; cnt < 16; cnt++){
printf("dr %d inv_d %d \n", harq_process->d[r][cnt], inv_d[cnt]);
}
printf(" \n");
printf("end dr \n");
for (int cnt =(50*p_decParams->Z-16) ; cnt < 50*p_decParams->Z; cnt++){
printf("%d ", harq_process->d[r][cnt]);
}
printf(" \n");*/
memset
(
pv
,
0
,
2
*
harq_process
->
Z
*
sizeof
(
int16_t
));
memset
(
pv
,
0
,
2
*
harq_process
->
Z
*
sizeof
(
int16_t
));
//memset(pl,0,2*p_decParams->Z*sizeof(int8_t));
//memset(pl,0,2*p_decParams->Z*sizeof(int8_t));
memset
((
pv
+
K_bytes_F
),
127
,
harq_process
->
F
*
sizeof
(
int16_t
));
memset
((
pv
+
K_bytes_F
),
127
,
harq_process
->
F
*
sizeof
(
int16_t
));
for
(
i
=
((
2
*
p_decParams
->
Z
)
>>
3
),
j
=
0
;
i
<
K_bytes_F
+
((
2
*
p_decParams
->
Z
)
>>
3
)
;
i
++
,
j
++
)
for
(
i
=
((
2
*
p_decParams
->
Z
)
>>
3
),
j
=
0
;
i
<
K_bytes_F
;
i
++
,
j
++
)
{
{
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
inv_d
[
8
*
j
]));
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
harq_process
->
d
[
r
]
[
8
*
j
]));
}
}
for
(
i
=
Kr_bytes
+
((
2
*
p_decParams
->
Z
)
>>
3
),
j
=
Kr_bytes
;
i
<
((
kc
*
p_decParams
->
Z
)
>>
3
);
i
++
,
j
++
)
for
(
i
=
Kr_bytes
,
j
=
K_bytes_F
-
((
2
*
p_decParams
->
Z
)
>>
3
)
;
i
<
((
kc
*
p_decParams
->
Z
)
>>
3
);
i
++
,
j
++
)
{
{
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
inv_d
[
8
*
j
]));
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
harq_process
->
d
[
r
]
[
8
*
j
]));
}
}
for
(
i
=
0
,
j
=
0
;
j
<
((
kc
*
p_decParams
->
Z
)
>>
4
);
i
+=
2
,
j
++
)
for
(
i
=
0
,
j
=
0
;
j
<
((
kc
*
p_decParams
->
Z
)
>>
4
);
i
+=
2
,
j
++
)
...
@@ -517,8 +518,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
...
@@ -517,8 +518,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
p_procTime
);
p_procTime
);
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if
(
check_crc
((
uint8_t
*
)
llrProcBuf
,
harq_process
->
B
,
harq_process
->
F
,
crc_type
))
{
if
(
check_crc
((
uint8_t
*
)
llrProcBuf
,
length_dec
,
harq_process
->
F
,
crc_type
))
{
printf
(
"
CRC OK
\n
"
);
printf
(
"
Segment %d CRC OK
\n
"
,
r
);
ret
=
2
;
ret
=
2
;
}
}
else
{
else
{
...
...
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Click to expand it.
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