Enabled UE to process RX and TX in every DL or UL (or mixed) slot respectivey

- the commit fixes also the selection of the thread_id in TX procedures
- DCI configuration is currently limited to slot 1 and 7

executables/nr-ue.c

@@ -373,8 +373,11 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
   nr_dcireq_t dcireq;
   nr_scheduled_response_t scheduled_response;
 
+  fapi_nr_config_request_t *cfg = &UE->nrUE_config;
+  int tx_slot_type = nr_ue_slot_select(cfg, proc->frame_tx, proc->nr_tti_tx);
+
   // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI
-  if (proc->nr_tti_tx == 8 || proc->nr_tti_tx == 19 || UE->frame_parms.frame_type == FDD){
+  if (tx_slot_type == NR_UPLINK_SLOT || tx_slot_type == NR_MIXED_SLOT){
 
     mod_id = UE->Mod_id;
 
@@ -403,7 +406,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
     rvidx = 0;
     //------------------------------------------------------------------------------//
 
-    scheduled_response.ul_config->slot = 8;
+    scheduled_response.ul_config->slot = proc->nr_tti_tx;
     scheduled_response.ul_config->number_pdus = 1;
     scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
     scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.rnti = n_rnti;
@@ -420,7 +423,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
     nr_ue_scheduled_response(&scheduled_response);
 
     if (UE->mode != loop_through_memory) {
-      uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_tx];
+      uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_rx];
       phy_procedures_nrUE_TX(UE,proc,0,thread_id);
     }
   }
@@ -430,12 +433,13 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
 
   nr_dcireq_t dcireq;
   nr_scheduled_response_t scheduled_response;
+  fapi_nr_config_request_t *cfg = &UE->nrUE_config;
+  int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx);
   uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period;
 
   //program DCI for slot 1
   //TODO: all of this has to be moved to the MAC!!!
-  // Note: temp hardcoded slot 7 for RAR
-  if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || proc->nr_tti_rx == 7 || UE->frame_parms.frame_type == FDD){
+  if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){
     dcireq.module_id = UE->Mod_id;
     dcireq.gNB_index = 0;
     dcireq.cc_id     = 0;
@@ -453,10 +457,8 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
     scheduled_response.slot = proc->nr_tti_rx;
 
     nr_ue_scheduled_response(&scheduled_response);
-  }
 
   // Process Rx data for one sub-frame
-  if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 || proc->nr_tti_rx == 7) {
 #ifdef UE_SLOT_PARALLELISATION
     phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
 #else

openair1/SCHED_NR/phy_frame_config_nr.c

@@ -369,6 +369,73 @@ int nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti)
   }
 }
 
+/*******************************************************************
+*
+* NAME :         nr_ue_slot_select
+*
+* DESCRIPTION :  function for the UE equivalent to nr_slot_select
+*
+*********************************************************************/
+
+int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti) {
+  /* for FFD all slot can be considered as an uplink */
+  int mu = cfg->ssb_config.scs_common, check_slot = 0;
+
+  if (cfg->cell_config.frame_duplex_type == FDD) {
+    return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT);
+  }
+
+  if (nr_frame%2 == 0) {
+    for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+      if (cfg->tdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) {
+        check_slot++;
+      }
+    }
+
+    if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+      return (NR_UPLINK_SLOT);
+    }
+
+    check_slot = 0;
+
+    for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+      if (cfg->tdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) {
+        check_slot++;
+      }
+    }
+
+    if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+      return (NR_DOWNLINK_SLOT);
+    } else {
+      return (NR_MIXED_SLOT);
+    }
+  } else {
+    for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+      if (cfg->tdd_table.max_tdd_periodicity_list[((1<<mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME) + nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) {
+        check_slot++;
+      }
+    }
+
+    if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+      return (NR_UPLINK_SLOT);
+    }
+
+    check_slot = 0;
+
+    for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+      if (cfg->tdd_table.max_tdd_periodicity_list[((1<<mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME) + nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) {
+        check_slot++;
+      }
+    }
+
+    if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+      return (NR_DOWNLINK_SLOT);
+    } else {
+      return (NR_MIXED_SLOT);
+    }
+  }
+}
+
 /*******************************************************************
 *
 * NAME :         free_tdd_configuration_nr

openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c

@@ -64,7 +64,9 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
 void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) {
 
   // check if DL slot
-  if (is_nr_DL_slot(mac->scc,slot)==1) {
+  if (slot == 1 || slot == 7) {
+
+    LOG_D(PHY,"Entering UE DCI configuration frame %d slot %d \n", frame, slot);
 
     // get BWP 1, Coreset 0, SearchSpace 0
     if (mac->DLbwp[0]==NULL) {