Type 0 PDCCH missing configurations

nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h

@@ -516,7 +516,7 @@ typedef struct {
   uint8_t aggregation_level;
   uint8_t n_rb;
   uint8_t n_symb;
-  uint8_t rb_offset;
+  int8_t rb_offset;
   uint8_t cr_mapping_type;
   uint8_t reg_bundle_size;
   uint8_t interleaver_size;

openair1/PHY/TOOLS/cdot_prod.c

@@ -169,7 +169,7 @@ int64_t dot_product64(int16_t *x,
 #if defined(__x86_64__) || defined(__i386__)
   __m128i *x128,*y128,mmtmp1,mmtmp2,mmtmp3,mmcumul,mmcumul_re,mmcumul_im;
   __m128i minus_i = _mm_set_epi16(-1,1,-1,1,-1,1,-1,1);
-  int32_t result;
+  int64_t result;
 
   x128 = (__m128i*) x;
   y128 = (__m128i*) y;

openair1/SCHED_NR/sched_nr.h

@@ -49,6 +49,9 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
 				  nr_frequency_range_e freq_range,
 				  uint8_t rmsi_pdcch_config,
 				  uint8_t ssb_idx,
+          uint8_t k_ssb,
+          uint16_t sfn_ssb,
+          uint8_t n_ssb,
 				  uint16_t nb_slots_per_frame,
 				  uint16_t N_RB);
 

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c

@@ -92,7 +92,8 @@ void nr_schedule_css_dlsch_phytest(module_id_t   module_idP,
 
 
     nr_configure_css_dci_initial(params_rel15,
-				 scs, scs, nr_FR1, 0, 0,
+				 scs, scs, nr_FR1, 0, 0, 0,
+         sfn_sf, slotP,
 				 slots_per_frame,
 				 dl_carrier_bandwidth);
 

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c

@@ -65,23 +65,47 @@ extern RAN_CONTEXT_t RC;
 
 extern int n_active_slices;
 
+  // Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs
 /// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config)
-uint8_t nr_coreset_nsymb_pdcch_type_0_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
-uint8_t nr_coreset_nsymb_pdcch_type_0_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3};
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_30[14] = {2,2,2,2,3,3,3,3,1,1,2,2,3,3};
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[9] = {1,1,2,2,3,3,1,2,3};
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[9] = {1,2,3,1,1,2,2,3,3};
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
+uint8_t nr_coreset_nsymb_pdcch_type_0_scs_120_60[12] = {1,1,2,2,3,3,1,2,1,1,1,1};
+
 /// LUT for the number of RBs in the coreset indexed by coreset index
-uint8_t nr_coreset_rb_offset_pdcch_type_0_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
-uint8_t nr_coreset_rb_offset_pdcch_type_0_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_15_15[15] = {0,2,4,0,2,4,12,16,12,16,12,16,38,38,38};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_15_30[14] = {5,6,7,8,5,6,7,8,18,20,18,20,18,20};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[9] = {2,6,2,6,2,6,28,28,28};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[9] = {4,4,4,0,56,0,56,0,56};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
+int8_t  nr_coreset_rb_offset_pdcch_type_0_scs_120_60[12] = {0,8,0,8,0,8,28,28,-1,49,-1,97};
+int8_t  nr_coreset_rb_offset_pdcch_type_0_scs_120_120[8] = {0,4,14,14,-1,24,-1,48};
+int8_t  nr_coreset_rb_offset_pdcch_type_0_scs_240_120[8] = {0,8,0,8,-1,25,-1,49};
+
 /// LUT for monitoring occasions param O indexed by ss index (4 LSB rmsi_pdcch_config)
 uint8_t nr_ss_param_O_type_0_mux1_FR1[16] = {0,0,2,2,5,5,7,7,0,5,0,0,2,2,5,5};
 uint8_t nr_ss_param_O_type_0_mux1_FR2[14] = {0,0,2.5,2.5,5,5,0,2.5,5,7.5,7.5,7.5,0,5};
+
 /// LUT for number of SS sets per slot indexed by ss index
 uint8_t nr_ss_sets_per_slot_type_0_FR1[16] = {1,2,1,2,1,2,1,2,1,1,1,1,1,1,1,1};
 uint8_t nr_ss_sets_per_slot_type_0_FR2[14] = {1,2,1,2,1,2,2,2,2,1,2,2,1,1};
+
 /// LUT for monitoring occasions param M indexed by ss index
 uint8_t nr_ss_param_M_type_0_mux1_FR1[16] = {1,0.5,1,0.5,1,0.5,1,0.5,2,2,1,1,1,1,1,1};
 uint8_t nr_ss_param_M_type_0_mux1_FR2[14] = {1,0.5,1,0.5,1,0.5,0.5,0.5,0.5,1,0.5,0.5,2,2};
+
 /// LUT for SS first symbol index indexed by ss index
 uint8_t nr_ss_first_symb_idx_type_0_mux1_FR1[8] = {0,0,1,2,1,2,1,2};
+  // Mux pattern type 2
+uint8_t nr_ss_first_symb_idx_scs_120_60_mux2[4] = {0,1,6,7};
+uint8_t nr_ss_first_symb_idx_scs_240_120_set1_mux2[6] = {0,1,2,3,0,1};
+  // Mux pattern type 3
+uint8_t nr_ss_first_symb_idx_scs_120_120_mux3[4] = {4,8,2,6};
+
 
 int is_nr_UL_slot(NR_COMMON_channels_t * ccP, int slot){
 
@@ -94,6 +118,9 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
 				  nr_frequency_range_e freq_range,
 				  uint8_t rmsi_pdcch_config,
 				  uint8_t ssb_idx,
+          uint8_t k_ssb,
+          uint16_t sfn_ssb,
+          uint8_t n_ssb, /*slot index overlapping the corresponding SSB index*/
 				  uint16_t nb_slots_per_frame,
 				  uint16_t N_RB)
 {
@@ -107,6 +134,28 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
 
     case kHz15:
       mu = 0;
+
+      switch(pdcch_scs) {
+        case kHz15:
+          AssertFatal(cset_idx<15,"Coreset index %d reserved for scs kHz15/kHz15\n", cset_idx);
+          pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
+          pdcch_params->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96;
+          pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx];
+          pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx];
+        break;
+
+        case kHz30:
+          AssertFatal(cset_idx<14,"Coreset index %d reserved for scs kHz15/kHz30\n", cset_idx);
+          pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
+          pdcch_params->n_rb = (cset_idx < 8)? 24 : 48;
+          pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx];
+          pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx];
+        break;
+
+        default:
+            AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+
+      }
       break;
 
     case kHz30:
@@ -115,14 +164,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
       if (N_RB < 106) { // Minimum 40Mhz bandwidth not satisfied
         switch(pdcch_scs) {
           case kHz15:
-            AssertFatal(1==0,"kHz15 not supported yet\n");   
+            AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx);
+            pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
+            pdcch_params->n_rb = (cset_idx < 10)? 48 : 96;
+            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx];
+            pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx];
           break;
 
           case kHz30:
             pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
-            pdcch_params->n_rb = (cset_idx < 10)? 24 : 48;
-            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
-            pdcch_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
+            pdcch_params->n_rb = (cset_idx < 6)? 24 : 48;
+            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx];
+            pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx];
           break;
 
           default:
@@ -130,31 +183,79 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
         }
       }
 
-      else {
-        AssertFatal(ss_idx<10 ,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+      else { // above 40Mhz
         switch(pdcch_scs) {
           case kHz15:
-              AssertFatal(1==0,"15 kHz SCS not supported yet\n"); 
+            AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx);
+            pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
+            pdcch_params->n_rb = (cset_idx < 3)? 48 : 96;
+            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx];
+            pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx];
           break;
 
           case kHz30:
+            AssertFatal(cset_idx<10,"Coreset index %d reserved for scs kHz30/kHz30\n", cset_idx);
             pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
             pdcch_params->n_rb = (cset_idx < 4)? 24 : 48;
-            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
-            pdcch_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
+            pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx];
+            pdcch_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx];
           break;
 
           default:
             AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
         }
       }
+      break;
+
+    case kHz120:
+      mu = 3;
+      switch(pdcch_scs) {
+        case kHz60:
+          AssertFatal(cset_idx<12,"Coreset index %d reserved for scs kHz120/kHz60\n", cset_idx);
+          pdcch_params->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2;
+          pdcch_params->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96;
+          pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx];
+          pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] :
+          (k_ssb == 0)? -41 : -42;
+        break;
+
+        case kHz120:
+          AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz120/kHz120\n", cset_idx);
+          pdcch_params->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3;
+          pdcch_params->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48;
+          pdcch_params->n_symb = (cset_idx == 2)? 1 : 2;
+          pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] :
+          (k_ssb == 0)? -20 : -21;
+        break;
+
+        default:
+            AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+      }
+    break;
 
+    case kHz240:
+    mu = 4;
+    switch(pdcch_scs) {
       case kHz60:
-      mu = 2;
+        AssertFatal(cset_idx<4,"Coreset index %d reserved for scs kHz240/kHz60\n", cset_idx);
+        pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
+        pdcch_params->n_rb = 96;
+        pdcch_params->n_symb = (cset_idx < 2)? 1 : 2;
+        pdcch_params->rb_offset = (cset_idx&1)? 16 : 0;
       break;
 
       case kHz120:
-    mu = 3;
+        AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz240/kHz120\n", cset_idx);
+        pdcch_params->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2;
+        pdcch_params->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48;
+        pdcch_params->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1;
+        pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] :
+        (k_ssb == 0)? -41 : -42;
+      break;
+
+      default:
+          AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+    }
     break;
 
   default:
@@ -170,7 +271,7 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
         O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
         pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
         M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
-        pdcch_params->first_symbol = (ss_idx < 8)? ( (ss_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
+        pdcch_params->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
       }
 
       else {
@@ -187,9 +288,29 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
     break;
 
     case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2:
+      AssertFatal( ((scs_common==kHz120)&&(pdcch_scs==kHz60)) || ((scs_common==kHz240)&&(pdcch_scs==kHz120)),
+      "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 2\n", scs_common, pdcch_scs );
+      AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs);
+
+      pdcch_params->nb_slots = 1;
+
+      if ((scs_common==kHz120)&&(pdcch_scs==kHz60)) {
+        pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3];
+        // Missing in pdcch_params sfn_C and n_C here and in else case
+      }
+      else {
+        pdcch_params->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //???
+      }
+
     break;
 
     case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3:
+      AssertFatal( (scs_common==kHz120)&&(pdcch_scs==kHz120),
+      "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 3\n", scs_common, pdcch_scs );
+      AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs);
+
+      pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3];
+
     break;
 
     default:

openair2/LAYER2/NR_MAC_gNB/mac_proto.h

@@ -72,6 +72,9 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
 				  nr_frequency_range_e freq_range,
 				  uint8_t rmsi_pdcch_config,
 				  uint8_t ssb_idx,
+          uint8_t k_ssb,
+          uint16_t sfn_ssb,
+          uint8_t n_ssb,
 				  uint16_t nb_slots_per_frame,
 				  uint16_t N_RB);