Commit 304bf7b7 authored by Haruki NAOI's avatar Haruki NAOI

Fix: add SNR filter for ULSCH AMC.

parent ef5574bf
...@@ -832,6 +832,7 @@ typedef struct { ...@@ -832,6 +832,7 @@ typedef struct {
uint8_t pucch3_snr[NFAPI_CC_MAX]; uint8_t pucch3_snr[NFAPI_CC_MAX];
uint8_t pusch_snr[NFAPI_CC_MAX]; uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX]; uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint16_t feedback_cnt[NFAPI_CC_MAX]; uint16_t feedback_cnt[NFAPI_CC_MAX];
uint16_t timing_advance; uint16_t timing_advance;
uint16_t timing_advance_r9; uint16_t timing_advance_r9;
......
...@@ -3346,7 +3346,7 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3346,7 +3346,7 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
uint16_t first_rb[MAX_NUM_CCs]; uint16_t first_rb[MAX_NUM_CCs];
uint8_t mcs; uint8_t mcs;
uint8_t snr; uint8_t snr;
uint8_t snr2mcs_offset = 4; uint8_t snr2mcs_offset = 0;
uint8_t rb_table_index; uint8_t rb_table_index;
uint8_t num_pucch_rb; uint8_t num_pucch_rb;
uint32_t tbs; uint32_t tbs;
...@@ -3441,10 +3441,13 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3441,10 +3441,13 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
UE_template = &UE_list->UE_template[CC_id][UE_id]; UE_template = &UE_list->UE_template[CC_id][UE_id];
if ( UE_list->UE_sched_ctrl[UE_id].phr_received == 1 ) { if ( UE_list->UE_sched_ctrl[UE_id].phr_received == 1 ) {
snr = (5 * UE_list->UE_sched_ctrl[UE_id].pusch_snr[CC_id] - 640) / 10; snr = (5 * UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[CC_id] - 640) / 10;
if((snr + snr2mcs_offset) >= 20) { if((snr + snr2mcs_offset) >= 20) {
mcs = 20; mcs = 20;
} }
else if((snr + snr2mcs_offset) < 3) {
mcs = 3;
}
else { else {
mcs = snr + snr2mcs_offset; mcs = snr + snr2mcs_offset;
} }
...@@ -3981,8 +3984,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, ...@@ -3981,8 +3984,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
nfapi_hi_dci0_request_t *nfapi_hi_dci0_req = &eNB->HI_DCI0_req[CC_id][subframeP]; nfapi_hi_dci0_request_t *nfapi_hi_dci0_req = &eNB->HI_DCI0_req[CC_id][subframeP];
nfapi_hi_dci0_req->sfn_sf = frameP<<4|subframeP; // sfnsf_add_subframe(sched_frame, sched_subframeP, 0); // sunday! nfapi_hi_dci0_req->sfn_sf = frameP<<4|subframeP; // sfnsf_add_subframe(sched_frame, sched_subframeP, 0); // sunday!
nfapi_hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; nfapi_hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST;
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d\n", LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP); harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,UE_template->mcs_UL[harq_pid],first_rb[CC_id],rb_table[rb_table_index],0);
ul_req_index = 0; ul_req_index = 0;
dlsch_flag = 0; dlsch_flag = 0;
...@@ -4136,8 +4139,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, ...@@ -4136,8 +4139,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid;
hi_dci0_req->number_of_dci++; hi_dci0_req->number_of_dci++;
// Add UL_config PDUs // Add UL_config PDUs
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d\n", LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP); harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,mcs_rv,ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb,ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb,UE_sched_ctrl->round_UL[CC_id][harq_pid]);
ul_req_index = 0; ul_req_index = 0;
dlsch_flag = 0; dlsch_flag = 0;
......
...@@ -2449,7 +2449,7 @@ add_new_ue(module_id_t mod_idP, ...@@ -2449,7 +2449,7 @@ add_new_ue(module_id_t mod_idP,
UE_list->assoc_ul_slice_idx[UE_id] = 0; UE_list->assoc_ul_slice_idx[UE_id] = 0;
UE_list->UE_sched_ctrl[UE_id].ta_update = 31; UE_list->UE_sched_ctrl[UE_id].ta_update = 31;
UE_list->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = 0; UE_list->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[cc_idP] = 0;
for (j = 0; j < 8; j++) { for (j = 0; j < 8; j++) {
UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB1] = (j == 0) ? 1 : 0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0 UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB1] = (j == 0) ? 1 : 0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB2] = 1; UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB2] = 1;
......
...@@ -174,12 +174,20 @@ rx_sdu(const module_id_t enb_mod_idP, ...@@ -174,12 +174,20 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_scheduling_control->ta_update = (UE_scheduling_control->ta_update * 3 + timing_advance) / 4; UE_scheduling_control->ta_update = (UE_scheduling_control->ta_update * 3 + timing_advance) / 4;
UE_scheduling_control->pusch_snr[CC_idP] = ul_cqi; UE_scheduling_control->pusch_snr[CC_idP] = ul_cqi;
double tpc_forgetting_filter=0.75; double snr_filter_tpc=0.75;
if(UE_scheduling_control->pusch_snr_avg[CC_idP] == 0) { if(UE_scheduling_control->pusch_snr_avg[CC_idP] == 0) {
UE_scheduling_control->pusch_snr_avg[CC_idP] = ul_cqi; UE_scheduling_control->pusch_snr_avg[CC_idP] = ul_cqi;
} }
else { else {
UE_scheduling_control->pusch_snr_avg[CC_idP] = (int)((double)UE_scheduling_control->pusch_snr_avg[CC_idP] * tpc_forgetting_filter + (double)ul_cqi * (1-tpc_forgetting_filter)); UE_scheduling_control->pusch_snr_avg[CC_idP] = (int)((double)UE_scheduling_control->pusch_snr_avg[CC_idP] * snr_filter_tpc + (double)ul_cqi * (1-snr_filter_tpc));
}
double snr_filter_amc=0.5;
if(UE_scheduling_control->pusch_snr_amc[CC_idP] == 0) {
UE_scheduling_control->pusch_snr_amc[CC_idP] = ul_cqi;
}
else {
UE_scheduling_control->pusch_snr_amc[CC_idP] = (int)((double)UE_scheduling_control->pusch_snr_amc[CC_idP] * snr_filter_amc + (double)ul_cqi * (1-snr_filter_amc));
} }
UE_scheduling_control->ul_consecutive_errors = 0; UE_scheduling_control->ul_consecutive_errors = 0;
......
...@@ -1001,6 +1001,7 @@ typedef struct { ...@@ -1001,6 +1001,7 @@ typedef struct {
uint8_t pucch3_snr[NFAPI_CC_MAX]; uint8_t pucch3_snr[NFAPI_CC_MAX];
uint8_t pusch_snr[NFAPI_CC_MAX]; uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX]; uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint16_t feedback_cnt[NFAPI_CC_MAX]; uint16_t feedback_cnt[NFAPI_CC_MAX];
uint16_t timing_advance; uint16_t timing_advance;
uint16_t timing_advance_r9; uint16_t timing_advance_r9;
......
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