Commit 645a0a61 authored by ISIP CS/NCTU's avatar ISIP CS/NCTU

add 256QAM & dmrs_pdsch

parent c548f425
...@@ -139,6 +139,21 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -139,6 +139,21 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
nr_init_pdcch_dmrs(gNB, cfg->sch_config.physical_cell_id.value); nr_init_pdcch_dmrs(gNB, cfg->sch_config.physical_cell_id.value);
//PDSCH DMRS init
gNB->nr_gold_pdsch_dmrs = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t**));
uint32_t ***pdsch_dmrs = gNB->nr_gold_pdsch_dmrs;
for (int slot=0; slot<fp->slots_per_frame; slot++) {
pdsch_dmrs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t*));
AssertFatal(pdsch_dmrs[slot]!=NULL, "NR init: pdsch_dmrs for slot %d - malloc failed\n", slot);
for (int symb=0; symb<fp->symbols_per_slot; symb++){
pdsch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t));
AssertFatal(pdsch_dmrs[slot][symb]!=NULL, "NR init: pdsch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb);
}
}
nr_init_pdsch_dmrs(gNB, cfg->sch_config.physical_cell_id.value);
/* /*
lte_gold(fp,gNB->lte_gold_table,fp->Nid_cell); lte_gold(fp,gNB->lte_gold_table,fp->Nid_cell);
generate_pcfich_reg_mapping(fp); generate_pcfich_reg_mapping(fp);
......
...@@ -9,6 +9,30 @@ BPSK = 23170; ...@@ -9,6 +9,30 @@ BPSK = 23170;
% Amplitude for QPSK (\f$ 2^15 \times 1/\sqrt{2}\f$) % Amplitude for QPSK (\f$ 2^15 \times 1/\sqrt{2}\f$)
QPSK = 23170; QPSK = 23170;
% First Amplitude for QAM16 (\f$ 2^15 \times 2/\sqrt{10}\f$)
QAM16_n1 = 20724;
% Second Amplitude for QAM16 (\f$ 2^15 \times 1/\sqrt{10}\f$)
QAM16_n2 = 10362;
% First Amplitude for QAM64 (\f$ 2^15 \times 4/\sqrt{42}\f$)
QAM64_n1 = 20225;
% Second Amplitude for QAM64 (\f$ 2^15 \times 2/\sqrt{42}\f$)
QAM64_n2 = 10112;
% Third Amplitude for QAM64 (\f$ 2^15 \times 1/\sqrt{42}\f$)
QAM64_n3 = 5056;
% First Amplitude for QAM256 (\f$ 2^15 \times 8/\sqrt{170}\f$)
QAM256_n1 = 20105;
% Second Amplitude for QAM256 (\f$ 2^15 \times 4/\sqrt{170}\f$)
QAM256_n2 = 10052;
% Third Amplitude for QAM256 (\f$ 2^15 \times 2/\sqrt{170}\f$)
QAM256_n3 = 5026;
% Third Amplitude for QAM256 (\f$ 2^15 \times 1/\sqrt{170}\f$)
QAM256_n4 = 2513;
% BPSK % BPSK
for b = 0:1 for b = 0:1
bpsk_table(b+1) = (1 - 2*b)*BPSK + 1j*(1-2*b)*BPSK; bpsk_table(b+1) = (1 - 2*b)*BPSK + 1j*(1-2*b)*BPSK;
...@@ -17,12 +41,91 @@ end ...@@ -17,12 +41,91 @@ end
%% QPSK %% QPSK
for r=0:1 %0 -- 1 LS for r=0:1 %0 -- 1 LS
for j=0:1 %0 -- 1 MS for j=0:1 %0 -- 1 MS
%% Formula is dispalayed
qpsk_table(2*r+j+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK); qpsk_table(2*r+j+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK);
end end
end end
table = [ 0; bpsk_table(:); qpsk_table(:) ]; %% QAM16
for a=-1:2:1
for b=-1:2:1
index = (1+a) + (1+b)/2;
qam16_table(index+1) = -a*(QAM16_n1 + (b*QAM16_n2));
end
end
for b0=0:1
for b1=0:1
for b2=0:1
for b3=0:1
qam16_table2(b0*8+b1*4+b2*2+b3*1+1) = qam16_table(b0*2+b2*1+1) + 1j*qam16_table(b1*2+b3*1+1);
end
end
end
end
%% QAM64
for a=-1:2:1
for b=-1:2:1
for c=-1:2:1
index = (1+a)*2 + (1+b) + (1+c)/2;
qam64_table(index+1) = -a*(QAM64_n1 + b*(QAM64_n2 + (c*QAM64_n3)));
end
end
end
for b0=0:1
for b1=0:1
for b2=0:1
for b3=0:1
for b4=0:1
for b5=0:1
qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1);
end
end
end
end
end
end
%%256QAM
%% QAM256 *******************************************************************************************
for a=-1:2:1
for b=-1:2:1
for c=-1:2:1
for d = -1:2:1
index = (1+a)*4 + (1+b)*2 + (1+c)+(1+d)/2;
qam256_table(index+1) = -a*(QAM256_n1 + b*(QAM256_n2 + (c*(QAM256_n3+d*QAM256_n4))));
end
end
end
end
for b0=0:1
for b1=0:1
for b2=0:1
for b3=0:1
for b4=0:1
for b5=0:1
for b6=0:1
for b7=0:1
%%qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1);
qam256_table2(b0*128+b1*64+b2*32+b3*16+b4*8+b5*4+b6*2+b7*1+1) = qam256_table(b0*8+b2*4+b4*2+b6*1+1) + 1j*qam256_table(b1*8+b3*4+b5*2+b7*1+1);
end
end
end
end
end
end
end
end
table = [ 0; bpsk_table(:); qpsk_table(:);qam16_table2(:); qam64_table2(:);qam256_table2(:) ];
scatter (real(qam256_table2), imag(qam256_table2), 'x');
save mod_table.mat table save mod_table.mat table
table2 = zeros(1,length(table)*2); table2 = zeros(1,length(table)*2);
...@@ -33,6 +136,9 @@ fd = fopen("nr_mod_table.h","w"); ...@@ -33,6 +136,9 @@ fd = fopen("nr_mod_table.h","w");
fprintf(fd,"#define NR_MOD_TABLE_SIZE_SHORT %d\n", length(table)*2); fprintf(fd,"#define NR_MOD_TABLE_SIZE_SHORT %d\n", length(table)*2);
fprintf(fd,"#define NR_MOD_TABLE_BPSK_OFFSET %d\n", 1); fprintf(fd,"#define NR_MOD_TABLE_BPSK_OFFSET %d\n", 1);
fprintf(fd,"#define NR_MOD_TABLE_QPSK_OFFSET %d\n", 3); fprintf(fd,"#define NR_MOD_TABLE_QPSK_OFFSET %d\n", 3);
fprintf(fd,"#define NR_MOD_TABLE_QAM16_OFFSET %d\n", 7);
fprintf(fd,"#define NR_MOD_TABLE_QAM64_OFFSET %d\n", 23);
fprintf(fd,"#define NR_MOD_TABLE_QAM256_OFFSET %d\n", 87);
fprintf(fd,"short nr_mod_table[MOD_TABLE_SIZE_SHORT] = {"); fprintf(fd,"short nr_mod_table[MOD_TABLE_SIZE_SHORT] = {");
fprintf(fd,"%d,",table2(1:end-1)); fprintf(fd,"%d,",table2(1:end-1));
fprintf(fd,"%d};\n",table2(end)); fprintf(fd,"%d};\n",table2(end));
......
...@@ -75,3 +75,31 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) ...@@ -75,3 +75,31 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
} }
} }
void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
{
uint32_t x1, x2;
uint8_t reset;
int Nscid;
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
uint32_t ***pdsch_dmrs = gNB->nr_gold_pdsch_dmrs;
//x2 compute by 38.211 7.4.1.1.1
Nscid = 0;
for (uint8_t slot=0; slot<fp->slots_per_frame; slot++) {
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<17) * (slot*symb*slot+symb+1) * (Nid+1) *((Nid<<1)+Nscid))&(((uint32_t)1<<31)-1);
printf("x2 = %d\n",x2);
for (uint32_t n=0; n<NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD; n++) {
pdsch_dmrs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
printf("slot = %d*** symb = %d*** n = %d*** \n",slot,symb,n);
reset = 0;
}
}
}
}
\ No newline at end of file
#define NR_MOD_TABLE_SIZE_SHORT 14 #define NR_MOD_TABLE_SIZE_SHORT 686
#define NR_MOD_TABLE_BPSK_OFFSET 1 #define NR_MOD_TABLE_BPSK_OFFSET 1
#define NR_MOD_TABLE_QPSK_OFFSET 3 #define NR_MOD_TABLE_QPSK_OFFSET 3
short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,23170,23170,-23170,-23170,23170,23170,23170,-23170,-23170,23170,-23170,-23170}; #define NR_MOD_TABLE_QAM16_OFFSET 7
#define NR_MOD_TABLE_QAM64_OFFSET 23
#define NR_MOD_TABLE_QAM256_OFFSET 87
short nr_mod_table[MOD_TABLE_SIZE_SHORT] = {0,0,23170,23170,-23170,-23170,23170,23170,23170,-23170,-23170,23170,-23170,-23170,10362,10362,10362,31086,31086,10362,31086,31086,10362,-10362,10362,-31086,31086,-10362,31086,-31086,-10362,10362,-10362,31086,-31086,10362,-31086,31086,-10362,-10362,-10362,-31086,-31086,-10362,-31086,-31086,15169,15169,15169,5057,5057,15169,5057,5057,15169,25281,15169,35393,5057,25281,5057,35393,25281,15169,25281,5057,35393,15169,35393,5057,25281,25281,25281,35393,35393,25281,35393,35393,15169,-15169,15169,-5057,5057,-15169,5057,-5057,15169,-25281,15169,-35393,5057,-25281,5057,-35393,25281,-15169,25281,-5057,35393,-15169,35393,-5057,25281,-25281,25281,-35393,35393,-25281,35393,-35393,-15169,15169,-15169,5057,-5057,15169,-5057,5057,-15169,25281,-15169,35393,-5057,25281,-5057,35393,-25281,15169,-25281,5057,-35393,15169,-35393,5057,-25281,25281,-25281,35393,-35393,25281,-35393,35393,-15169,-15169,-15169,-5057,-5057,-15169,-5057,-5057,-15169,-25281,-15169,-35393,-5057,-25281,-5057,-35393,-25281,-15169,-25281,-5057,-35393,-15169,-35393,-5057,-25281,-25281,-25281,-35393,-35393,-25281,-35393,-35393,12566,12566,12566,17592,17592,12566,17592,17592,12566,7540,12566,2514,17592,7540,17592,2514,7540,12566,7540,17592,2514,12566,2514,17592,7540,7540,7540,2514,2514,7540,2514,2514,12566,27644,12566,22618,17592,27644,17592,22618,12566,32670,12566,37696,17592,32670,17592,37696,7540,27644,7540,22618,2514,27644,2514,22618,7540,32670,7540,37696,2514,32670,2514,37696,27644,12566,27644,17592,22618,12566,22618,17592,27644,7540,27644,2514,22618,7540,22618,2514,32670,12566,32670,17592,37696,12566,37696,17592,32670,7540,32670,2514,37696,7540,37696,2514,27644,27644,27644,22618,22618,27644,22618,22618,27644,32670,27644,37696,22618,32670,22618,37696,32670,27644,32670,22618,37696,27644,37696,22618,32670,32670,32670,37696,37696,32670,37696,37696,12566,-12566,12566,-17592,17592,-12566,17592,-17592,12566,-7540,12566,-2514,17592,-7540,17592,-2514,7540,-12566,7540,-17592,2514,-12566,2514,-17592,7540,-7540,7540,-2514,2514,-7540,2514,-2514,12566,-27644,12566,-22618,17592,-27644,17592,-22618,12566,-32670,12566,-37696,17592,-32670,17592,-37696,7540,-27644,7540,-22618,2514,-27644,2514,-22618,7540,-32670,7540,-37696,2514,-32670,2514,-37696,27644,-12566,27644,-17592,22618,-12566,22618,-17592,27644,-7540,27644,-2514,22618,-7540,22618,-2514,32670,-12566,32670,-17592,37696,-12566,37696,-17592,32670,-7540,32670,-2514,37696,-7540,37696,-2514,27644,-27644,27644,-22618,22618,-27644,22618,-22618,27644,-32670,27644,-37696,22618,-32670,22618,-37696,32670,-27644,32670,-22618,37696,-27644,37696,-22618,32670,-32670,32670,-37696,37696,-32670,37696,-37696,-12566,12566,-12566,17592,-17592,12566,-17592,17592,-12566,7540,-12566,2514,-17592,7540,-17592,2514,-7540,12566,-7540,17592,-2514,12566,-2514,17592,-7540,7540,-7540,2514,-2514,7540,-2514,2514,-12566,27644,-12566,22618,-17592,27644,-17592,22618,-12566,32670,-12566,37696,-17592,32670,-17592,37696,-7540,27644,-7540,22618,-2514,27644,-2514,22618,-7540,32670,-7540,37696,-2514,32670,-2514,37696,-27644,12566,-27644,17592,-22618,12566,-22618,17592,-27644,7540,-27644,2514,-22618,7540,-22618,2514,-32670,12566,-32670,17592,-37696,12566,-37696,17592,-32670,7540,-32670,2514,-37696,7540,-37696,2514,-27644,27644,-27644,22618,-22618,27644,-22618,22618,-27644,32670,-27644,37696,-22618,32670,-22618,37696,-32670,27644,-32670,22618,-37696,27644,-37696,22618,-32670,32670,-32670,37696,-37696,32670,-37696,37696,-12566,-12566,-12566,-17592,-17592,-12566,-17592,-17592,-12566,-7540,-12566,-2514,-17592,-7540,-17592,-2514,-7540,-12566,-7540,-17592,-2514,-12566,-2514,-17592,-7540,-7540,-7540,-2514,-2514,-7540,-2514,-2514,-12566,-27644,-12566,-22618,-17592,-27644,-17592,-22618,-12566,-32670,-12566,-37696,-17592,-32670,-17592,-37696,-7540,-27644,-7540,-22618,-2514,-27644,-2514,-22618,-7540,-32670,-7540,-37696,-2514,-32670,-2514,-37696,-27644,-12566,-27644,-17592,-22618,-12566,-22618,-17592,-27644,-7540,-27644,-2514,-22618,-7540,-22618,-2514,-32670,-12566,-32670,-17592,-37696,-12566,-37696,-17592,-32670,-7540,-32670,-2514,-37696,-7540,-37696,-2514,-27644,-27644,-27644,-22618,-22618,-27644,-22618,-22618,-27644,-32670,-27644,-37696,-22618,-32670,-22618,-37696,-32670,-27644,-32670,-22618,-37696,-27644,-37696,-22618,-32670,-32670,-32670,-37696,-37696,-32670,-37696,-37696};
\ No newline at end of file
...@@ -37,6 +37,6 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB); ...@@ -37,6 +37,6 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB);
@param Nid is used for the initialization of x2, Physical cell Id by default or upper layer configured pdcch_scrambling_ID @param Nid is used for the initialization of x2, Physical cell Id by default or upper layer configured pdcch_scrambling_ID
*/ */
void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid); void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
#endif #endif
...@@ -454,6 +454,9 @@ typedef struct PHY_VARS_gNB_s { ...@@ -454,6 +454,9 @@ typedef struct PHY_VARS_gNB_s {
/// PDCCH DMRS sequence /// PDCCH DMRS sequence
uint32_t ***nr_gold_pdcch_dmrs; uint32_t ***nr_gold_pdcch_dmrs;
/// PDSCH DMRS sequence
uint32_t ***nr_gold_pdsch_dmrs;
/// Indicator set to 0 after first SR /// Indicator set to 0 after first SR
uint8_t first_sr[NUMBER_OF_UE_MAX]; uint8_t first_sr[NUMBER_OF_UE_MAX];
......
...@@ -69,6 +69,9 @@ ...@@ -69,6 +69,9 @@
/*used for the resource mapping*/ /*used for the resource mapping*/
#define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE) #define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE)
#define NR_MAX_PDSCH_DMRS_LENGTH 1100 //275*2(k)*2(QPSK)
#define NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD 35 // ceil(NR_MAX_PDSCH_DMRS_LENGTH/32)
#define NR_MAX_DCI_PAYLOAD_SIZE 64 #define NR_MAX_DCI_PAYLOAD_SIZE 64
#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE) #define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE)
#define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32) #define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment