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canghaiwuhen
OpenXG-RAN
Commits
adc3ab4e
Commit
adc3ab4e
authored
Sep 11, 2019
by
Sakthivel Velumani
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1.Fixed bug in setting UE's coreset.frequecny_domain_resource
2.Set UE's coreset.rb_offset according to gNB's
parent
8119806f
Changes
1
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-1
openair1/SIMULATION/NR_PHY/dlsim.c
openair1/SIMULATION/NR_PHY/dlsim.c
+3
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openair1/SIMULATION/NR_PHY/dlsim.c
View file @
adc3ab4e
...
@@ -591,13 +591,15 @@ int main(int argc, char **argv)
...
@@ -591,13 +591,15 @@ int main(int argc, char **argv)
uint64_t
mask
=
0x0
;
uint64_t
mask
=
0x0
;
uint16_t
num_rbs
=
24
;
uint16_t
num_rbs
=
24
;
uint16_t
rb_offset
=
0
;
uint16_t
rb_offset
=
gNB
->
pdcch_vars
.
dci_alloc
[
0
].
pdcch_params
.
rb_offset
;
uint16_t
cell_id
=
0
;
uint16_t
cell_id
=
0
;
uint16_t
num_symbols
=
2
;
uint16_t
num_symbols
=
2
;
for
(
i
=
0
;
i
<
(
num_rbs
/
6
);
++
i
){
// 38.331 Each bit corresponds a group of 6 RBs
for
(
i
=
0
;
i
<
(
num_rbs
/
6
);
++
i
){
// 38.331 Each bit corresponds a group of 6 RBs
mask
=
mask
>>
1
;
mask
=
mask
>>
1
;
mask
=
mask
|
0x100000000000
;
mask
=
mask
|
0x100000000000
;
}
}
uint16_t
rb_offset_count
=
rb_offset
/
6
;
mask
=
mask
>>
rb_offset_count
;
dl_config
->
dl_config_list
[
0
].
dci_config_pdu
.
dci_config_rel15
.
coreset
.
frequency_domain_resource
=
mask
;
dl_config
->
dl_config_list
[
0
].
dci_config_pdu
.
dci_config_rel15
.
coreset
.
frequency_domain_resource
=
mask
;
dl_config
->
dl_config_list
[
0
].
dci_config_pdu
.
dci_config_rel15
.
coreset
.
rb_offset
=
rb_offset
;
// additional parameter other than coreset
dl_config
->
dl_config_list
[
0
].
dci_config_pdu
.
dci_config_rel15
.
coreset
.
rb_offset
=
rb_offset
;
// additional parameter other than coreset
...
...
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