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Commit bf4a8849 authored by Haruki NAOI's avatar Haruki NAOI
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Add: PUSCH AMC using average BLER. 

(cherry picked from commit 1ab0a979fdbcc933ae249838841dc7f61c0e5aba)

# Conflicts:
#	openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
parent 1bad0cc6
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Showing with 96 additions and 19 deletions
openair2/LAYER2/MAC/defs.h
View file @ bf4a8849
...@@ -758,6 +758,10 @@ typedef struct { ...@@ -758,6 +758,10 @@ typedef struct {
uint32_t pucch_tpc_tx_frame; uint32_t pucch_tpc_tx_frame;
uint32_t pucch_tpc_tx_subframe; uint32_t pucch_tpc_tx_subframe;
/// stores the frame where the last bler was calculated
uint32_t pusch_bler_calc_frame;
uint32_t pusch_bler_calc_subframe;
#ifdef LOCALIZATION #ifdef LOCALIZATION
eNB_UE_estimated_distances distance; eNB_UE_estimated_distances distance;
#endif #endif
...@@ -833,6 +837,12 @@ typedef struct { ...@@ -833,6 +837,12 @@ typedef struct {
uint8_t pusch_snr[NFAPI_CC_MAX]; uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX]; uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX]; uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint64_t pusch_rx_num[NFAPI_CC_MAX];
uint64_t pusch_rx_num_old[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num_old[NFAPI_CC_MAX];
double pusch_bler[NFAPI_CC_MAX];
uint8_t mcs_offset[NFAPI_CC_MAX];
uint16_t feedback_cnt[NFAPI_CC_MAX]; uint16_t feedback_cnt[NFAPI_CC_MAX];
uint16_t timing_advance; uint16_t timing_advance;
uint16_t timing_advance_r9; uint16_t timing_advance_r9;
......
openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
View file @ bf4a8849
...@@ -3344,9 +3344,11 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3344,9 +3344,11 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
uint8_t total_rbs=0; uint8_t total_rbs=0;
uint8_t average_rbs; uint8_t average_rbs;
uint16_t first_rb[MAX_NUM_CCs]; uint16_t first_rb[MAX_NUM_CCs];
uint8_t mcs; int8_t mcs;
uint8_t snr; uint8_t snr;
uint8_t snr2mcs_offset = 0; uint8_t snr2mcs_offset = 3;
double bler_filter=0.9;
double bler;
uint8_t rb_table_index; uint8_t rb_table_index;
uint8_t num_pucch_rb; uint8_t num_pucch_rb;
uint32_t tbs; uint32_t tbs;
...@@ -3440,16 +3442,61 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3440,16 +3442,61 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
} else { } else {
UE_template = &UE_list->UE_template[CC_id][UE_id]; UE_template = &UE_list->UE_template[CC_id][UE_id];
int32_t framex10psubframe = UE_template->pusch_bler_calc_frame*10+UE_template->pusch_bler_calc_subframe;
int pusch_bler_interval=100;
double total_bler;
if(UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id] == 0 && UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id] == 0) {
total_bler = 0;
}
else {
total_bler = (double)UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id] / (double)(UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id] + UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id]) * 100;
}
if (((framex10psubframe+pusch_bler_interval)<=(frameP*10+subframeP)) || //normal case
((framex10psubframe>(frameP*10+subframeP)) && (((10240-framex10psubframe+frameP*10+subframeP)>=pusch_bler_interval)))) { //frame wrap-around
UE_template->pusch_bler_calc_frame=frameP;
UE_template->pusch_bler_calc_subframe=subframeP;
int pusch_rx_num_diff = UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id] - UE_list->UE_sched_ctrl[UE_id].pusch_rx_num_old[CC_id];
int pusch_rx_error_num_diff = UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id] - UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num_old[CC_id];
if((pusch_rx_num_diff == 0) && (pusch_rx_error_num_diff == 0)) { /* first rx case or no rx among interval time */
bler = UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id];
}
else {
bler = (double)pusch_rx_error_num_diff / (double)(pusch_rx_num_diff + pusch_rx_error_num_diff) * 100;
}
UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id] = UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id] * bler_filter + bler * (1.0-bler_filter);
UE_list->UE_sched_ctrl[UE_id].pusch_rx_num_old[CC_id] = UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id];
UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num_old[CC_id] = UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id];
if(bler < 0.5) {
if(UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id] !=0) {
UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id]--;
}
}
if(bler >= 2) {
UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id]++;
if(UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id] >= 20) {
UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id]=20;
}
}
}
if ( UE_list->UE_sched_ctrl[UE_id].phr_received == 1 ) { if ( UE_list->UE_sched_ctrl[UE_id].phr_received == 1 ) {
snr = (5 * UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[CC_id] - 640) / 10; snr = (5 * UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[CC_id] - 640) / 10;
if((snr + snr2mcs_offset) >= 20) { mcs = snr - snr2mcs_offset;
if(mcs > 20) {
mcs = 20; mcs = 20;
} }
else if((snr + snr2mcs_offset) < 3) {
mcs = 3; if(mcs - UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id] < 6) {
mcs = 6;
} }
else { else {
mcs = snr + snr2mcs_offset; mcs = mcs - UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id];
} }
} else { } else {
mcs = 10; mcs = 10;
...@@ -3463,19 +3510,13 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3463,19 +3510,13 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ul_total_buffer > 0 ) { if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ul_total_buffer > 0 ) {
rb_table_index = 2; rb_table_index = 2;
tbs = get_TBS_UL(mcs,rb_table[rb_table_index]); tbs = get_TBS_UL(mcs,rb_table[rb_table_index]);
tx_power= estimate_ue_tx_power(tbs*8,rb_table[rb_table_index],0,frame_parms->Ncp,0); tx_power = (int8_t)(hundred_times_log10_NPRB[rb_table[rb_table_index] - 1] / 100);
while ( (((UE_template->phr_info - tx_power) < 0 ) || (tbs > bytes_to_schedule)) && (mcs > 3) ) {
mcs--;
tbs = get_TBS_UL(mcs,rb_table[rb_table_index]);
tx_power= estimate_ue_tx_power(tbs*8,rb_table[rb_table_index],0,frame_parms->Ncp,0);
}
while ( (tbs < bytes_to_schedule) && (rb_table[rb_table_index]<(frame_parms->N_RB_UL-num_pucch_rb-first_rb[CC_id])) && while ( (tbs < bytes_to_schedule) && (rb_table[rb_table_index]<(frame_parms->N_RB_UL-num_pucch_rb-first_rb[CC_id])) &&
((UE_template->phr_info - tx_power) > 0) && (rb_table_index < 32 )) { ((UE_template->phr_info - tx_power) > 0) && (rb_table_index < 32 )) {
rb_table_index++; rb_table_index++;
tbs = get_TBS_UL(mcs,rb_table[rb_table_index]); tbs = get_TBS_UL(mcs,rb_table[rb_table_index]);
tx_power= estimate_ue_tx_power(tbs*8,rb_table[rb_table_index],0,frame_parms->Ncp,0); tx_power = (int8_t)(hundred_times_log10_NPRB[rb_table[rb_table_index] - 1] / 100);
} }
if ( rb_table[rb_table_index]<3 ) { if ( rb_table[rb_table_index]<3 ) {
...@@ -3505,6 +3546,11 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP, ...@@ -3505,6 +3546,11 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index; UE_list->UE_template[CC_id][UE_id].pre_allocated_rb_table_index_ul = rb_table_index;
UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs; UE_list->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs;
} }
LOG_D(MAC,"[eNB %d] frame %d subframe %d, UE %d/%x CC %d snr %d mcs %d mcs_offset %d bler %lf total_bler %lf ( %d %d ) rb_num %d phr_info %d tx_power %d bsr %d\n",
module_idP,frameP,subframeP,UE_id,UE_RNTI(CC_id,UE_id),CC_id, snr, mcs, UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id],
total_bler, UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id], rb_table[rb_table_index-1], UE_template->phr_info, tx_power, bytes_to_schedule);
} else { } else {
if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED){ if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED){
// assigne RBS( 6 RBs) // assigne RBS( 6 RBs)
...@@ -3984,8 +4030,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, ...@@ -3984,8 +4030,8 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
nfapi_hi_dci0_request_t *nfapi_hi_dci0_req = &eNB->HI_DCI0_req[CC_id][subframeP]; nfapi_hi_dci0_request_t *nfapi_hi_dci0_req = &eNB->HI_DCI0_req[CC_id][subframeP];
nfapi_hi_dci0_req->sfn_sf = frameP<<4|subframeP; // sfnsf_add_subframe(sched_frame, sched_subframeP, 0); // sunday! nfapi_hi_dci0_req->sfn_sf = frameP<<4|subframeP; // sfnsf_add_subframe(sched_frame, sched_subframeP, 0); // sunday!
nfapi_hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; nfapi_hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST;
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d\n", LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d mcs %d sinr %d bler %lf\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,UE_template->mcs_UL[harq_pid],first_rb[CC_id],rb_table[rb_table_index],0); harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,UE_template->mcs_UL[harq_pid],first_rb[CC_id],rb_table[rb_table_index],0,UE_template->mcs_UL[harq_pid],(5 * UE_sched_ctrl->pusch_snr_amc[CC_id] - 640) / 10,UE_sched_ctrl->pusch_bler[CC_id]);
ul_req_index = 0; ul_req_index = 0;
dlsch_flag = 0; dlsch_flag = 0;
...@@ -4139,8 +4185,9 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP, ...@@ -4139,8 +4185,9 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.harq_pid = harq_pid;
hi_dci0_req->number_of_dci++; hi_dci0_req->number_of_dci++;
// Add UL_config PDUs // Add UL_config PDUs
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d\n", LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d mcs %d sinr %d bler %lf\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,mcs_rv,ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb,ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb,UE_sched_ctrl->round_UL[CC_id][harq_pid]); harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,mcs_rv,ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb,ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb,UE_sched_ctrl->round_UL[CC_id][harq_pid],UE_template->mcs_UL[harq_pid],(5 * UE_sched_ctrl->pusch_snr_amc[CC_id] - 640) / 10,UE_sched_ctrl->pusch_bler[CC_id]);
ul_req_index = 0; ul_req_index = 0;
dlsch_flag = 0; dlsch_flag = 0;
......
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
View file @ bf4a8849
...@@ -2450,6 +2450,13 @@ add_new_ue(module_id_t mod_idP, ...@@ -2450,6 +2450,13 @@ add_new_ue(module_id_t mod_idP,
UE_list->UE_sched_ctrl[UE_id].ta_update = 31; UE_list->UE_sched_ctrl[UE_id].ta_update = 31;
UE_list->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = 0; UE_list->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[cc_idP] = 0; UE_list->UE_sched_ctrl[UE_id].pusch_snr_amc[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_rx_num_old[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num_old[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].pusch_bler[cc_idP] = 0;
UE_list->UE_sched_ctrl[UE_id].mcs_offset[cc_idP] = 0;
for (j = 0; j < 8; j++) { for (j = 0; j < 8; j++) {
UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB1] = (j == 0) ? 1 : 0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0 UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB1] = (j == 0) ? 1 : 0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB2] = 1; UE_list->UE_template[cc_idP][UE_id].oldNDI[j][TB2] = 1;
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @ bf4a8849
...@@ -166,6 +166,8 @@ rx_sdu(const module_id_t enb_mod_idP, ...@@ -166,6 +166,8 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_scheduling_control->ul_inactivity_timer = 0; UE_scheduling_control->ul_inactivity_timer = 0;
UE_scheduling_control->ul_failure_timer = 0; UE_scheduling_control->ul_failure_timer = 0;
UE_scheduling_control->ul_scheduled &= (~(1 << harq_pid)); UE_scheduling_control->ul_scheduled &= (~(1 << harq_pid));
UE_scheduling_control->pusch_rx_num[CC_idP]++;
/* Update with smoothing: 3/4 of old value and 1/4 of new. /* Update with smoothing: 3/4 of old value and 1/4 of new.
* This is the logic that was done in the function * This is the logic that was done in the function
* lte_est_timing_advance_pusch, maybe it's not necessary? * lte_est_timing_advance_pusch, maybe it's not necessary?
...@@ -206,6 +208,7 @@ rx_sdu(const module_id_t enb_mod_idP, ...@@ -206,6 +208,7 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_template_ptr->scheduled_ul_bytes = 0; UE_template_ptr->scheduled_ul_bytes = 0;
} }
} else { // sduP == NULL => error } else { // sduP == NULL => error
UE_scheduling_control->pusch_rx_error_num[CC_idP]++;
LOG_W(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x\n", LOG_W(MAC, "[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x\n",
enb_mod_idP, enb_mod_idP,
harq_pid, harq_pid,
......
openair2/LAYER2/MAC/mac.h
View file @ bf4a8849
...@@ -923,6 +923,10 @@ typedef struct { ...@@ -923,6 +923,10 @@ typedef struct {
uint32_t pucch_tpc_tx_frame; uint32_t pucch_tpc_tx_frame;
uint32_t pucch_tpc_tx_subframe; uint32_t pucch_tpc_tx_subframe;
/// stores the frame where the last bler was calculated
uint32_t pusch_bler_calc_frame;
uint32_t pusch_bler_calc_subframe;
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) #if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
uint8_t rach_resource_type; uint8_t rach_resource_type;
...@@ -1002,6 +1006,12 @@ typedef struct { ...@@ -1002,6 +1006,12 @@ typedef struct {
uint8_t pusch_snr[NFAPI_CC_MAX]; uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX]; uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX]; uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint64_t pusch_rx_num[NFAPI_CC_MAX];
uint64_t pusch_rx_num_old[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num_old[NFAPI_CC_MAX];
double pusch_bler[NFAPI_CC_MAX];
uint8_t mcs_offset[NFAPI_CC_MAX];
uint16_t feedback_cnt[NFAPI_CC_MAX]; uint16_t feedback_cnt[NFAPI_CC_MAX];
uint16_t timing_advance; uint16_t timing_advance;
uint16_t timing_advance_r9; uint16_t timing_advance_r9;
......
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