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Commit d383cd52 authored by Florian Kaltenberger's avatar Florian Kaltenberger
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Merge branch 'nr_pdcch_updates' into 'develop-nr' 

Nr pdcch updates

See merge request oai/openairinterface5g!516
parents f1e30d57 bad87bd1
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Showing with 145 additions and 201 deletions
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
View file @ d383cd52
...@@ -36,7 +36,6 @@ ...@@ -36,7 +36,6 @@
#include "nr_dlsch.h" #include "nr_dlsch.h"
void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) { void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) {
nr_cce_t* cce; nr_cce_t* cce;
...@@ -48,6 +47,8 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -48,6 +47,8 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
uint8_t R = pdcch_params->interleaver_size; uint8_t R = pdcch_params->interleaver_size;
uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb; uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb;
uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C; uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C;
uint16_t n_RNTI = (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params->rnti:0;
uint32_t A[3]={39827,39829,39839};
if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1) if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
...@@ -59,6 +60,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -59,6 +60,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON) if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON)
Y = 0; Y = 0;
else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
Y = (A[0]*n_RNTI)%65537; // Candidate 0, antenna port 0
} }
if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
...@@ -111,6 +113,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -111,6 +113,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
} }
} }
/*static inline uint64_t dci_field(uint64_t field, uint8_t size) {
uint64_t ret = 0;
for (int i=0; i<size; i++)
ret |= ((field>>i)&1)<<(size-i-1);
return ret;
}*/
void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
int frame, int frame,
int subframe, int subframe,
...@@ -156,38 +165,38 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -156,38 +165,38 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
case NFAPI_NR_DL_DCI_FORMAT_1_0: case NFAPI_NR_DL_DCI_FORMAT_1_0:
switch(params_rel15->rnti_type) { switch(params_rel15->rnti_type) {
case NFAPI_NR_RNTI_RA: case NFAPI_NR_RNTI_RA:
// printf("dci_pdu %llx\n",(unsigned long long int)*dci_pdu);
// Freq domain assignment // Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize; pos=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("frequency-domain assignment %d (%d bits)=> %d (%llx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("frequency-domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// Time domain assignment // Time domain assignment
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("time-domain assignment %d (3 bits)=> %d (%llx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("time-domain assignment %d (3 bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// VRB to PRB mapping // VRB to PRB mapping
pos++; pos++;
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("vrb to prb mapping %d (1 bits)=> %d (%llx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// MCS // MCS
pos+=5; pos+=5;
*dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("mcs %d (5 bits)=> %d (%llx)\n",pdu_rel15->mcs,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("mcs %d (5 bits)=> %d (0x%lx)\n",pdu_rel15->mcs,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// TB scaling // TB scaling
pos+=2; pos+=2;
*dci_pdu |= (pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("tb_scaling %d (2 bits)=> %d (%llx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("tb_scaling %d (2 bits)=> %d (0x%lx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,*dci_pdu);
#endif #endif
break; break;
...@@ -195,14 +204,27 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -195,14 +204,27 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("Format indicator %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->format_indicator,1,dci_alloc->size-pos,*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16) // Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize; pos+=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos)); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu);
#endif
if (((pdu_rel15->frequency_domain_assignment+1)&1) ==0) //fsize are all 1 38.212 p86 uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
if (!((pdu_rel15->frequency_domain_assignment>>i)&1)) {
is_ra = 0;
break;
}
if (is_ra) //fsize are all 1 38.212 p86
{ {
// ra_preamble_index 6 bits // ra_preamble_index 6 bits
pos+=6; pos+=6;
...@@ -228,42 +250,72 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -228,42 +250,72 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("Time domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,4,dci_alloc->size-pos,*dci_pdu);
#endif
// VRB to PRB mapping 1bit // VRB to PRB mapping 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("VRB to PRB %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,1,dci_alloc->size-pos,*dci_pdu);
#endif
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
pos+=5; pos+=5;
*dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("MCS %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->mcs,5,dci_alloc->size-pos,*dci_pdu);
#endif
// New data indicator 1bit // New data indicator 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("NDI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->ndi,1,dci_alloc->size-pos,*dci_pdu);
#endif
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; pos+=2;
*dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("RV %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->rv,2,dci_alloc->size-pos,*dci_pdu);
#endif
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("HARQ_PID %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->harq_pid,4,dci_alloc->size-pos,*dci_pdu);
#endif
// Downlink assignment index 2bit // Downlink assignment index 2bit
pos+=2; pos+=2;
*dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("DAI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->dai,2,dci_alloc->size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; pos+=2;
*dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("TPC %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->tpc,2,dci_alloc->size-pos,*dci_pdu);
#endif
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("PUCCH RI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pucch_resource_indicator,3,dci_alloc->size-pos,*dci_pdu);
#endif
// PDSCH-to-HARQ_feedback timing indicator 3bit // PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_alloc->size-pos,*dci_pdu);
#endif
} //end else } //end else
break; break;
...@@ -272,26 +324,26 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -272,26 +324,26 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// Short Messages Indicator – 2 bits // Short Messages Indicator – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++);
// Short Messages – 8 bits // Short Messages – 8 bits
for (int i=0; i<8; i++) for (int i=0; i<8; i++)
*dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// TB scaling 2 bit // TB scaling 2 bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++);
break; break;
...@@ -303,49 +355,49 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -303,49 +355,49 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
break; break;
case NFAPI_NR_RNTI_TC: case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// Downlink assignment index – 2 bits // Downlink assignment index – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUCCH – 2 bits // TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// LOG_I(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", // LOG_I(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n",
...@@ -354,49 +406,50 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -354,49 +406,50 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// PDSCH-to-HARQ_feedback timing indicator – 3 bits // PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++) for (int i=0; i<3; i++)
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++);
break; break;
} }
break;
case NFAPI_NR_UL_DCI_FORMAT_0_0: case NFAPI_NR_UL_DCI_FORMAT_0_0:
switch(params_rel15->rnti_type) switch(params_rel15->rnti_type)
{ {
case NFAPI_NR_RNTI_C: case NFAPI_NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++);
break; break;
...@@ -410,39 +463,39 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -410,39 +463,39 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++);
break; break;
} }
break; break;
} }
LOG_I(PHY, "DCI PDU: [0]->0x%16llxx \t [1]->0x%16llx \n",(long long unsigned int)dci_pdu[0], (long long unsigned int)dci_pdu[1]); LOG_I(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]);
LOG_I(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); LOG_I(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx);
/// DLSCH struct /// DLSCH struct
......
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
View file @ d383cd52
...@@ -338,11 +338,9 @@ ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol); ...@@ -338,11 +338,9 @@ ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol);
for (int l=rel15->start_symbol; l<rel15->start_symbol+rel15->nb_symbols; l++) { for (int l=rel15->start_symbol; l<rel15->start_symbol+rel15->nb_symbols; l++) {
k = start_sc; k = start_sc;
for (int i=0; i<rel15->n_prb*NR_NB_SC_PER_RB; i++) { for (int i=0; i<rel15->n_prb*NR_NB_SC_PER_RB; i++) {
// Note the dmrs index modulo 2048 only works for that symbol size -- to be fixed soon if ((l == dmrs_symbol) && (k == ((start_sc+get_pdsch_dmrs_idx(n, k_prime, delta, dmrs_type))%(frame_parms.ofdm_symbol_size)))) {
// Also the different amplitudes are for debug purposes and temporary ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (Wt[l_prime[0]]*Wf[k_prime]*amp*mod_dmrs[dmrs_idx<<1]) >> 15;
if ((l == dmrs_symbol) && (k == ((start_sc+get_pdsch_dmrs_idx(n, k_prime, delta, dmrs_type))&((1<<11)-1)))) { ((int16_t*)txdataF[ap])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (Wt[l_prime[0]]*Wf[k_prime]*amp*mod_dmrs[(dmrs_idx<<1) + 1]) >> 15;
((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (Wt[l_prime[0]]*Wf[k_prime]*(amp>>1)*mod_dmrs[dmrs_idx<<1]) >> 15;
((int16_t*)txdataF[ap])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (Wt[l_prime[0]]*Wf[k_prime]*(amp>>1)*mod_dmrs[(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_DLSCH_MAPPING #ifdef DEBUG_DLSCH_MAPPING
printf("dmrs_idx %d\t l %d \t k %d \t k_prime %d \t n %d \t txdataF: %d %d\n", printf("dmrs_idx %d\t l %d \t k %d \t k_prime %d \t n %d \t txdataF: %d %d\n",
dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1], dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1],
...@@ -356,8 +354,8 @@ dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_s ...@@ -356,8 +354,8 @@ dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_s
else { else {
((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1] = ((amp<<1) * tx_layers[ap][m<<1]) >> 15; ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * tx_layers[ap][m<<1]) >> 15;
((int16_t*)txdataF[ap])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp<<1) * tx_layers[ap][(m<<1) + 1]) >> 15; ((int16_t*)txdataF[ap])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15;
#ifdef DEBUG_DLSCH_MAPPING #ifdef DEBUG_DLSCH_MAPPING
printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", printf("m %d\t l %d \t k %d \t txdataF: %d %d\n",
m, l, k, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1], m, l, k, ((int16_t*)txdataF[ap])[(l*frame_parms.ofdm_symbol_size + k)<<1],
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ d383cd52
...@@ -1439,10 +1439,10 @@ void nr_dci_decoding_procedure0(int s, ...@@ -1439,10 +1439,10 @@ void nr_dci_decoding_procedure0(int s,
*crc_scrambled =_tpc_srs_rnti; *crc_scrambled =_tpc_srs_rnti;
*format_found=_format_2_3_found; *format_found=_format_2_3_found;
} }
#ifdef NR_PDCCH_DCI_DEBUG //#ifdef NR_PDCCH_DCI_DEBUG
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> format_found=%d\n",*format_found); printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> format_found=%d\n",*format_found);
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> crc_scrambled=%d\n",*crc_scrambled); printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> crc_scrambled=%d\n",*crc_scrambled);
#endif //#endif
if (*format_found!=255) { if (*format_found!=255) {
dci_alloc[*dci_cnt].dci_length = sizeof_bits; dci_alloc[*dci_cnt].dci_length = sizeof_bits;
dci_alloc[*dci_cnt].rnti = crc; dci_alloc[*dci_cnt].rnti = crc;
...@@ -1453,10 +1453,10 @@ void nr_dci_decoding_procedure0(int s, ...@@ -1453,10 +1453,10 @@ void nr_dci_decoding_procedure0(int s,
dci_alloc[*dci_cnt].dci_pdu[2] = dci_estimation[2]; dci_alloc[*dci_cnt].dci_pdu[2] = dci_estimation[2];
dci_alloc[*dci_cnt].dci_pdu[3] = dci_estimation[3]; dci_alloc[*dci_cnt].dci_pdu[3] = dci_estimation[3];
//#ifdef NR_PDCCH_DCI_DEBUG //#ifdef NR_PDCCH_DCI_DEBUG
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> rnti matches -> DCI FOUND !!! crc =>%x, sizeof_bits %d, sizeof_bytes %d \n", printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> rnti matches -> DCI FOUND !!! crc =>0x%x, sizeof_bits %d, sizeof_bytes %d \n",
dci_alloc[*dci_cnt].rnti, dci_alloc[*dci_cnt].dci_length, sizeof_bytes); dci_alloc[*dci_cnt].rnti, dci_alloc[*dci_cnt].dci_length, sizeof_bytes);
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> dci_cnt %d (format_css %d crc_scrambled %d) L %d, firstCCE %d pdu[0] %x pdu[1] %x pdu[2] %x pdu[3] %x \n", printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> dci_cnt %d (format_css %d crc_scrambled %d) L %d, firstCCE %d pdu[0] 0x%lx pdu[1] 0x%lx \n",
*dci_cnt, format_css,*crc_scrambled,dci_alloc[*dci_cnt].L, dci_alloc[*dci_cnt].firstCCE,dci_alloc[*dci_cnt].dci_pdu[0],dci_alloc[*dci_cnt].dci_pdu[1],dci_alloc[*dci_cnt].dci_pdu[2],dci_alloc[*dci_cnt].dci_pdu[3]); *dci_cnt, format_css,*crc_scrambled,dci_alloc[*dci_cnt].L, dci_alloc[*dci_cnt].firstCCE,dci_alloc[*dci_cnt].dci_pdu[0],dci_alloc[*dci_cnt].dci_pdu[1]);
//#endif //#endif
if ((format_css == cformat0_0_and_1_0) || (format_uss == uformat0_0_and_1_0)){ if ((format_css == cformat0_0_and_1_0) || (format_uss == uformat0_0_and_1_0)){
if ((*crc_scrambled == _p_rnti) || (*crc_scrambled == _si_rnti) || (*crc_scrambled == _ra_rnti)){ if ((*crc_scrambled == _p_rnti) || (*crc_scrambled == _si_rnti) || (*crc_scrambled == _ra_rnti)){
......
openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
View file @ d383cd52
...@@ -52,7 +52,7 @@ ...@@ -52,7 +52,7 @@
//#define DEBUG_DCI //#define DEBUG_DCI
#define NR_PDCCH_DCI_TOOLS #define NR_PDCCH_DCI_TOOLS
//#define NR_PDCCH_DCI_TOOLS_DEBUG #define NR_PDCCH_DCI_TOOLS_DEBUG
typedef unsigned __int128 uint128_t; typedef unsigned __int128 uint128_t;
...@@ -64,17 +64,10 @@ int8_t *nr_delta_PUCCH_lut = nr_delta_PUSCH_acc; ...@@ -64,17 +64,10 @@ int8_t *nr_delta_PUCCH_lut = nr_delta_PUSCH_acc;
#ifdef NR_PDCCH_DCI_TOOLS #ifdef NR_PDCCH_DCI_TOOLS
uint16_t nr_dci_field(uint32_t dci_pdu[4], uint16_t nr_dci_field(uint64_t dci_pdu[2],
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS], uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS],
uint8_t dci_field) uint8_t dci_field)
{ {
// uint16_t field_value = 0 ;
// first_bit_position contains the position of the first bit of the corresponding field within the dci pdu payload
// last_bit_position contains the position of the last bit of the corresponding field within the dci pdu payload
// uint16_t last_bit_position = 0;
// uint8_t bit=0;
//printf("\tdci_field=%d, \tsize=%d \t|",dci_field,dci_fields_sizes[dci_field]);
int dci_size=0; int dci_size=0;
for (int i=0;i<NBR_NR_DCI_FIELDS;i++) dci_size+=dci_fields_sizes[i]; for (int i=0;i<NBR_NR_DCI_FIELDS;i++) dci_size+=dci_fields_sizes[i];
...@@ -87,25 +80,13 @@ uint16_t nr_dci_field(uint32_t dci_pdu[4], ...@@ -87,25 +80,13 @@ uint16_t nr_dci_field(uint32_t dci_pdu[4],
for (int i=0; i<=dci_field ; i++){ for (int i=0; i<=dci_field ; i++){
first_bit_position = first_bit_position - dci_fields_sizes[i]; first_bit_position = first_bit_position - dci_fields_sizes[i];
} }
// last_bit_position = first_bit_position + dci_fields_sizes[dci_field];
//printf("\tfirst_bit=%d,\tlast_bit=%d",first_bit_position,last_bit_position);
/*
for (int i=0; i<4; i++)
for (int j=0; j<32; j++){
if ((((i*32)+j) >= first_bit_position) && (((i*32)+j) < last_bit_position)){
bit = (dci_pdu[i]<<(31-j))>>31;
field_value = (field_value<<1) + bit;
//printf(" bit(%d)=%d[%d] ",(i*32)+j,bit,field_value);
}
}
*/
uint64_t *dci_pdu64=(uint64_t*)&dci_pdu[0]; /*uint16_t tmp1 = ((*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
/* uint16_t tmp2 = 0;
printf("pdu %llx, field %d, pos %d, size %d => %u\n",(long long unsigned int)*dci_pdu64,dci_field,first_bit_position,dci_fields_sizes[dci_field], for (int i=0; i<dci_fields_sizes[dci_field]; i++)
(unsigned int)((*dci_pdu64>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1)));*/ tmp2 |= ((tmp1>>i)&1)<<(dci_fields_sizes[dci_field]-i-1);*/
return (uint16_t)((*dci_pdu64>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1)); return ((uint16_t)(*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
} }
int nr_extract_dci_info(PHY_VARS_NR_UE *ue, int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
...@@ -113,7 +94,7 @@ int nr_extract_dci_info(PHY_VARS_NR_UE *ue, ...@@ -113,7 +94,7 @@ int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
lte_frame_type_t frame_type, lte_frame_type_t frame_type,
uint8_t dci_length, uint8_t dci_length,
uint16_t rnti, uint16_t rnti,
uint32_t dci_pdu[4], uint64_t dci_pdu[2],
NR_DCI_INFO_EXTRACTED_t *nr_pdci_info_extracted, NR_DCI_INFO_EXTRACTED_t *nr_pdci_info_extracted,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS], uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
NR_DL_UE_HARQ_t *pdlsch0_harq, NR_DL_UE_HARQ_t *pdlsch0_harq,
...@@ -312,8 +293,8 @@ int nr_extract_dci_info(PHY_VARS_NR_UE *ue, ...@@ -312,8 +293,8 @@ int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
// uint8_t sizes_count=0; // uint8_t sizes_count=0;
// uint8_t left_shift=0; // uint8_t left_shift=0;
#ifdef NR_PDCCH_DCI_TOOLS_DEBUG #ifdef NR_PDCCH_DCI_TOOLS_DEBUG
printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) -> Entering function nr_extract_dci_info() with dci_pdu=%x %x %x %x dci_length=%d\n", printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) -> Entering function nr_extract_dci_info() with dci_pdu=%lx %lx dci_length=%d\n",
dci_pdu[0],dci_pdu[1],dci_pdu[2],dci_pdu[3], dci_length); dci_pdu[0],dci_pdu[1], dci_length);
printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) -> for format %d, dci_fields_sizes {",dci_format); printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) -> for format %d, dci_fields_sizes {",dci_format);
for (int i=0; i<NBR_NR_DCI_FIELDS; i++) printf("%d ",dci_fields_sizes[i][dci_format]); for (int i=0; i<NBR_NR_DCI_FIELDS; i++) printf("%d ",dci_fields_sizes[i][dci_format]);
printf("}\n"); printf("}\n");
...@@ -1040,7 +1021,7 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, ...@@ -1040,7 +1021,7 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t eNB_id, uint8_t eNB_id,
int frame, int frame,
uint8_t nr_tti_rx, uint8_t nr_tti_rx,
uint32_t dci_pdu[4], uint64_t dci_pdu[2],
uint16_t rnti, uint16_t rnti,
uint8_t dci_length, uint8_t dci_length,
NR_DCI_format_t dci_format, NR_DCI_format_t dci_format,
...@@ -1074,8 +1055,8 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue, ...@@ -1074,8 +1055,8 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t status=0; uint8_t status=0;
#ifdef NR_PDCCH_DCI_TOOLS_DEBUG #ifdef NR_PDCCH_DCI_TOOLS_DEBUG
printf("\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci) -> dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=%x, dci_pdu[2]=%x, dci_pdu[2]=%x, dci_pdu[3]=%x\n", printf("\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci) -> dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",
dci_format,rnti,dci_length,dci_pdu[0],dci_pdu[1],dci_pdu[2],dci_pdu[3]); dci_format,rnti,dci_length,dci_pdu[0],dci_pdu[1]);
#endif #endif
......
openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
View file @ d383cd52
...@@ -394,7 +394,7 @@ typedef struct { ...@@ -394,7 +394,7 @@ typedef struct {
/// search space /// search space
dci_space_t search_space; dci_space_t search_space;
/// DCI pdu /// DCI pdu
uint32_t dci_pdu[4]; uint64_t dci_pdu[2];
//#if defined(UPGRADE_RAT_NR) //#if defined(UPGRADE_RAT_NR)
#if 1 #if 1
/// harq information /// harq information
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ d383cd52
...@@ -100,7 +100,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, ...@@ -100,7 +100,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
params_rel15->first_slot = 0; params_rel15->first_slot = 0;
pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value); pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value);
pdu_rel15->time_domain_assignment = get_SLIV(dlsch_pdu_rel15->start_symbol, dlsch_pdu_rel15->nb_symbols); pdu_rel15->time_domain_assignment = 3; // row index used here instead of SLIV
pdu_rel15->vrb_to_prb_mapping = 1; pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 9; pdu_rel15->mcs = 9;
pdu_rel15->tb_scaling = 1; pdu_rel15->tb_scaling = 1;
...@@ -229,7 +229,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ...@@ -229,7 +229,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
dlsch_pdu_rel15->start_prb = 0; dlsch_pdu_rel15->start_prb = 0;
dlsch_pdu_rel15->n_prb = 50; dlsch_pdu_rel15->n_prb = 50;
dlsch_pdu_rel15->start_symbol = 2; dlsch_pdu_rel15->start_symbol = 2;
dlsch_pdu_rel15->nb_symbols = 8; dlsch_pdu_rel15->nb_symbols = 9;
dlsch_pdu_rel15->rnti = rnti; dlsch_pdu_rel15->rnti = rnti;
dlsch_pdu_rel15->nb_layers =1; dlsch_pdu_rel15->nb_layers =1;
dlsch_pdu_rel15->nb_codewords = 1; dlsch_pdu_rel15->nb_codewords = 1;
...@@ -244,7 +244,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ...@@ -244,7 +244,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
dl_carrier_bandwidth); dl_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value); pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value);
pdu_rel15->time_domain_assignment = get_SLIV(dlsch_pdu_rel15->start_symbol, dlsch_pdu_rel15->nb_symbols); pdu_rel15->time_domain_assignment = 3; // row index used here instead of SLIV;
pdu_rel15->vrb_to_prb_mapping = 1; pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 9; pdu_rel15->mcs = 9;
pdu_rel15->tb_scaling = 1; pdu_rel15->tb_scaling = 1;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ d383cd52
...@@ -408,94 +408,6 @@ void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel1 ...@@ -408,94 +408,6 @@ void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel1
//searchSpaceType //searchSpaceType
pdcch_params->search_space_type = search_space->search_space_type; pdcch_params->search_space_type = search_space->search_space_type;
/*
//searchSpaceId
AssertFatal(search_space->search_space_id<40, "Search space index out of range %d\n", search_space->search_space_id);
//controlResourceSetId
//monitoringSlotPeriodicityAndOffset
//duration
pdcch_params->nb_ss_sets_per_slot = search_space->duration;
//monitoringSymbolsWithinSlot
pdcch_params->first_symbol = search_space->monitoring_symbols_in_slot;
//nrofCandidates
pdcch_params->aggregation_level = (uint8_t)number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS - 1];
//Common_CSS
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON){
switch(search_space->css_formats_0_0_and_1_0){
case NFAPI_NR_RNTI_C:
pdcch_params->rnti_type = NFAPI_NR_RNTI_C;
break;
case NFAPI_NR_RNTI_CS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_CS;
break;
case NFAPI_NR_RNTI_SP_CSI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SP_CSI;
break;
case NFAPI_NR_RNTI_RA:
pdcch_params->rnti_type = NFAPI_NR_RNTI_RA;
break;
case NFAPI_NR_RNTI_TC:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TC;
break;
case NFAPI_NR_RNTI_P:
pdcch_params->rnti_type = NFAPI_NR_RNTI_P;
break;
case NFAPI_NR_RNTI_SI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SI;
break;
}
switch (search_space->css_format_2_0){
case NFAPI_NR_RNTI_SFI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SFI;
break;
}
switch (search_space->css_format_2_1){
case NFAPI_NR_RNTI_INT:
pdcch_params->rnti_type = NFAPI_NR_RNTI_INT;
break;
}
switch (search_space->css_format_2_2){
case NFAPI_NR_RNTI_TPC_PUSCH:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_PUSCH;
break;
case NFAPI_NR_RNTI_TPC_PUCCH:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_PUCCH;
break;
}
switch (search_space->css_format_2_3){
case NFAPI_NR_RNTI_TPC_SRS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_SRS;
break;
}
}
//Ue_Specific_USS
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC){
switch (search_space->uss_dci_formats){
case NFAPI_NR_RNTI_C:
pdcch_params->rnti_type = NFAPI_NR_RNTI_C;
break;
case NFAPI_NR_RNTI_CS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_CS;
break;
case NFAPI_NR_RNTI_SP_CSI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SP_CSI;
break;
}
}
*/
pdcch_params->n_RB_BWP = N_RB; pdcch_params->n_RB_BWP = N_RB;
} }
......
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