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Commit ffed6b71 authored by Stefan's avatar Stefan
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SSR 20/12/18 ulsch_scheduler_pre_processor

parent 076d4e12
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Showing with 148 additions and 177 deletions
openair2/LAYER2/MAC/pre_processor.c
View file @ ffed6b71
......@@ -1605,24 +1605,22 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
unsigned char sched_subframeP,
uint16_t *first_rb)
{
int16_t i;
uint16_t UE_id, n, r;
uint16_t UE_id, n;
uint8_t CC_id, harq_pid;
uint16_t nb_allocated_rbs[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB];
uint16_t total_allocated_rbs[NFAPI_CC_MAX];
uint16_t average_rbs_per_user[NFAPI_CC_MAX];
int16_t total_remaining_rbs[NFAPI_CC_MAX];
uint16_t total_ue_count[NFAPI_CC_MAX];
rnti_t rnti = -1;
UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
slice_info_t *sli = &RC.mac[module_idP]->slice_info;
UE_TEMPLATE *UE_template = 0;
UE_sched_ctrl *ue_sched_ctl;
int N_RB_UL = 0;
uint16_t available_rbs, first_rb_offset;
rnti_t rntiTable[MAX_MOBILES_PER_ENB];
bool continueTable[MAX_MOBILES_PER_ENB];
bool sliceMember;
rnti_t rntiTable[MAX_MOBILES_PER_ENB]; // Rnti array => Add SSR 12-2018
bool continueTable[MAX_MOBILES_PER_ENB]; // Loop continue flag array => Add SSR 12-2018
bool sliceMember; // Slice membership flag => Add SSR 12-2018
LOG_D(MAC, "In ulsch_preprocessor: assign max mcs min rb\n");
// maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
......@@ -1635,7 +1633,8 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
// we need to distribute RBs among UEs
// step1: reset the vars
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) {
uint8_t CC_nb = (uint8_t) RC.nb_mac_CC[module_idP];
for (CC_id = 0; CC_id < CC_nb; CC_id++) {
total_allocated_rbs[CC_id] = 0;
total_remaining_rbs[CC_id] = 0;
average_rbs_per_user[CC_id] = 0;
......@@ -1643,7 +1642,16 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
}
// Step 1.5: Calculate total_ue_count
for (UE_id = UE_list->head_ul; UE_id >= 0; i = UE_list->next_ul[UE_id]) {
for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
// Calculate continue condition
/*
if (UE_RNTI(module_idP, UE_id) == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
if (!ue_ul_slice_membership(module_idP, UE_id, slice_idx))
continue;
*/
rntiTable[UE_id] = UE_RNTI(module_idP, UE_id);
sliceMember = ue_ul_slice_membership(module_idP, UE_id, slice_idx);
continueTable[UE_id] = (rntiTable[UE_id] == NOT_A_RNTI || UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1 || !sliceMember);
......@@ -1653,7 +1661,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
if (UE_template->pre_allocated_nb_rb_ul[slice_idx] > 0) {
total_ue_count[CC_id] += 1;
total_ue_count[CC_id]++;
}
}
}
......@@ -1661,18 +1669,8 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
LOG_D(MAC, "In ulsch_preprocessor: step2 \n");
// step 2: calculate the average rb per UE
for (UE_id = UE_list->head_ul; UE_id >= 0; i = UE_list->next_ul[UE_id]) {
for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
if (continueTable[UE_id]) continue;
/*
rnti = UE_RNTI(module_idP, i);
UE_id = i;
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
continue;
if (!ue_ul_slice_membership(module_idP, UE_id, slice_idx))
continue;
*/
LOG_D(MAC, "In ulsch_preprocessor: handling UE %d/%x\n", UE_id,
rntiTable[UE_id]);
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
......@@ -1719,16 +1717,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
// step 3: assigne RBS
for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
if (continueTable[UE_id]) continue;
/*
rnti = UE_RNTI(module_idP, i);
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
continue;
if (!ue_ul_slice_membership(module_idP, i, slice_idx))
continue;
UE_id = i;
*/
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
......@@ -1742,8 +1731,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
nb_allocated_rbs[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid];
} else {
nb_allocated_rbs[CC_id][UE_id] =
cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_idx],
average_rbs_per_user[CC_id]);
cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_idx], average_rbs_per_user[CC_id]);
}
total_allocated_rbs[CC_id] += nb_allocated_rbs[CC_id][UE_id];
......@@ -1755,47 +1743,31 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
}
// step 4: assigne the remaining RBs and set the pre_allocated rbs accordingly
for (r = 0; r < 2; r++) {
for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
if (continueTable[UE_id]) continue;
/*
rnti = UE_RNTI(module_idP, i);
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
continue;
if (!ue_ul_slice_membership(module_idP, i, slice_idx))
continue;
UE_id = i;
*/
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
if (r == 0) {
N_RB_UL = to_prb(RC.mac[module_idP]->common_channels[CC_id].ul_Bandwidth);
first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx];
available_rbs = cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx],
N_RB_UL - first_rb[CC_id] - first_rb_offset);
available_rbs = cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset);
total_remaining_rbs[CC_id] = available_rbs - total_allocated_rbs[CC_id];
if (total_ue_count[CC_id] == 1) {
total_remaining_rbs[CC_id] += 1;
total_remaining_rbs[CC_id]++;
}
while ((UE_template->pre_allocated_nb_rb_ul[slice_idx] > 0)
&& (nb_allocated_rbs[CC_id][UE_id] < UE_template->pre_allocated_nb_rb_ul[slice_idx])
&& (total_remaining_rbs[CC_id] > 0)) {
nb_allocated_rbs[CC_id][UE_id] =
cmin(nb_allocated_rbs[CC_id][UE_id] + 1,
UE_template->pre_allocated_nb_rb_ul[slice_idx]);
nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id] + 1, UE_template->pre_allocated_nb_rb_ul[slice_idx]);
total_remaining_rbs[CC_id]--;
total_allocated_rbs[CC_id]++;
}
} else {
UE_template->pre_allocated_nb_rb_ul[slice_idx] = nb_allocated_rbs[CC_id][UE_id];
LOG_D(MAC, "******************UL Scheduling Information for UE%d CC_id %d ************************\n",
UE_id, CC_id);
......@@ -1803,8 +1775,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
module_idP, UE_id, CC_id, UE_template->pre_allocated_nb_rb_ul[slice_idx]);
}
}
}
}
return;
}
void
......
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