Commit 0a437ce1 authored by ChiehChun's avatar ChiehChun

Change vrb_map to rballoc_mask

parent f0a1c099
...@@ -348,6 +348,20 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -348,6 +348,20 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
/* Calculate num of RBG and RBG size from UE_id=0 */
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
uint8_t rballoc_mask[bwpSize];
int n_rb_sched = 0;
for (int i = 0; i < bwpSize; i++) {
// calculate mask: init with "NOT" vrb_map:
// if any RB in vrb_map is blocked (1), the current RBG will be 0
rballoc_mask[i] = !vrb_map[i];
n_rb_sched += rballoc_mask[i];
}
/* Retrieve amount of data to send for this UE */ /* Retrieve amount of data to send for this UE */
sched_ctrl->num_total_bytes = 0; sched_ctrl->num_total_bytes = 0;
const int lcid = DL_SCH_LCID_DTCH; const int lcid = DL_SCH_LCID_DTCH;
...@@ -417,13 +431,10 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -417,13 +431,10 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
return; return;
} }
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
// for now HARQ PID is fixed and should be the same as in post-processor // for now HARQ PID is fixed and should be the same as in post-processor
const int current_harq_pid = slot % 8; const int current_harq_pid = slot % 8;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid]; NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
NR_UE_ret_info_t *retInfo = &sched_ctrl->retInfo[current_harq_pid]; NR_UE_ret_info_t *retInfo = &sched_ctrl->retInfo[current_harq_pid];
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
if (harq->round != 0) { /* retransmission */ if (harq->round != 0) { /* retransmission */
sched_ctrl->time_domain_allocation = retInfo->time_domain_allocation; sched_ctrl->time_domain_allocation = retInfo->time_domain_allocation;
...@@ -433,7 +444,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -433,7 +444,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
while (rbSize < retInfo->rbSize) { while (rbSize < retInfo->rbSize) {
rbStart += rbSize; /* last iteration rbSize was not enough, skip it */ rbStart += rbSize; /* last iteration rbSize was not enough, skip it */
rbSize = 0; rbSize = 0;
while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++; while (rbStart < bwpSize && !rballoc_mask[rbStart]) rbStart++;
if (rbStart >= bwpSize) { if (rbStart >= bwpSize) {
LOG_E(MAC, LOG_E(MAC,
"cannot allocate retransmission for UE %d/RNTI %04x: no resources\n", "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n",
...@@ -442,7 +453,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -442,7 +453,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
return; return;
} }
while (rbStart + rbSize < bwpSize while (rbStart + rbSize < bwpSize
&& !vrb_map[rbStart + rbSize] && rballoc_mask[rbStart + rbSize]
&& rbSize < retInfo->rbSize) && rbSize < retInfo->rbSize)
rbSize++; rbSize++;
} }
...@@ -463,7 +474,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -463,7 +474,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
sched_ctrl->numDmrsCdmGrpsNoData = 1; sched_ctrl->numDmrsCdmGrpsNoData = 1;
// Freq-demain allocation // Freq-demain allocation
while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++; while (rbStart < bwpSize && !rballoc_mask[rbStart]) rbStart++;
uint8_t N_PRB_DMRS = uint8_t N_PRB_DMRS =
getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData); getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
...@@ -486,14 +497,16 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -486,14 +497,16 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
0 /* tb_scaling */, 0 /* tb_scaling */,
1 /* nrOfLayers */) 1 /* nrOfLayers */)
>> 3; >> 3;
} while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize] && TBS < sched_ctrl->num_total_bytes + oh); } while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart + rbSize] && TBS < sched_ctrl->num_total_bytes + oh);
sched_ctrl->rbSize = rbSize; sched_ctrl->rbSize = rbSize;
sched_ctrl->rbStart = rbStart; sched_ctrl->rbStart = rbStart;
} }
/* mark the corresponding RBs as used */ /* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_ctrl->rbSize; rb++) for (int rb = 0; rb < sched_ctrl->rbSize; rb++) {
vrb_map[rb + sched_ctrl->rbStart] = 1; vrb_map[rb + sched_ctrl->rbStart] = 1;
rballoc_mask[rb + sched_ctrl->rbStart] = 0;
}
} }
void nr_schedule_ue_spec(module_id_t module_id, void nr_schedule_ue_spec(module_id_t module_id,
......
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