Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
O
OpenXG-RAN
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
wangjie
OpenXG-RAN
Commits
1eb44387
Commit
1eb44387
authored
Mar 04, 2021
by
Francesco Mani
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
bugfix in csirs vrb map occupation
parent
4e6fb20f
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
17 additions
and
17 deletions
+17
-17
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+17
-17
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
1eb44387
...
...
@@ -1871,20 +1871,20 @@ void nr_csirs_scheduling(int Mod_idP,
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1
:
csirs_pdu_rel15
->
row
=
1
;
csirs_pdu_rel15
->
freq_domain
=
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row1
.
buf
[
0
])
>>
4
)
&
0x0f
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row2
:
csirs_pdu_rel15
->
row
=
2
;
csirs_pdu_rel15
->
freq_domain
=
(((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row1
.
buf
[
1
]
>>
4
)
&
0x0f
)
|
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row1
.
buf
[
0
]
<<
8
)
&
0xf0
));
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row4
:
csirs_pdu_rel15
->
row
=
4
;
csirs_pdu_rel15
->
freq_domain
=
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row1
.
buf
[
0
])
>>
5
)
&
0x0f
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other
:
...
...
@@ -1895,18 +1895,18 @@ void nr_csirs_scheduling(int Mod_idP,
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p2
:
csirs_pdu_rel15
->
row
=
3
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p4
:
csirs_pdu_rel15
->
row
=
5
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p8
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
8
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
else
{
...
...
@@ -1915,12 +1915,12 @@ void nr_csirs_scheduling(int Mod_idP,
num_k
+=
(((
csirs_pdu_rel15
->
freq_domain
)
>>
k
)
&
0x01
);
if
(
num_k
==
4
)
{
csirs_pdu_rel15
->
row
=
6
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
7
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
}
...
...
@@ -1928,12 +1928,12 @@ void nr_csirs_scheduling(int Mod_idP,
case
NR_CSI_RS_ResourceMapping__nrofPorts_p12
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
10
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
else
{
csirs_pdu_rel15
->
row
=
9
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
}
break
;
...
...
@@ -1942,24 +1942,24 @@ void nr_csirs_scheduling(int Mod_idP,
csirs_pdu_rel15
->
row
=
12
;
else
csirs_pdu_rel15
->
row
=
11
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p24
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
14
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
else
{
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4
)
{
csirs_pdu_rel15
->
row
=
15
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
13
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
}
...
...
@@ -1967,18 +1967,18 @@ void nr_csirs_scheduling(int Mod_idP,
case
NR_CSI_RS_ResourceMapping__nrofPorts_p32
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
17
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
else
{
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4
)
{
csirs_pdu_rel15
->
row
=
18
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
16
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
csirs_pdu_rel15
->
nr_of_rbs
;
rb
++
)
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
)
;
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment