changed coreset settings to match with runel

openair1/PHY/NR_TRANSPORT/nr_dci.c

@@ -213,7 +213,7 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
                  pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value;
   t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_alloc.size, dci_alloc.L);
   printf("DCI PDU old: %lx\n",dci_alloc.dci_pdu[0]);
-  //dci_alloc.dci_pdu[0] = 0x90B478F0000; // To test runel DCI with UE
+  dci_alloc.dci_pdu[0] = 0x90B478F0000; // To test runel DCI with UE
   printf("DCI PDU new: %lx\n",dci_alloc.dci_pdu[0]);
 //  dci_alloc.dci_pdu[1] = 0x0;
   polar_encoder_fast(dci_alloc.dci_pdu, encoder_output, pdcch_params.rnti, 1, currentPtr);

openair1/PHY/NR_TRANSPORT/nr_dci_tools.c

@@ -160,7 +160,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
   dlsch->harq_mask                |= (1<<pdu_rel15->harq_pid);
   dlsch->rnti                      = params_rel15->rnti;
 
-  dci_alloc->L = 8;
+  dci_alloc->L = 4;
   memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t));
   dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format,
 				    dci_alloc->pdcch_params.rnti_type,

openair1/SIMULATION/NR_PHY/dlsim.c

@@ -683,9 +683,9 @@ int main(int argc, char **argv)
   
   uint64_t mask = 0x0;
   uint16_t num_rbs=24;
-  uint16_t rb_offset=gNB->pdcch_vars.dci_alloc[0].pdcch_params.rb_offset;
+  uint16_t rb_offset=120;//gNB->pdcch_vars.dci_alloc[0].pdcch_params.rb_offset;
   uint16_t cell_id=47;
-  uint16_t num_symbols=2;
+  uint16_t num_symbols=1;
   for(i=0; i<(num_rbs/6); ++i){   //  38.331 Each bit corresponds a group of 6 RBs
     mask = mask >> 1;
     mask = mask | 0x100000000000;

openair2/LAYER2/NR_MAC_gNB/main.c

@@ -51,8 +51,8 @@ void set_cset_offset(uint16_t offset_bits) {
 void nr_init_coreset(nfapi_nr_coreset_t *coreset) {
 
   coreset->coreset_id = 1;
-  coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
-  coreset->duration = 2;
+  coreset->frequency_domain_resources = 0x1E00000;//0x1FFFE0000000; // 96 RB starting from CRB0
+  coreset->duration = 1;
   coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
   coreset->reg_bundle_size = 6;
   coreset->interleaver_size = 2;