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Commit 27dd07ea authored by Nick Ho's avatar Nick Ho
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Complete the new way packing DCI and Configure PHY at the same time

parent af9833ff
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Showing with 347 additions and 1976 deletions
cmake_targets/CMakeLists.txt
View file @ 27dd07ea
...@@ -984,6 +984,7 @@ set(PHY_SRC ...@@ -984,6 +984,7 @@ set(PHY_SRC
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dlsch_decoding.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dlsch_decoding.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dlsch_scrambling.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dlsch_scrambling.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_nb_iot.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/uci_tools.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/uci_tools.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/lte_mcs.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/lte_mcs.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/pbch.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/pbch.c
......
openair1/PHY/LTE_TRANSPORT/dci_nb_iot.h
View file @ 27dd07ea
...@@ -68,7 +68,6 @@ struct DCIFormatN0{ ...@@ -68,7 +68,6 @@ struct DCIFormatN0{
}; };
typedef struct DCIFormatN0 DCIFormatN0_t; typedef struct DCIFormatN0 DCIFormatN0_t;
#define sizeof_DDCIFormatN0_t 23
/// DCI Format Type N1 for User data /// DCI Format Type N1 for User data
struct DCIFormatN1{ struct DCIFormatN1{
...@@ -94,7 +93,6 @@ struct DCIFormatN1{ ...@@ -94,7 +93,6 @@ struct DCIFormatN1{
typedef struct DCIFormatN1 DCIFormatN1_t; typedef struct DCIFormatN1 DCIFormatN1_t;
#define sizeof_DCIFormatN1_t 23
/// DCI Format Type N1 for initial RA /// DCI Format Type N1 for initial RA
struct DCIFormatN1_RA{ struct DCIFormatN1_RA{
...@@ -111,7 +109,6 @@ struct DCIFormatN1_RA{ ...@@ -111,7 +109,6 @@ struct DCIFormatN1_RA{
}; };
typedef struct DCIFormatN1_RA DCIFormatN1_RA_t; typedef struct DCIFormatN1_RA DCIFormatN1_RA_t;
#define sizeof_DCIFormatN1_RA_t 23
/// DCI Format Type N1 for RAR /// DCI Format Type N1 for RAR
struct DCIFormatN1_RAR{ struct DCIFormatN1_RAR{
...@@ -134,7 +131,6 @@ struct DCIFormatN1_RAR{ ...@@ -134,7 +131,6 @@ struct DCIFormatN1_RAR{
}; };
typedef struct DCIFormatN1_RAR DCIFormatN1_RAR_t; typedef struct DCIFormatN1_RAR DCIFormatN1_RAR_t;
#define sizeof_DCIFormatN1_RAR_t 23
// DCI Format Type N2 for direct indication, 15 bits // DCI Format Type N2 for direct indication, 15 bits
struct DCIFormatN2_Ind{ struct DCIFormatN2_Ind{
...@@ -147,7 +143,6 @@ struct DCIFormatN2_Ind{ ...@@ -147,7 +143,6 @@ struct DCIFormatN2_Ind{
}; };
typedef struct DCIFormatN2_Ind DCIFormatN2_Ind_t; typedef struct DCIFormatN2_Ind DCIFormatN2_Ind_t;
#define sizeof_DCIFormatN2_Ind_t 15
// DCI Format Type N2 for Paging, 15 bits // DCI Format Type N2 for Paging, 15 bits
struct DCIFormatN2_Pag{ struct DCIFormatN2_Pag{
...@@ -164,9 +159,8 @@ struct DCIFormatN2_Pag{ ...@@ -164,9 +159,8 @@ struct DCIFormatN2_Pag{
}; };
typedef struct DCIFormatN2_Pag DCIFormatN2_Pag_t; typedef struct DCIFormatN2_Pag DCIFormatN2_Pag_t;
#define sizeof_DCIFormatN2_Pag_t 15
typedef union DCI_CONTENT { typedef union DCI_CONTENT {
// //
DCIFormatN0_t DCIN0; DCIFormatN0_t DCIN0;
// //
...@@ -180,4 +174,106 @@ typedef struct DCIFormatN2_Pag DCIFormatN2_Pag_t; ...@@ -180,4 +174,106 @@ typedef struct DCIFormatN2_Pag DCIFormatN2_Pag_t;
// //
DCIFormatN2_Pag_t DCIN2_Pag; DCIFormatN2_Pag_t DCIN2_Pag;
}DCI_CONTENT; }DCI_CONTENT;
\ No newline at end of file
/*Structure for packing*/
struct DCIN0{
/// DCI subframe repetition Number, 2 bits
uint8_t DCIRep:2;
/// New Data Indicator, 1 bits
uint8_t ndi:1;
/// Repetition Number, 3 bits
uint8_t RepNum:3;
/// Redundancy version for HARQ (only use 0 and 2), 1 bits
uint8_t rv:1;
/// Modulation and Coding Scheme, 4 bits
uint8_t mcs:4;
/// Scheduling Delay, 2 bits
uint8_t Scheddly:2;
/// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign:3;
/// Subcarrier indication, 6 bits
uint8_t scind:6;
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type:1;
} __attribute__ ((__packed__));
typedef struct DCIN0 DCIN0_t;
#define sizeof_DCIN0_t 23
struct DCIN1_RAR{
// Reserved 5 bits like payload
uint8_t Reserved:5;
// DCI subframe repetition Number, 2 bits
uint8_t DCIRep:2;
// Repetition Number, 4 bits
uint8_t RepNum:4;
// Modulation and Coding Scheme, 4 bits
uint8_t mcs:4;
// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign:3;
// Scheduling Delay, 3 bits
uint8_t Scheddly:3;
//NPDCCH order indicator (set to 0),1 bits
uint8_t orderIndicator:1;
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type:1;
} __attribute__ ((__packed__));
typedef struct DCIN1_RAR DCIN1_RAR_t;
#define sizeof_DCIN1_RAR_t 23
struct DCIN1{
// DCI subframe repetition Number, 2 bits
uint8_t DCIRep:2;
// HARQ-ACK resource,4 bits
uint8_t HARQackRes:4;
// New Data Indicator,1 bits
uint8_t ndi:1;
// Repetition Number, 4 bits
uint8_t RepNum:4;
// Modulation and Coding Scheme, 4 bits
uint8_t mcs:4;
// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign:3;
// Scheduling Delay, 3 bits
uint8_t Scheddly:3;
//NPDCCH order indicator (set to 0),1 bits
uint8_t orderIndicator:1;
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type:1;
} __attribute__ ((__packed__));
typedef struct DCIN1 DCIN1_t;
#define sizeof_DCIN1_t 23
// DCI Format Type N2 for direct indication, 15 bits
struct DCIN2_Ind{
// Reserved information bits, 6 bits
uint8_t resInfoBits:6;
//Direct indication information, 8 bits
uint8_t directIndInf:8;
//Flag for paging(1)/direct indication(0), set to 0,1 bits
uint8_t type:1;
} __attribute__ ((__packed__));;
typedef struct DCIN2_Ind DCIN2_Ind_t;
#define sizeof_DCIN2_Ind_t 15
// DCI Format Type N2 for Paging, 15 bits
struct DCIN2_Pag{
// Reserved 3 bits
uint8_t DCIRep:3;
// Repetition Number, 4 bits
uint8_t RepNum:4;
// Modulation and Coding Scheme, 4 bits
uint8_t mcs:4;
// Resourse Assignment (RU Assignment), 3 bits
uint8_t ResAssign:3;
//Flag for paging(1)/direct indication(0), set to 1,1 bits
uint8_t type:1;
} __attribute__ ((__packed__));;
typedef struct DCIN2_Pag DCIN2_Pag_t;
#define sizeof_DCIN2_Pag_t 15
\ No newline at end of file
openair1/PHY/LTE_TRANSPORT/dci_tools_nb_iot.c
View file @ 27dd07ea
...@@ -43,30 +43,41 @@ ...@@ -43,30 +43,41 @@
#include "LAYER2/MAC/extern.h" #include "LAYER2/MAC/extern.h"
#include "LAYER2/MAC/defs.h" #include "LAYER2/MAC/defs.h"
#include "PHY/defs_nb_iot.h"
//#define DEBUG_DCI //#define DEBUG_DCI
void NB_add_dci(DCI_PDU_NB *DCI_pdu,void *pdu,rnti_t rnti,unsigned char dci_size_bytes,unsigned char aggregation,unsigned char dci_size_bits,unsigned char dci_fmt)
{
memcpy(&DCI_pdu->dci_alloc[DCI_pdu->Num_dci].dci_pdu[0],pdu,dci_size_bytes);
DCI_pdu->dci_alloc[DCI_pdu->Num_dci].dci_length = dci_size_bits;
DCI_pdu->dci_alloc[DCI_pdu->Num_dci].L = aggregation;
DCI_pdu->dci_alloc[DCI_pdu->Num_dci].rnti = rnti;
DCI_pdu->dci_alloc[DCI_pdu->Num_dci].format = dci_fmt;
DCI_pdu->Num_dci++;
int8_t delta_PUSCH_abs[4] = {-4,-1,1,4}; LOG_D(MAC,"add ue specific dci format %d for rnti %x \n",dci_fmt,rnti);
int8_t delta_PUSCH_acc[4] = {-1,0,1,3}; }
int8_t *delta_PUCCH_lut = delta_PUSCH_acc;
int NB_generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB, int NB_generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB_NB *eNB,
eNB_rxtx_proc_t *proc, eNB_rxtx_proc_NB_t *proc,
DCI_CONTENT *DCI_Content, DCI_CONTENT *DCI_Content,
uint16_t rnti, uint16_t rnti,
DCI_format_NB_t dci_format, DCI_format_NB_t dci_format,
uint8_t UE_id) uint8_t UE_id,
uint8_t aggregation,
uint8_t Num_dci
)
{ {
uint8_t harq_pid;
uint32_t rb_alloc;
uint8_t transmission_mode=eNB->transmission_mode[UE_id];
ANFBmode_t AckNackFBMode = eNB->pucch_config_dedicated[UE_id].tdd_AckNackFeedbackMode;
LTE_eNB_ULSCH_t *ulsch=eNB->ulsch[UE_id]; LTE_eNB_ULSCH_t *ulsch=eNB->ulsch[UE_id];
LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms; NB_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
int subframe = proc->subframe_tx; int subframe = proc->subframe_tx;
void *ULSCH_DCI_NB = NULL;
DCI_PDU_NB *DCI_pdu;
/// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits /// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
uint8_t type; uint8_t type;
...@@ -89,1934 +100,197 @@ int NB_generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB, ...@@ -89,1934 +100,197 @@ int NB_generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB,
if (dci_format == DCIFormatN0) if (dci_format == DCIFormatN0)
{ {
/*HARQ PID Set*/
type = &DCI_Content->DCIN0.type; type = DCI_Content->DCIN0.type;
scind = &DCI_Content->DCIN0.scind; scind = DCI_Content->DCIN0.scind;
ResAssign = &DCI_Content->DCIN0.ResAssign; ResAssign = DCI_Content->DCIN0.ResAssign;
mcs = &DCI_Content->DCIN0.mcs; mcs = DCI_Content->DCIN0.mcs;
ndi = &DCI_Content->DCIN0.ndi; ndi = DCI_Content->DCIN0.ndi;
Scheddly = &DCI_Content->DCIN0.Scheddly; Scheddly = DCI_Content->DCIN0.Scheddly;
RepNum = &DCI_Content->DCIN0.RepNum; RepNum = DCI_Content->DCIN0.RepNum;
rv = &DCI_Content->DCIN0.rv; rv = DCI_Content->DCIN0.rv;
DCIRep = &DCI_Content->DCIN0.DCIRep; DCIRep = DCI_Content->DCIN0.DCIRep;
/*Packed DCI here*/
((DCIN0_t *)ULSCH_DCI_NB)->type =type;
((DCIN0_t *)ULSCH_DCI_NB)->scind =scind;
((DCIN0_t *)ULSCH_DCI_NB)->ResAssign =ResAssign;
((DCIN0_t *)ULSCH_DCI_NB)->Scheddly =Scheddly;
((DCIN0_t *)ULSCH_DCI_NB)->mcs =mcs;
((DCIN0_t *)ULSCH_DCI_NB)->rv =rv;
((DCIN0_t *)ULSCH_DCI_NB)->RepNum =RepNum;
((DCIN0_t *)ULSCH_DCI_NB)->ndi =ndi;
((DCIN0_t *)ULSCH_DCI_NB)->DCIRep =DCIRep;
DCI_pdu->Num_dci = Num_dci;
NB_add_dci(DCI_pdu,ULSCH_DCI_NB,rnti,sizeof(DCIN0_t),aggregation,sizeof_DCIN0_t,DCIFormatN0);
// use this value to configure PHY both harq_processes and resource mapping. // use this value to configure PHY both harq_processes and resource mapping.
return(0); return(0);
} }
else else
{ {
LOG_E(PHY,"generate_eNB_ulsch_params_from_dci, Illegal dci_format %d\n",dci_format); LOG_E(PHY,"generate_eNB_ulsch_params_from_dci, Illegal dci_format %d\n",dci_format);
return(-1); return(-1);
} }
} }
int NB_generate_eNB_dlsch_params_from_dci(int frame, int NB_generate_eNB_dlsch_params_from_dci(int frame,
uint8_t subframe, uint8_t subframe,
void *dci_pdu, DCI_CONTENT *DCI_Content,
uint16_t rnti, uint16_t rnti,
DCI_format_t dci_format, DCI_format_NB_t dci_format,
LTE_eNB_DLSCH_t **dlsch, LTE_eNB_DLSCH_t **dlsch,
LTE_DL_FRAME_PARMS *frame_parms, NB_DL_FRAME_PARMS *frame_parms,
PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, uint8_t aggregation,
uint16_t si_rnti, uint8_t Num_dci
uint16_t ra_rnti, )
uint16_t p_rnti,
uint16_t DL_pmi_single,
uint8_t beamforming_mode)
{ {
uint8_t harq_pid = UINT8_MAX; void *DLSCH_DCI_NB = NULL;
uint32_t rballoc = UINT32_MAX; DCI_PDU_NB *DCI_pdu;
uint32_t RIV_max = 0;
uint8_t NPRB,tbswap,tpmi=0;
LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
uint8_t frame_type=frame_parms->frame_type;
uint8_t vrb_type=0;
uint8_t mcs=0,mcs1=0,mcs2=0;
uint8_t I_mcs = 0;
uint8_t rv=0,rv1=0,rv2=0;
uint8_t rah=0;
uint8_t TPC=0;
uint8_t TB0_active=0,TB1_active=0;
LTE_DL_eNB_HARQ_t *dlsch0_harq=NULL,*dlsch1_harq=NULL;
// printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);
switch (dci_format) {
case format0:
return(-1);
break;
case format1A: // This is DLSCH allocation for control traffic
dlsch[0]->subframe_tx[subframe] = 1;
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_type == TDD) {
vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->codeword=0;
if (vrb_type==LOCALIZED) {
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT6[rballoc];
}
else {
LOG_E(PHY,"Distributed RB allocation not done yet\n");
mac_xface->macphy_exit("exiting");
}
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT6[rballoc];//NPRB;
RIV_max = RIV_max6;
break;
case 25:
if (frame_type == TDD) {
vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
if (vrb_type==LOCALIZED) {
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT25[rballoc];
}
else {
LOG_E(PHY,"Distributed RB allocation not done yet\n");
mac_xface->macphy_exit("exiting");
}
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT25[rballoc];//NPRB;
RIV_max = RIV_max25;
break;
case 50:
if (frame_type == TDD) {
vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
//printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
if (vrb_type==LOCALIZED) {
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT50_0[rballoc];
dlsch0_harq->rb_alloc[1] = localRIV2alloc_LUT50_1[rballoc];
}
else {
LOG_E(PHY,"Distributed RB allocation not done yet\n");
mac_xface->macphy_exit("exiting");
}
dlsch0_harq->vrb_type = vrb_type;
dlsch0_harq->nb_rb = RIV2nb_rb_LUT50[rballoc];//NPRB;
RIV_max = RIV_max50;
break;
case 100:
if (frame_type == TDD) {
vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
TPC = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
mcs = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
TPC = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->vrb_type = vrb_type;
if (vrb_type==LOCALIZED) {
dlsch0_harq->rb_alloc[0] = localRIV2alloc_LUT100_0[rballoc];
dlsch0_harq->rb_alloc[1] = localRIV2alloc_LUT100_1[rballoc];
dlsch0_harq->rb_alloc[2] = localRIV2alloc_LUT100_2[rballoc];
dlsch0_harq->rb_alloc[3] = localRIV2alloc_LUT100_3[rballoc];
}
else {
LOG_E(PHY,"Distributed RB allocation not done yet\n");
mac_xface->macphy_exit("exiting");
}
dlsch0_harq->nb_rb = RIV2nb_rb_LUT100[rballoc];//NPRB;
RIV_max = RIV_max100;
break;
default:
LOG_E(PHY,"Invalid N_RB_D %dL\n", frame_parms->N_RB_DL);
DevParam (frame_parms->N_RB_DL, 0, 0);
break;
}
// harq_pid field is reserved
if ((rnti==si_rnti) || (rnti==ra_rnti) || (rnti==p_rnti)) { //
harq_pid=0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1)+2;
// 36-213 sec.7.1.7.2 p.26
I_mcs = mcs;
} else {
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
if (rballoc>RIV_max) {
LOG_E(PHY,"ERROR: Format 1A: rb_alloc (%x) > RIV_max (%x)\n",rballoc,RIV_max);
return(-1);
}
NPRB = dlsch0_harq->nb_rb;
I_mcs = get_I_TBS(mcs);
}
if (NPRB==0)
return(-1);
//printf("NPRB %d, nb_rb %d, ndi %d\n",NPRB,dlsch0_harq->nb_rb,ndi);
dlsch0_harq->rvidx = rv;
dlsch0_harq->Nl = 1;
//dlsch0_harq->layer_index = 0;
dlsch0_harq->mimo_mode = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
/*
if ((rnti!=si_rnti)&&(rnti!=ra_rnti)&&(rnti!=p_rnti)) { //handle toggling for C-RNTI
if (dlsch0_harq->first_tx == 1) {
LOG_D(PHY,"First TX for TC-RNTI %x, clearing first_tx flag\n",rnti);
dlsch0_harq->first_tx=0;
dlsch0_harq->Ndi = 1;
}
else {
if (ndi == dlsch0_harq->DCINdi)
dlsch0_harq->Ndi = 0;
else
dlsch0_harq->Ndi = 1;
}
dlsch0_harq->DCINdi=ndi;
}
else {
dlsch0_harq->Ndi = 1;
}
*/
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[I_mcs][NPRB-1];
dlsch[0]->current_harq_pid = harq_pid;
dlsch[0]->harq_ids[subframe] = harq_pid;
dlsch[0]->active = 1;
dlsch0 = dlsch[0];
dlsch[0]->rnti = rnti;
dlsch[0]->harq_ids[subframe] = harq_pid;
if (dlsch0_harq->round == 0)
dlsch0_harq->status = ACTIVE;
break;
case format1:
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_TDD_t *)dci_pdu)->ndi,harq_pid);
} else {
mcs = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_FDD_t *)dci_pdu)->ndi,harq_pid);
}
break;
case 50:
if (frame_type == TDD) {
mcs = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
dlsch0_harq->codeword=0;
// printf("DCI: Setting subframe_tx for subframe %d\n",subframe);
dlsch[0]->subframe_tx[subframe] = 1;
conv_rballoc(rah,
rballoc,frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
frame_parms->N_RB_DL);
NPRB = dlsch0_harq->nb_rb;
if (NPRB==0)
return(-1);
dlsch0_harq->rvidx = rv;
dlsch0_harq->Nl = 1;
// dlsch[0]->layer_index = 0;
if (beamforming_mode == 0)
dlsch0_harq->mimo_mode = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
else if (beamforming_mode == 7)
dlsch0_harq->mimo_mode = TM7;
else
LOG_E(PHY,"Invalid beamforming mode %dL\n", beamforming_mode);
dlsch0_harq->dl_power_off = 1;
/*
if (dlsch[0]->harq_processes[harq_pid]->first_tx == 1) {
LOG_D(PHY,"First TX for C-RNTI %x, clearing first_tx flag, shouldn't happen!\n",rnti);
dlsch[0]->harq_processes[harq_pid]->first_tx=0;
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
else {
LOG_D(PHY,"Checking for Toggled Ndi for C-RNTI %x, old value %d, DCINdi %d\n",rnti,dlsch[0]->harq_processes[harq_pid]->DCINdi,ndi);
if (ndi == dlsch[0]->harq_processes[harq_pid]->DCINdi)
dlsch[0]->harq_processes[harq_pid]->Ndi = 0;
else
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
dlsch[0]->harq_processes[harq_pid]->DCINdi=ndi;
*/
dlsch[0]->active = 1;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
// MCS and TBS don't change across HARQ rounds
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][NPRB-1];
}
dlsch[0]->current_harq_pid = harq_pid;
dlsch[0]->harq_ids[subframe] = harq_pid;
dlsch0 = dlsch[0];
dlsch[0]->rnti = rnti;
break;
case format2: // DL Scheduling assignment for MIMO including closed loop spatial multiplexing
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 25:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 50:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 100:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tpmi;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
// note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
TB0_active = 1;
TB1_active = 1;
if ((rv1 == 1) && (mcs1 == 0)) {
TB0_active=0;
}
if ((rv2 == 1) && (mcs2 == 0)) {
TB1_active=0;
}
#ifdef DEBUG_HARQ
printf("RV0 = %d, RV1 = %d. MCS0 = %d, MCS1=%d\n", rv1, rv2, mcs1, mcs2);
#endif
if (TB0_active && TB1_active && tbswap==0) {
dlsch0=dlsch[0];
dlsch1=dlsch[1];
dlsch0->active = 1;
dlsch1->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
dlsch0_harq->status = ACTIVE;
dlsch1_harq->status = ACTIVE;
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
#ifdef DEBUG_HARQ
printf("\n ENB: BOTH ACTIVE\n");
#endif
}
else if (TB0_active && TB1_active && tbswap==1) {
dlsch0=dlsch[0];
dlsch1=dlsch[1];
dlsch0->active = 1;
dlsch1->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
dlsch0_harq->status = ACTIVE;
dlsch1_harq->status = ACTIVE;
dlsch0_harq->codeword=1;
dlsch1_harq->codeword=0;
}
else if (TB0_active && (TB1_active==0)) {
dlsch0=dlsch[0];
dlsch0->active = 1;
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch0_harq->mcs = mcs1;
dlsch0_harq->rvidx = rv1;
dlsch0_harq->status = ACTIVE;
dlsch0_harq->codeword = 0;
dlsch1=NULL;
dlsch1_harq = NULL;
#ifdef DEBUG_HARQ
printf("\n ENB: TB1 is deactivated, retransmit TB0 transmit in TM6\n");
#endif
}
else if ((TB0_active==0) && TB1_active) {
dlsch1=dlsch[1];
dlsch1->active = 1;
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch1_harq->mcs = mcs2;
dlsch1_harq->rvidx = rv2;
dlsch1_harq->status = ACTIVE;
dlsch1_harq->codeword = 0;
dlsch0=NULL;
dlsch0_harq = NULL;
#ifdef DEBUG_HARQ
printf("\n ENB: TB0 is deactivated, retransmit TB1 transmit in TM6\n");
#endif
}
if (dlsch0 != NULL){
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
}
if (dlsch1_harq != NULL){
dlsch1->current_harq_pid = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
}
if (dlsch0 != NULL ){
conv_rballoc(rah,
rballoc,
frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch0_harq->nb_rb = conv_nprb(rah, rballoc, frame_parms->N_RB_DL);
if (dlsch1 != NULL){
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
}
} else if ((dlsch0 == NULL ) && (dlsch1 != NULL )){
conv_rballoc(rah,
rballoc,
frame_parms->N_RB_DL,
dlsch1_harq->rb_alloc);
dlsch1_harq->nb_rb = conv_nprb(rah, rballoc, frame_parms->N_RB_DL);
}
/*if (dlsch0_harq->nb_rb == 0)
return(-1);*/
// assume both TBs are active
if (dlsch0_harq != NULL)
dlsch0_harq->Nl = 1;
if (dlsch1_harq != NULL)
dlsch1_harq->Nl = 1;
// check if either TB is disabled (see 36-213 V11.3 Section )
if (frame_parms->nb_antenna_ports_eNB == 2) {
if ((dlsch0 != NULL) && (dlsch1 != NULL)) { //two CW active
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
switch (tpmi) {
case 0:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,1);
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0,1);
break;
case 1:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1);
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1);
break;
case 2: // PUSCH precoding
dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch0_harq->pmi_alloc = DL_pmi_single;
dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
default:
break;
}
} else if ((dlsch0 != NULL) && (dlsch1 == NULL)) { // only CW 0 active
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->TBS= TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
switch (tpmi) {
case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,0);
break;
case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,0);
break;
case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2,0);
break;
case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3,0);
break;
case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
}
} else if ((dlsch0 == NULL) && (dlsch1 != NULL)) {
dlsch1_harq->dl_power_off = 1;
dlsch1_harq->TBS= TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
switch (tpmi) {
case 0 :
dlsch1_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0,0);
break;
case 2:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,1,0);
break;
case 3:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,2,0);
break;
case 4:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,3,0);
break;
case 5:
dlsch1_harq->mimo_mode = PUSCH_PRECODING0;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch1_harq->mimo_mode = PUSCH_PRECODING1;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
}
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
// fill in later
}
// reset HARQ process if this is the first transmission
/* if (dlsch0_harq->round == 0)
dlsch0_harq->status = ACTIVE;
if (dlsch1_harq->round == 0)
dlsch1_harq->status = ACTIVE;*/
if (dlsch0_harq != NULL)
dlsch0->rnti = rnti;
if (dlsch1 != NULL)
dlsch1->rnti = rnti;
break;
case format2A:
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 25:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 50:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
case 100:
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
} else {
mcs1 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
if (frame_type == TDD) {
mcs1 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
} else {
mcs1 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
tbswap = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
tpmi = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
}
} else {
LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",subframe,rnti,frame_parms->nb_antenna_ports_eNB);
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
// Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
// note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
// This must be set as in TM4, does not work properly now.
if (tbswap == 0) {
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
} else {
dlsch0 = dlsch[1];
dlsch1 = dlsch[0];
}
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
dlsch1->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
conv_rballoc(rah,
rballoc,
frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
frame_parms->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
if (dlsch0_harq->nb_rb == 0)
return(-1);
dlsch0_harq->mcs = mcs1; //N1 start
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// assume both TBs are active /// type = 0 => DCI Format N0, type = 1 => DCI Format N1, 1 bits
dlsch0_harq->Nl = 1; uint8_t type;
dlsch1_harq->Nl = 1; //NPDCCH order indicator (set to 0),1 bits
dlsch0->active = 1; uint8_t orderIndicator;
dlsch1->active = 1; // Scheduling Delay, 3 bits
uint8_t Scheddly;
// Resourse Assignment (RU Assignment), 3 bits
// check if either TB is disabled (see 36-213 V11.3 Section ) uint8_t ResAssign;
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) { // Modulation and Coding Scheme, 4 bits
dlsch0->active = 0; uint8_t mcs;
} // Repetition Number, 4 bits
uint8_t RepNum;
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) { // Reserved 5 bits
dlsch1->active = 0; uint8_t Reserved;
} // DCI subframe repetition Number, 2 bits
uint8_t DCIRep;
// dlsch0_harq->dl_power_off = 0; // New Data Indicator,1 bits
// dlsch1_harq->dl_power_off = 0; uint8_t ndi;
// HARQ-ACK resource,4 bits
uint8_t HARQackRes;
if (frame_parms->nb_antenna_ports_eNB == 2) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
if ((dlsch0->active==1) && (dlsch1->active==1)) {
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
} else {
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) { // 4 antenna case
if ((dlsch0->active==1) && (dlsch1->active==1)) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case 1: // one-layers on TB 0, two on TB 1
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->Nl = 2;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case 2: // two-layers on TB 0, two on TB 1
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->Nl = 2;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
if (frame_parms->N_RB_DL <= 56) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
} else {
LOG_E(PHY,"Add implementation of Table 7.1.7.2.2-1 for two-layer TBS conversion with N_RB_DL > 56\n");
}
break;
case 3: //
LOG_E(PHY,"Illegal value (3) for TPMI in Format 2A DCI\n");
break;
}
} else if (dlsch0->active == 1) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
break;
case 1: // two-layers on TB 0
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch0_harq->Nl = 2;
dlsch0_harq->dl_power_off = 1;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
break;
case 2: // two-layers on TB 0, two on TB 1
case 3: //
LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
break;
}
} else if (dlsch1->active == 1) {
switch (tpmi) {
case 0: // one layer per transport block
dlsch0_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->mimo_mode = ALAMOUTI;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
break;
case 1: // two-layers on TB 0
dlsch1_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->Nl = 2;
dlsch1_harq->dl_power_off = 1;
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
break;
case 2: // two-layers on TB 0, two on TB 1
case 3: //
LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
break;
}
}
} else {
LOG_E(PHY,"Illegal number of antennas for eNB %d\n",frame_parms->nb_antenna_ports_eNB);
}
// reset HARQ process if this is the first transmission
if ((dlsch0->active==1) && (dlsch0_harq->round == 0))
dlsch0_harq->status = ACTIVE;
if ((dlsch1->active==1) && (dlsch1_harq->round == 0))
dlsch1_harq->status = ACTIVE;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
// printf("eNB: Format 2A TBS0 %d, TBS1 %d\n",dlsch0_harq->TBS,dlsch1_harq->TBS);
break;
case format2B:
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2B_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
dlsch1->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah,
rballoc,
frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
frame_parms->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0))
dlsch0_harq->status = DISABLED;
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0))
dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
dlsch0_harq->mcs = mcs1;
if (dlsch0_harq->nb_rb > 0) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case format2C:
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2C_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2C_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
dlsch1->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah,
rballoc,
frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc,
frame_parms->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
if (dlsch0_harq->nb_rb == 0)
return(-1);
dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
dlsch0->active = 0;
}
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
dlsch1->active = 0;
}
if ((dlsch0_harq->round == 0) && (dlsch0->active == 1) ) {
dlsch0_harq->status = ACTIVE;
dlsch0_harq->mcs = mcs1;
}
if ((dlsch1_harq->round == 0) && (dlsch1->active == 1) ) {
dlsch1_harq->status = ACTIVE;
dlsch1_harq->mcs = mcs2;
}
// check TPMI information to compute TBS //N2 start
if (frame_parms->nb_antenna_ports_eNB == 2) {
if (dlsch1->active == 1) { // both TBs are active
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
}
} else if (frame_parms->nb_antenna_ports_eNB == 4) {
} //Direct indication information, 8 bits
uint8_t directIndInf;
// Reserved information bits, 6 bits
uint8_t resInfoBits;
dlsch0->rnti = rnti; // printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1; switch (dci_format) {
dlsch1_harq->dl_power_off = 1;
case DCIFormatN0:
return(-1);
break; break;
case format2D: case DCIFormatN1_RAR: // This is DLSCH allocation for control traffic
switch (frame_parms->N_RB_DL) {
case 6:
if (frame_type == TDD) {
mcs1 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv1 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 25:
if (frame_type == TDD) {
mcs1 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_5MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_5MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_5MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 50:
if (frame_type == TDD) {
mcs1 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_10MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_10MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_10MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
case 100:
if (frame_type == TDD) {
mcs1 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_20MHz_TDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_20MHz_TDD_t *)dci_pdu)->harq_pid;
} else {
mcs1 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->mcs1;
mcs2 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->mcs2;
rballoc = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rballoc;
rah = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rah;
rv1 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rv1;
rv2 = ((DCI2D_20MHz_FDD_t *)dci_pdu)->rv2;
harq_pid = ((DCI2D_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
}
type = DCI_Content->DCIN1_RAR.type;
orderIndicator = DCI_Content->DCIN1_RAR.orderIndicator;
Scheddly = DCI_Content->DCIN1_RAR.Scheddly;
ResAssign = DCI_Content->DCIN1_RAR.ResAssign;
mcs = DCI_Content->DCIN1_RAR.mcs;
RepNum = DCI_Content->DCIN1_RAR.RepNum;
Reserved = DCI_Content->DCIN1_RAR.Reserved;
DCIRep = DCI_Content->DCIN1_RAR.DCIRep;
/*Packed DCI here*/
((DCIN1_RAR_t *)DLSCH_DCI_NB)->type =type;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->orderIndicator =orderIndicator;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->Scheddly =Scheddly;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->ResAssign =ResAssign;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->mcs =mcs;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->RepNum =RepNum;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->DCIRep =DCIRep;
((DCIN1_RAR_t *)DLSCH_DCI_NB)->Reserved =Reserved;
if (harq_pid>=8) { DCI_pdu->Num_dci = Num_dci;
LOG_E(PHY,"ERROR: Format 2_2A: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
NB_add_dci(DCI_pdu,DLSCH_DCI_NB,rnti,sizeof(DCIN1_RAR_t),aggregation,sizeof_DCIN1_RAR_t,DCIFormatN1_RAR);
dlsch0 = dlsch[0]; // use this value to configure PHY both harq_processes and resource mapping.
dlsch1 = dlsch[1];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
dlsch1->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
case DCIFormatN1: // for user data
dlsch0_harq = dlsch0->harq_processes[harq_pid]; type = DCI_Content->DCIN1.type;
dlsch1_harq = dlsch1->harq_processes[harq_pid]; orderIndicator = DCI_Content->DCIN1.orderIndicator;
Scheddly = DCI_Content->DCIN1.Scheddly;
ResAssign = DCI_Content->DCIN1.ResAssign;
mcs = DCI_Content->DCIN1.mcs;
RepNum = DCI_Content->DCIN1.RepNum;
ndi = DCI_Content->DCIN1.ndi;
HARQackRes = DCI_Content->DCIN1.HARQackRes;
DCIRep = DCI_Content->DCIN1.DCIRep;
/*Packed DCI here*/
((DCIN1_t *)DLSCH_DCI_NB)->type =type;
((DCIN1_t *)DLSCH_DCI_NB)->orderIndicator =orderIndicator;
((DCIN1_t *)DLSCH_DCI_NB)->Scheddly =Scheddly;
((DCIN1_t *)DLSCH_DCI_NB)->ResAssign =ResAssign;
((DCIN1_t *)DLSCH_DCI_NB)->mcs =mcs;
((DCIN1_t *)DLSCH_DCI_NB)->RepNum =RepNum;
((DCIN1_t *)DLSCH_DCI_NB)->ndi =ndi;
((DCIN1_t *)DLSCH_DCI_NB)->HARQackRes =HARQackRes;
((DCIN1_t *)DLSCH_DCI_NB)->DCIRep =DCIRep;
// Needs to be checked DCI_pdu->Num_dci = Num_dci;
dlsch0_harq->codeword=0;
dlsch1_harq->codeword=1;
conv_rballoc(rah, NB_add_dci(DCI_pdu,DLSCH_DCI_NB,rnti,sizeof(DCIN1_t),aggregation,sizeof_DCIN1_t,DCIFormatN1);
rballoc,
frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(rah, // use this value to configure PHY both harq_processes and resource mapping.
rballoc,
frame_parms->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
dlsch0_harq->mcs = mcs1; case DCIFormatN2_Ind:
dlsch1_harq->mcs = mcs2;
dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26) type = DCI_Content->DCIN2_Ind.type;
directIndInf = DCI_Content->DCIN2_Ind.directIndInf;
resInfoBits = DCI_Content->DCIN2_Ind.resInfoBits;
/*Packed DCI here*/
((DCIN2_Ind_t *)DLSCH_DCI_NB)->type =type;
((DCIN2_Ind_t *)DLSCH_DCI_NB)->directIndInf =directIndInf;
((DCIN2_Ind_t *)DLSCH_DCI_NB)->resInfoBits =resInfoBits;
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) DCI_pdu->Num_dci = Num_dci;
dlsch0_harq->status = DISABLED;
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) NB_add_dci(DCI_pdu,DLSCH_DCI_NB,rnti,sizeof(DCIN2_Ind_t),aggregation,sizeof_DCIN2_Ind_t,DCIFormatN2_Ind);
dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1; // use this value to configure PHY both harq_processes and resource mapping.
case DCIFormatN2_Pag:
if (dlsch0_harq->round == 0) { type = DCI_Content->DCIN2_Pag.type;
dlsch0_harq->status = ACTIVE; ResAssign = DCI_Content->DCIN2_Pag.ResAssign;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid); mcs = DCI_Content->DCIN2_Pag.mcs;
} RepNum = DCI_Content->DCIN2_Pag.RepNum;
DCIRep = DCI_Content->DCIN2_Pag.DCIRep;
dlsch0_harq->mcs = mcs1; /*Packed DCI here*/
((DCIN2_Pag_t *)DLSCH_DCI_NB)->type =type;
((DCIN2_Pag_t *)DLSCH_DCI_NB)->ResAssign =ResAssign;
((DCIN2_Pag_t *)DLSCH_DCI_NB)->mcs =mcs;
((DCIN2_Pag_t *)DLSCH_DCI_NB)->RepNum =RepNum;
((DCIN2_Pag_t *)DLSCH_DCI_NB)->DCIRep =DCIRep;
if (dlsch0_harq->nb_rb > 0) { DCI_pdu->Num_dci = Num_dci;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1; NB_add_dci(DCI_pdu,DLSCH_DCI_NB,rnti,sizeof(DCIN2_Pag_t),aggregation,sizeof_DCIN2_Pag_t,DCIFormatN2_Pag);
dlsch0->rnti = rnti; // use this value to configure PHY both harq_processes and resource mapping.
dlsch1->rnti = rnti;
dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1;
break;
case format1E_2A_M10PRB:
harq_pid = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
if (harq_pid>=8) {
LOG_E(PHY,"ERROR: Format 1E_2A_M10PRB: harq_pid=%d >= 8\n", harq_pid);
return(-1);
}
/*
tbswap = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
if (tbswap == 0) {
dlsch0 = dlsch[0];
dlsch1 = dlsch[1];
}
else{
dlsch0 = dlsch[1];
dlsch1 = dlsch[0];
}
*/
dlsch0 = dlsch[0];
dlsch0->subframe_tx[subframe] = 1;
dlsch0->current_harq_pid = harq_pid;
//dlsch1->current_harq_pid = harq_pid;
dlsch0->harq_ids[subframe] = harq_pid;
//dlsch1->harq_ids[subframe] = harq_pid;
// printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);
dlsch0_harq = dlsch0->harq_processes[harq_pid];
// Needs to be checked
dlsch0_harq->codeword=0;
conv_rballoc(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
dlsch0_harq->rb_alloc);
//dlsch1->rb_alloc[0] = dlsch0->rb_alloc[0];
dlsch0_harq->nb_rb = conv_nprb(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
frame_parms->N_RB_DL);
//dlsch1->nb_rb = dlsch0->nb_rb;
dlsch0_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
//dlsch1_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
dlsch0_harq->rvidx = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv;
//dlsch1_harq->rvidx = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;
// check if either TB is disabled (see 36-213 V8.6 p. 26) --> only for format 2 and 2A
//if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0))
// dlsch0_harq->status = DISABLED;
//if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0))
// dlsch1_harq->status = DISABLED;
dlsch0_harq->Nl = 1;
//dlsch0->layer_index = tbswap;
//dlsch1->layer_index = 1-tbswap;
// Fix this
tpmi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;
switch (tpmi) {
case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0, 0);
break;
case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1, 0);
break;
case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2, 0);
break;
case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3, 0);
break;
case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
dlsch0_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
return(-1);
break;
}
// printf("Set pmi %x (tpmi %d)\n",dlsch0->pmi_alloc,tpmi);
if (frame_parms->mode1_flag == 1)
dlsch0_harq->mimo_mode = SISO;
// dlsch0_harq->Ndi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
dlsch0_harq->mcs = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
if (dlsch0_harq->nb_rb > 0) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
} else {
dlsch0_harq->TBS = 0;
}
dlsch0->active = 1;
dlsch0->rnti = rnti;
//dlsch1->rnti = rnti;
// dlsch0->dl_power_off = 1;
dlsch0_harq->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
//dlsch1->dl_power_off = 1;
break;
default: default:
LOG_E(PHY,"Unknown DCI format\n"); LOG_E(PHY,"Unknown DCI format\n");
...@@ -2025,57 +299,10 @@ int NB_generate_eNB_dlsch_params_from_dci(int frame, ...@@ -2025,57 +299,10 @@ int NB_generate_eNB_dlsch_params_from_dci(int frame,
} }
if (dlsch0_harq) {
dlsch0_harq->frame = frame;
dlsch0_harq->subframe = subframe;
}
if (dlsch1_harq) {
dlsch1_harq->frame = frame;
dlsch1_harq->subframe = subframe;
}
#ifdef DEBUG_DCI
if (dlsch0) {
printf("dlsch0 eNB: dlsch0 %p\n",dlsch0);
printf("dlsch0 eNB: rnti %x\n",dlsch0->rnti);
printf("dlsch0 eNB: NBRB %d\n",dlsch0_harq->nb_rb);
printf("dlsch0 eNB: rballoc %x\n",dlsch0_harq->rb_alloc[0]);
printf("dlsch0 eNB: harq_pid %d\n",harq_pid);
printf("dlsch0 eNB: round %d\n",dlsch0_harq->round);
printf("dlsch0 eNB: rvidx %d\n",dlsch0_harq->rvidx);
printf("dlsch0 eNB: TBS %d (NPRB %d)\n",dlsch0_harq->TBS,NPRB);
printf("dlsch0 eNB: mcs %d\n",dlsch0_harq->mcs);
printf("dlsch0 eNB: tpmi %d\n",tpmi);
printf("dlsch0 eNB: mimo_mode %d\n",dlsch0_harq->mimo_mode);
}
if (dlsch1) {
printf("dlsch1 eNB: dlsch1 %p\n",dlsch1);
printf("dlsch1 eNB: rnti %x\n",dlsch1->rnti);
printf("dlsch1 eNB: NBRB %d\n",dlsch1_harq->nb_rb);
printf("dlsch1 eNB: rballoc %x\n",dlsch1_harq->rb_alloc[0]);
printf("dlsch1 eNB: harq_pid %d\n",harq_pid);
printf("dlsch1 eNB: round %d\n",dlsch1_harq->round);
printf("dlsch1 eNB: rvidx %d\n",dlsch1_harq->rvidx);
printf("dlsch1 eNB: TBS %d (NPRB %d)\n",dlsch1_harq->TBS,NPRB);
printf("dlsch1 eNB: mcs %d\n",dlsch1_harq->mcs);
printf("dlsch1 eNB: tpmi %d\n",tpmi);
printf("dlsch1 eNB: mimo_mode %d\n",dlsch1_harq->mimo_mode);
}
#endif
// compute DL power control parameters // compute DL power control parameters
if (dlsch0 != NULL){
computeRhoA_eNB(pdsch_config_dedicated, dlsch[0],dlsch0_harq->dl_power_off, frame_parms->nb_antenna_ports_eNB);
computeRhoB_eNB(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antenna_ports_eNB,dlsch[0],dlsch0_harq->dl_power_off);
}
if (dlsch1 != NULL){
computeRhoA_eNB(pdsch_config_dedicated, dlsch[1],dlsch1_harq->dl_power_off, frame_parms->nb_antenna_ports_eNB);
computeRhoB_eNB(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antenna_ports_eNB,dlsch[1],dlsch1_harq->dl_power_off);
}
return(0); return(0);
......
openair1/PHY/LTE_TRANSPORT/defs_nb_iot.h
View file @ 27dd07ea
...@@ -50,11 +50,17 @@ typedef struct { ...@@ -50,11 +50,17 @@ typedef struct {
/// rnti /// rnti
rnti_t rnti; rnti_t rnti;
/// Format /// Format
DCI_format_t format; DCI_format_NB_t format;
/// DCI pdu /// DCI pdu
uint8_t dci_pdu[8]; uint8_t dci_pdu[8];
} DCI_ALLOC_NB_t; } DCI_ALLOC_NB_t;
typedef struct {
//delete the count for the DCI numbers,NUM_DCI_MAX should set to 1
uint32_t num_npdcch_symbols;
uint8_t Num_dci;
DCI_ALLOC_NB_t dci_alloc[2] ;
} DCI_PDU_NB;
/**@}*/ /**@}*/
#endif #endif
openair1/PHY/LTE_TRANSPORT/proto_nb_iot.h 0 → 100644
View file @ 27dd07ea
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/LTE_TRANSPORT/proto.h
* \brief Function prototypes for PHY physical/transport channel processing and generation V8.6 2009-03
* \author R. Knopp, F. Kaltenberger
* \date 2011
* \version 0.1
* \company Eurecom
* \email: knopp@eurecom.fr
* \note
* \warning
*/
#ifndef __LTE_TRANSPORT_PROTO_NB_IOT__H__
#define __LTE_TRANSPORT_PROTO_NB_IOT__H__
#include "PHY/defs_nb_iot.h"
#include <math.h>
// Functions below implement 36-211 and 36-212
/*Function to pack the DCI*/
void NB_add_dci(DCI_PDU_NB *DCI_pdu,void *pdu,rnti_t rnti,unsigned char dci_size_bytes,unsigned char aggregation,unsigned char dci_size_bits,unsigned char dci_fmt);
/*Use the UL DCI Information to configure PHY and also Packed*/
int NB_generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB_NB *eNB,
eNB_rxtx_proc_NB_t *proc,
DCI_CONTENT *DCI_Content,
uint16_t rnti,
DCI_format_NB_t dci_format,
uint8_t UE_id,
uint8_t aggregation,
uint8_t Num_dci
);
/*Use the DL DCI Information to configure PHY and also Packed*/
int NB_generate_eNB_dlsch_params_from_dci(int frame,
uint8_t subframe,
DCI_CONTENT *DCI_Content,
uint16_t rnti,
DCI_format_NB_t dci_format,
LTE_eNB_DLSCH_t **dlsch,
NB_DL_FRAME_PARMS *frame_parms,
uint8_t aggregation,
uint8_t Num_dci
);
#endif
openair1/PHY/defs_nb_iot.h
View file @ 27dd07ea
...@@ -314,6 +314,7 @@ typedef struct PHY_VARS_eNB_NB_s { ...@@ -314,6 +314,7 @@ typedef struct PHY_VARS_eNB_NB_s {
#include "PHY/LTE_REFSIG/defs.h" #include "PHY/LTE_REFSIG/defs.h"
#include "PHY/MODULATION/defs.h" #include "PHY/MODULATION/defs.h"
#include "PHY/LTE_TRANSPORT/proto.h" #include "PHY/LTE_TRANSPORT/proto.h"
#include "PHY/LTE_TRANSPORT/proto_nb_iot.h"
#include "PHY/LTE_ESTIMATION/defs.h" #include "PHY/LTE_ESTIMATION/defs.h"
#include "SIMULATION/ETH_TRANSPORT/defs.h" #include "SIMULATION/ETH_TRANSPORT/defs.h"
......
openair1/SCHED/phy_procedures_lte_eNb_nb_iot.c
View file @ 27dd07ea
...@@ -77,27 +77,6 @@ ...@@ -77,27 +77,6 @@
#define PUCCH 1 #define PUCCH 1
void exit_fun(const char* s);
extern int exit_openair;
struct timespec start_fh, start_fh_prev;
int start_fh_sf, start_fh_prev_sf;
// Fix per CC openair rf/if device update
// extern openair0_device openair0;
unsigned char dlsch_input_buffer[2700] __attribute__ ((aligned(32)));
int eNB_sync_buffer0[640*6] __attribute__ ((aligned(32)));
int eNB_sync_buffer1[640*6] __attribute__ ((aligned(32)));
int *eNB_sync_buffer[2] = {eNB_sync_buffer0, eNB_sync_buffer1};
extern uint16_t hundred_times_log10_NPRB[100];
unsigned int max_peak_val;
int max_sync_pos;
int harq_pid_updated[NUMBER_OF_UE_MAX][8] = {{0}};
int harq_pid_round[NUMBER_OF_UE_MAX][8] = {{0}};
//DCI_ALLOC_t dci_alloc[8]; //DCI_ALLOC_t dci_alloc[8];
#ifdef EMOS #ifdef EMOS
...@@ -115,8 +94,6 @@ extern int rx_sig_fifo; ...@@ -115,8 +94,6 @@ extern int rx_sig_fifo;
#endif #endif
void NB_phy_procedures_eNB_uespec_RX(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,const relaying_type_t r_type) void NB_phy_procedures_eNB_uespec_RX(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,const relaying_type_t r_type)
{ {
//RX processing for ue-specific resources (i //RX processing for ue-specific resources (i
...@@ -708,7 +685,7 @@ void NB_generate_eNB_dlsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t * proc,Sched ...@@ -708,7 +685,7 @@ void NB_generate_eNB_dlsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t * proc,Sched
// configure dlsch parameters and CCE index // configure dlsch parameters and CCE index
LOG_D(PHY,"Generating dlsch params for RA_RNTI\n"); LOG_D(PHY,"Generating dlsch params for RA_RNTI\n");
NB_generate_eNB_dlsch_params_from_dci(); //NB_generate_eNB_dlsch_params_from_dci();
//eNB->dlsch_ra->nCCE[subframe] = dci_alloc->firstCCE; //eNB->dlsch_ra->nCCE[subframe] = dci_alloc->firstCCE;
/*Log for common DCI*/ /*Log for common DCI*/
...@@ -718,7 +695,7 @@ void NB_generate_eNB_dlsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t * proc,Sched ...@@ -718,7 +695,7 @@ void NB_generate_eNB_dlsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t * proc,Sched
if (UE_id>=0) if (UE_id>=0)
{ {
LOG_D(PHY,"Generating dlsch params for RNTI %x\n",Sched_Rsp->rntiP); LOG_D(PHY,"Generating dlsch params for RNTI %x\n",Sched_Rsp->rntiP);
NB_generate_eNB_dlsch_params_from_dci(); //NB_generate_eNB_dlsch_params_from_dci();
/*Log for remaining DCI*/ /*Log for remaining DCI*/
...@@ -741,7 +718,7 @@ void NB_generate_eNB_ulsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,Sched_ ...@@ -741,7 +718,7 @@ void NB_generate_eNB_ulsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,Sched_
/*Log for generate ULSCH DCI*/ /*Log for generate ULSCH DCI*/
NB_generate_eNB_ulsch_params_from_dci(); //NB_generate_eNB_ulsch_params_from_dci();
//LOG for ULSCH DCI Resource allocation //LOG for ULSCH DCI Resource allocation
......
openair2/LAYER2/MAC/defs_nb_iot.h
View file @ 27dd07ea
...@@ -415,11 +415,6 @@ typedef struct { ...@@ -415,11 +415,6 @@ typedef struct {
uint8_t R:2; uint8_t R:2;
} __attribute__((__packed__))POWER_HEADROOM_CMD_NB; } __attribute__((__packed__))POWER_HEADROOM_CMD_NB;
typedef struct {
//delete the count for the DCI numbers,NUM_DCI_MAX should set to 1
uint32_t num_npdcch_symbols;
DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ;
} DCI_PDU_NB;
typedef struct { typedef struct {
uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ; uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))BCCH_PDU_NB; } __attribute__((__packed__))BCCH_PDU_NB;
......
openair2/PHY_INTERFACE/IF_Module_nb_iot.h
View file @ 27dd07ea
...@@ -81,6 +81,8 @@ typedef struct{ ...@@ -81,6 +81,8 @@ typedef struct{
/*DCI start*/ /*DCI start*/
// Format of DCI // Format of DCI
uint8_t aggregation;
uint8_t Num_dci;
DCI_format_NB_t DCI_Format; DCI_format_NB_t DCI_Format;
// Content of DCI // Content of DCI
DCI_CONTENT *DCI_Content; DCI_CONTENT *DCI_Content;
......
record.txt
View file @ 27dd07ea
...@@ -73,7 +73,10 @@ Comment: merge with RRC branch, start the TX part implementation ...@@ -73,7 +73,10 @@ Comment: merge with RRC branch, start the TX part implementation
Modified: openair2/LAYER2/MAC/phy_procedures_lte_eNB_nb_iot.c Modified: openair2/LAYER2/MAC/phy_procedures_lte_eNB_nb_iot.c
Comment: Complete the TX part, add the NB_generate_eNB_dlsch_params and NB_generate_eNB_ulsch_params Comment: Complete the TX part, add the NB_generate_eNB_dlsch_params and NB_generate_eNB_ulsch_params
Since original OAI packed the DCI in MAC, and unpack at PHY to apply the physical layer configuration. Since original OAI packed the DCI in MAC, and unpack at PHY to apply the physical layer configuration.
so we'll apply the configuration and pack the DCI at the same time. so we'll apply the configuration and pack the DCI at the same time.
5/31
Comment: Complete the dci_tools the part configuring the PHY and do the pack of dci at the same times.
Add DCI packed format in dci_nb_iot.h
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