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wangjie
OpenXG-RAN
Commits
44d1eb80
Commit
44d1eb80
authored
Apr 25, 2018
by
Robert Schmidt
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preprocessor reset: avoid unnecessary iterations
parent
5ceba4a2
Changes
1
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1 changed file
with
79 additions
and
81 deletions
+79
-81
openair2/LAYER2/MAC/pre_processor.c
openair2/LAYER2/MAC/pre_processor.c
+79
-81
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openair2/LAYER2/MAC/pre_processor.c
View file @
44d1eb80
...
@@ -1446,14 +1446,6 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
...
@@ -1446,14 +1446,6 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
if
(
!
ue_dl_slice_membership
(
module_idP
,
UE_id
,
slice_idx
))
if
(
!
ue_dl_slice_membership
(
module_idP
,
UE_id
,
slice_idx
))
continue
;
continue
;
vrb_map
=
RC
.
mac
[
module_idP
]
->
common_channels
[
CC_id
].
vrb_map
;
N_RB_DL
=
to_prb
(
RC
.
mac
[
module_idP
]
->
common_channels
[
CC_id
].
mib
->
message
.
dl_Bandwidth
);
#ifdef SF0_LIMIT
sf0_lower
=
-
1
;
sf0_upper
=
-
1
;
#endif
LOG_D
(
MAC
,
"Running preprocessor for UE %d (%x)
\n
"
,
UE_id
,
rnti
);
LOG_D
(
MAC
,
"Running preprocessor for UE %d (%x)
\n
"
,
UE_id
,
rnti
);
// initialize harq_pid and round
// initialize harq_pid and round
if
(
ue_sched_ctl
->
ta_timer
)
if
(
ue_sched_ctl
->
ta_timer
)
...
@@ -1522,35 +1514,13 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
...
@@ -1522,35 +1514,13 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
ue_sched_ctl
->
pre_nb_available_rbs
[
CC_id
]
=
0
;
ue_sched_ctl
->
pre_nb_available_rbs
[
CC_id
]
=
0
;
ue_sched_ctl
->
dl_pow_off
[
CC_id
]
=
2
;
ue_sched_ctl
->
dl_pow_off
[
CC_id
]
=
2
;
switch
(
N_RB_DL
)
{
for
(
i
=
0
;
i
<
N_RBG
[
CC_id
];
i
++
)
{
case
6
:
ue_sched_ctl
->
rballoc_sub_UE
[
CC_id
][
i
]
=
0
;
RBGsize
=
1
;
}
RBGsize_last
=
1
;
break
;
case
15
:
RBGsize
=
2
;
RBGsize_last
=
1
;
break
;
case
25
:
RBGsize
=
2
;
RBGsize_last
=
1
;
break
;
case
50
:
RBGsize
=
3
;
RBGsize_last
=
2
;
break
;
case
75
:
RBGsize
=
4
;
RBGsize_last
=
3
;
break
;
case
100
:
RBGsize
=
4
;
RBGsize_last
=
4
;
break
;
default:
AssertFatal
(
1
==
0
,
"unsupported RBs (%d)
\n
"
,
N_RB_DL
);
}
}
N_RB_DL
=
to_prb
(
RC
.
mac
[
module_idP
]
->
common_channels
[
CC_id
].
mib
->
message
.
dl_Bandwidth
);
#ifdef SF0_LIMIT
#ifdef SF0_LIMIT
switch
(
N_RBG
[
CC_id
])
{
switch
(
N_RBG
[
CC_id
])
{
case
6
:
case
6
:
...
@@ -1578,13 +1548,42 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
...
@@ -1578,13 +1548,42 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
}
}
#endif
#endif
switch
(
N_RB_DL
)
{
case
6
:
RBGsize
=
1
;
RBGsize_last
=
1
;
break
;
case
15
:
RBGsize
=
2
;
RBGsize_last
=
1
;
break
;
case
25
:
RBGsize
=
2
;
RBGsize_last
=
1
;
break
;
case
50
:
RBGsize
=
3
;
RBGsize_last
=
2
;
break
;
case
75
:
RBGsize
=
4
;
RBGsize_last
=
3
;
break
;
case
100
:
RBGsize
=
4
;
RBGsize_last
=
4
;
break
;
default:
AssertFatal
(
1
==
0
,
"unsupported RBs (%d)
\n
"
,
N_RB_DL
);
}
vrb_map
=
RC
.
mac
[
module_idP
]
->
common_channels
[
CC_id
].
vrb_map
;
// Initialize Subbands according to VRB map
// Initialize Subbands according to VRB map
for
(
i
=
0
;
i
<
N_RBG
[
CC_id
];
i
++
)
{
for
(
i
=
0
;
i
<
N_RBG
[
CC_id
];
i
++
)
{
int
rb_size
=
i
==
N_RBG
[
CC_id
]
-
1
?
RBGsize_last
:
RBGsize
;
int
rb_size
=
i
==
N_RBG
[
CC_id
]
-
1
?
RBGsize_last
:
RBGsize
;
ue_sched_ctl
->
rballoc_sub_UE
[
CC_id
][
i
]
=
0
;
rballoc_sub
[
CC_id
][
i
]
=
0
;
rballoc_sub
[
CC_id
][
i
]
=
0
;
#ifdef SF0_LIMIT
#ifdef SF0_LIMIT
// for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors)
// for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors)
/* TODO: make it proper - allocate those RBs, do not "protect" them, but
/* TODO: make it proper - allocate those RBs, do not "protect" them, but
...
@@ -1608,7 +1607,6 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
...
@@ -1608,7 +1607,6 @@ dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
MIMO_mode_indicator
[
CC_id
][
i
]
=
2
;
MIMO_mode_indicator
[
CC_id
][
i
]
=
2
;
}
}
}
}
}
}
}
...
...
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