Create separate phytest UL preprocessor

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c

@@ -427,3 +427,95 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,
 	dci_pdu_rel15->rv);
 
 }
+
+void nr_ul_preprocessor_phytest(module_id_t module_id,
+                                frame_t frame,
+                                sub_frame_t slot,
+                                int num_slots_per_tdd,
+                                uint64_t ulsch_in_slot_bitmap) {
+  gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
+  NR_COMMON_channels_t *cc = nr_mac->common_channels;
+  NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+  const int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
+  NR_UE_info_t *UE_info = &nr_mac->UE_info;
+
+  AssertFatal(UE_info->num_UEs <= 1,
+              "%s() cannot handle more than one UE, but found %d\n",
+              __func__,
+              UE_info->num_UEs);
+  if (UE_info->num_UEs == 0)
+    return;
+
+  const int UE_id = 0;
+  const int CC_id = 0;
+
+  NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+
+  const int tda = 1;
+  const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
+    sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
+  AssertFatal(tda < tdaList->list.count,
+              "time domain assignment %d >= %d\n",
+              tda,
+              tdaList->list.count);
+  int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
+  const int sched_frame = frame + (slot + K2 >= num_slots_per_tdd);
+  const int sched_slot = (slot + K2) % num_slots_per_tdd;
+  /* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
+   * limitations).  Note that if K2 or the TDD configuration is changed, below
+   * conditions might exclude each other and never be true */
+  if (!(is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot) && sched_slot == 8))
+    return;
+
+  const uint16_t rbStart = 0;
+  const uint16_t rbSize = 50; /* due to OAI UE limitations */
+  uint16_t *vrb_map_UL =
+      &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * 275];
+  for (int i = rbStart; i < rbStart + rbSize; ++i) {
+    if (vrb_map_UL[i]) {
+      LOG_E(MAC,
+            "%s(): %4d.%2d RB %d is already reserved, cannot schedule UE\n",
+            __func__,
+            frame,
+            slot,
+            i);
+      return;
+    }
+  }
+
+  sched_ctrl->sched_pusch->time_domain_allocation = tda;
+  sched_ctrl->sched_pusch->slot = sched_slot;
+  sched_ctrl->sched_pusch->frame = sched_frame;
+
+  const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
+  sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
+  uint8_t nr_of_candidates;
+  find_aggregation_candidates(&sched_ctrl->aggregation_level,
+                              &nr_of_candidates,
+                              sched_ctrl->search_space);
+  sched_ctrl->coreset = get_coreset(
+      sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */);
+  const int cid = sched_ctrl->coreset->controlResourceSetId;
+  const uint16_t Y = UE_info->Y[UE_id][cid][slot];
+  const int m = UE_info->num_pdcch_cand[UE_id][cid];
+  sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
+                                           sched_ctrl->active_bwp,
+                                           sched_ctrl->coreset,
+                                           sched_ctrl->aggregation_level,
+                                           Y,
+                                           m,
+                                           nr_of_candidates);
+  if (sched_ctrl->cce_index < 0) {
+    LOG_E(MAC, "%s(): CCE list not empty, couldn't schedule PUSCH\n", __func__);
+    return;
+  }
+  UE_info->num_pdcch_cand[UE_id][cid]++;
+
+  sched_ctrl->sched_pusch->mcs = 9;
+  sched_ctrl->sched_pusch->rbStart = rbStart;
+  sched_ctrl->sched_pusch->rbSize = rbSize;
+
+  /* mark the corresponding RBs as used */
+  for (int rb = rbStart; rb < rbStart + rbSize; rb++)
+    vrb_map_UL[rb] = 1;
+}

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c

@@ -481,7 +481,6 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
 
   const int UE_id = 0;
   const int CC_id = 0;
-
   NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
 
   const int tda = 1;
@@ -494,16 +493,19 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
   int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
   const int sched_frame = frame + (slot + K2 >= num_slots_per_tdd);
   const int sched_slot = (slot + K2) % num_slots_per_tdd;
-  /* check if slot is UL, and for phy test verify that it is in first TDD
-   * period, slot 8 (for K2=6, this is at slot 2 in the gNB; because of UE
-   * limitations).  Note that if K2 or the TDD configuration is changed, below
-   * conditions might exclude each other and never be true */
-  const bool transmit =
-      is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
-      && (!get_softmodem_params()->phy_test || sched_slot == 8);
-  if (!transmit)
+  if (!is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot))
     return;
 
+  /* get first, largest unallocated region */
+  uint16_t *vrb_map_UL =
+      &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * 275];
+  uint16_t rbStart = 0;
+  while (vrb_map_UL[rbStart]) rbStart++;
+  const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+  uint16_t rbSize = 1;
+  while (rbStart + rbSize < bwpSize && !vrb_map_UL[rbStart+rbSize])
+    rbSize++;
+
   sched_ctrl->sched_pusch->time_domain_allocation = tda;
   sched_ctrl->sched_pusch->slot = sched_slot;
   sched_ctrl->sched_pusch->frame = sched_frame;
@@ -533,12 +535,9 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
   UE_info->num_pdcch_cand[UE_id][cid]++;
 
   sched_ctrl->sched_pusch->mcs = 9;
-  sched_ctrl->sched_pusch->rbStart = 0;
-  sched_ctrl->sched_pusch->rbSize = get_softmodem_params()->phy_test ?
-    50 : NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+  sched_ctrl->sched_pusch->rbStart = rbStart;
+  sched_ctrl->sched_pusch->rbSize = rbSize;
 
-  uint16_t *vrb_map_UL =
-      &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * 275];
   /* mark the corresponding RBs as used */
   for (int rb = 0; rb < sched_ctrl->sched_pusch->rbSize; rb++)
     vrb_map_UL[rb + sched_ctrl->sched_pusch->rbStart] = 1;

openair2/LAYER2/NR_MAC_gNB/mac_proto.h

@@ -152,6 +152,13 @@ void nr_preprocessor_phytest(module_id_t module_id,
                              frame_t frame,
                              sub_frame_t slot,
                              int num_slots_per_tdd);
+/* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a
+ * fixed set of resources */
+void nr_ul_preprocessor_phytest(module_id_t module_id,
+                                frame_t frame,
+                                sub_frame_t slot,
+                                int num_slots_per_tdd,
+                                uint64_t ulsch_in_slot_bitmap);
 
 void nr_schedule_css_dlsch_phytest(module_id_t   module_idP,
                                    frame_t       frameP,
@@ -287,6 +294,8 @@ void find_aggregation_candidates(uint8_t *aggregation_level,
                                  uint8_t *nr_of_candidates,
                                  NR_SearchSpace_t *ss);
 
+long get_K2(NR_BWP_Uplink_t *ubwp, int time_domain_assignment, int mu);
+
 uint8_t nr_get_tpc(int target, uint8_t cqi, int incr);
 
 int get_spf(nfapi_nr_config_request_scf_t *cfg);

openair2/LAYER2/NR_MAC_gNB/main.c

@@ -82,12 +82,13 @@ void mac_top_init_gNB(void)
         
       RC.nrmac[i]->ul_handle = 0;
 
-      if (get_softmodem_params()->phy_test)
+      if (get_softmodem_params()->phy_test) {
         RC.nrmac[i]->pre_processor_dl = nr_preprocessor_phytest;
-      else
+        RC.nrmac[i]->pre_processor_ul = nr_ul_preprocessor_phytest;
+      } else {
         RC.nrmac[i]->pre_processor_dl = nr_simple_dlsch_preprocessor;
-
         RC.nrmac[i]->pre_processor_ul = nr_simple_ulsch_preprocessor;
+      }
 
     }//END for (i = 0; i < RC.nb_nr_macrlc_inst; i++)