Commit 6eea5b9c authored by Eurecom's avatar Eurecom

testing ok for 40,50,60 MHz BW.

parent 2c010009
...@@ -737,10 +737,6 @@ int phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { ...@@ -737,10 +737,6 @@ int phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) {
} }
} }
stop_meas(&gNB->phy_proc_rx); stop_meas(&gNB->phy_proc_rx);
// figure out a better way to choose slot_rx, 19 is ok for a particular TDD configuration with 30kHz SCS
if ((frame_rx&127) == 0 && slot_rx==19) {
LOG_I(PHY, "Number of bad PUCCH received: %lu\n", gNB->bad_pucch);
}
if (pucch_decode_done || pusch_decode_done) { if (pucch_decode_done || pusch_decode_done) {
T(T_GNB_PHY_PUCCH_PUSCH_IQ, T_INT(frame_rx), T_INT(slot_rx), T_BUFFER(&gNB->common_vars.rxdataF[0][0], gNB->frame_parms.symbols_per_slot * gNB->frame_parms.ofdm_symbol_size * 4)); T(T_GNB_PHY_PUCCH_PUSCH_IQ, T_INT(frame_rx), T_INT(slot_rx), T_BUFFER(&gNB->common_vars.rxdataF[0][0], gNB->frame_parms.symbols_per_slot * gNB->frame_parms.ofdm_symbol_size * 4));
......
...@@ -3281,10 +3281,10 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD ...@@ -3281,10 +3281,10 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_rbs = -1; type0_PDCCH_CSS_config->num_rbs = -1;
type0_PDCCH_CSS_config->num_symbols = -1; type0_PDCCH_CSS_config->num_symbols = -1;
type0_PDCCH_CSS_config->rb_offset = -1; type0_PDCCH_CSS_config->rb_offset = -1;
LOG_D(NR_MAC,"scs_ssb %d, scs_pdcch %d\n",scs_ssb,scs_pdcch); LOG_D(NR_MAC,"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",(int)NR_SubcarrierSpacing_kHz30,(int)scs_ssb,(int)scs_pdcch,min_channel_bw);
// type0-pdcch coreset // type0-pdcch coreset
switch( (scs_ssb << 3) | scs_pdcch ){ switch( ((int)scs_ssb << 3) | (int)scs_pdcch ){
case (NR_SubcarrierSpacing_kHz15 << 5) | NR_SubcarrierSpacing_kHz15: case (NR_SubcarrierSpacing_kHz15 << 5) | NR_SubcarrierSpacing_kHz15:
AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n"); AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n");
type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1; type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1;
...@@ -3394,13 +3394,14 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD ...@@ -3394,13 +3394,14 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
break; break;
default: default:
LOG_E(NR_MAC,"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",NR_SubcarrierSpacing_kHz30,(int)scs_ssb,(int)scs_pdcch,min_channel_bw);
break; break;
} }
LOG_D(NR_MAC,"Coreset0: index_4msb=%d, num_rbs=%d, num_symb=%d, rb_offset=%d\n", LOG_D(NR_MAC,"Coreset0: index_4msb=%d, num_rbs=%d, num_symb=%d, rb_offset=%d\n",
index_4msb,type0_PDCCH_CSS_config->num_rbs,type0_PDCCH_CSS_config->num_symbols,type0_PDCCH_CSS_config->rb_offset ); index_4msb,type0_PDCCH_CSS_config->num_rbs,type0_PDCCH_CSS_config->num_symbols,type0_PDCCH_CSS_config->rb_offset );
AssertFatal(type0_PDCCH_CSS_config->num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined"); AssertFatal(type0_PDCCH_CSS_config->num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined, index_4msb=%d, min_channel_bw %d, scs_ssb %d, scs_pdcch %d\n",index_4msb,min_channel_bw,(int)scs_ssb,(int)scs_pdcch);
AssertFatal(type0_PDCCH_CSS_config->num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined"); AssertFatal(type0_PDCCH_CSS_config->num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
AssertFatal(type0_PDCCH_CSS_config->rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined"); AssertFatal(type0_PDCCH_CSS_config->rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
......
...@@ -402,7 +402,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -402,7 +402,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} }
if ((slot == 0) && (frame & 127) == 0) dump_mac_stats(RC.nrmac[module_idP]); // if ((slot == 0) && (frame & 127) == 0) dump_mac_stats(RC.nrmac[module_idP]);
// This schedules MIB // This schedules MIB
......
...@@ -1180,7 +1180,6 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1180,7 +1180,6 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
NR_BWP_Downlink_t *bwp = NULL; NR_BWP_Downlink_t *bwp = NULL;
NR_ControlResourceSet_t *coreset = NULL; NR_ControlResourceSet_t *coreset = NULL;
NR_BWP_t *genericParameters = NULL;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList=NULL; NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList=NULL;
if (ra->CellGroup && if (ra->CellGroup &&
...@@ -1189,11 +1188,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1189,11 +1188,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList && ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList &&
ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]) { ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]) {
bwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; bwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1];
genericParameters = &bwp->bwp_Common->genericParameters;
pdsch_TimeDomainAllocationList = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; pdsch_TimeDomainAllocationList = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
} }
else { else {
genericParameters= &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
pdsch_TimeDomainAllocationList = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; pdsch_TimeDomainAllocationList = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
} }
coreset = get_coreset(scc,bwp, ss, NR_SearchSpace__searchSpaceType_PR_common); coreset = get_coreset(scc,bwp, ss, NR_SearchSpace__searchSpaceType_PR_common);
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
#include "SIMULATION/TOOLS/sim.h" #include "SIMULATION/TOOLS/sim.h"
#include "executables/softmodem-common.h" #include "executables/softmodem-common.h"
#include "LAYER2/nr_rlc/nr_rlc_oai_api.h" #include "LAYER2/nr_rlc/nr_rlc_oai_api.h"
#include "LAYER2/NR_MAC_COMMON/nr_mac.h"
#define false 0 #define false 0
#define true 1 #define true 1
...@@ -66,6 +66,8 @@ void fill_default_coresetZero(NR_ControlResourceSet_t *coreset0, ...@@ -66,6 +66,8 @@ void fill_default_coresetZero(NR_ControlResourceSet_t *coreset0,
NR_Type0_PDCCH_CSS_config_t type0_PDCCH_CSS_config; NR_Type0_PDCCH_CSS_config_t type0_PDCCH_CSS_config;
int num_slot_per_frame = 10*(1<<ssbSubcarrierSpacing); int num_slot_per_frame = 10*(1<<ssbSubcarrierSpacing);
LOG_I(NR_RRC,"num_slot_per_frame %d, ssb_subcarrier_offset %d,ssb_start_symbol %d, ssbSubcarrierSpacing %d, frequency_range %d, ssboffset_pointa %d\n",
num_slot_per_frame,ssb_subcarrier_offset,ssb_start_symbol,ssbSubcarrierSpacing,frequency_range,ssboffset_pointa);
get_type0_PDCCH_CSS_config_parameters(&type0_PDCCH_CSS_config, get_type0_PDCCH_CSS_config_parameters(&type0_PDCCH_CSS_config,
0, 0,
mib, mib,
......
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