Commit 887c8acd authored by masayuki.harada's avatar masayuki.harada

Fix initial TA with MIMO-L1

parent eedd7591
...@@ -68,8 +68,9 @@ fill_rar(const module_id_t module_idP, ...@@ -68,8 +68,9 @@ fill_rar(const module_id_t module_idP,
rar[4] = (uint8_t) (ra->rnti >> 8); rar[4] = (uint8_t) (ra->rnti >> 8);
rar[5] = (uint8_t) (ra->rnti & 0xff); rar[5] = (uint8_t) (ra->rnti & 0xff);
//ra->timing_offset = 0; //ra->timing_offset = 0;
#ifndef PHY_RM
ra->timing_offset /= 16; //T_A = N_TA/16, where N_TA should be on a 30.72Msps ra->timing_offset /= 16; //T_A = N_TA/16, where N_TA should be on a 30.72Msps
// ra->timing_offset /= 16; //T_A = N_TA/16, where N_TA should be on a 30.72Msps #endif
// rar[0] = (uint8_t) (ra->timing_offset >> (2 + 4)); // 7 MSBs of timing advance + divide by 4 // rar[0] = (uint8_t) (ra->timing_offset >> (2 + 4)); // 7 MSBs of timing advance + divide by 4
// rar[1] = (uint8_t) (ra->timing_offset << (4 - 2)) & 0xf0; // 4 LSBs of timing advance + divide by 4 // rar[1] = (uint8_t) (ra->timing_offset << (4 - 2)) & 0xf0; // 4 LSBs of timing advance + divide by 4
rar[0] = (uint8_t) (ra->timing_offset >> 4); // 7 MSBs of timing advance rar[0] = (uint8_t) (ra->timing_offset >> 4); // 7 MSBs of timing advance
......
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