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wangjie
OpenXG-RAN
Commits
a05e595a
Commit
a05e595a
authored
Jul 16, 2021
by
hardy
Browse files
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Merge remote-tracking branch 'origin/dongzhanyi-zte-develop1' into integration_2021_wk28
parents
33a2f1df
88b8b421
Changes
3
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3 changed files
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19 additions
and
19 deletions
+19
-19
openair1/PHY/NR_TRANSPORT/nr_dci.c
openair1/PHY/NR_TRANSPORT/nr_dci.c
+17
-17
openair1/PHY/NR_TRANSPORT/nr_dci.h
openair1/PHY/NR_TRANSPORT/nr_dci.h
+1
-1
openair1/SCHED_NR/phy_procedures_nr_gNB.c
openair1/SCHED_NR/phy_procedures_nr_gNB.c
+1
-1
No files found.
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @
a05e595a
...
@@ -70,7 +70,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -70,7 +70,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
uint32_t
**
gold_pdcch_dmrs
,
uint32_t
**
gold_pdcch_dmrs
,
int32_t
*
txdataF
,
int32_t
*
txdataF
,
int16_t
amp
,
int16_t
amp
,
NR_DL_FRAME_PARMS
frame_parms
)
{
NR_DL_FRAME_PARMS
*
frame_parms
)
{
int16_t
mod_dmrs
[
NR_MAX_CSET_DURATION
][
NR_MAX_PDCCH_DMRS_LENGTH
>>
1
]
__attribute__
((
aligned
(
16
)));
// 3 for the max coreset duration
int16_t
mod_dmrs
[
NR_MAX_CSET_DURATION
][
NR_MAX_PDCCH_DMRS_LENGTH
>>
1
]
__attribute__
((
aligned
(
16
)));
// 3 for the max coreset duration
uint16_t
cset_start_sc
;
uint16_t
cset_start_sc
;
...
@@ -85,7 +85,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -85,7 +85,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
// compute rb_offset and n_prb based on frequency allocation
// compute rb_offset and n_prb based on frequency allocation
nr_fill_cce_list
(
gNB
,
0
,
pdcch_pdu_rel15
);
nr_fill_cce_list
(
gNB
,
0
,
pdcch_pdu_rel15
);
get_coreset_rballoc
(
pdcch_pdu_rel15
->
FreqDomainResource
,
&
n_rb
,
&
rb_offset
);
get_coreset_rballoc
(
pdcch_pdu_rel15
->
FreqDomainResource
,
&
n_rb
,
&
rb_offset
);
cset_start_sc
=
frame_parms
.
first_carrier_offset
+
(
pdcch_pdu_rel15
->
BWPStart
+
rb_offset
)
*
NR_NB_SC_PER_RB
;
cset_start_sc
=
frame_parms
->
first_carrier_offset
+
(
pdcch_pdu_rel15
->
BWPStart
+
rb_offset
)
*
NR_NB_SC_PER_RB
;
for
(
int
d
=
0
;
d
<
pdcch_pdu_rel15
->
numDlDci
;
d
++
)
{
for
(
int
d
=
0
;
d
<
pdcch_pdu_rel15
->
numDlDci
;
d
++
)
{
/*The coreset is initialised
/*The coreset is initialised
...
@@ -165,8 +165,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -165,8 +165,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
/// Resource mapping
/// Resource mapping
if
(
cset_start_sc
>=
frame_parms
.
ofdm_symbol_size
)
if
(
cset_start_sc
>=
frame_parms
->
ofdm_symbol_size
)
cset_start_sc
-=
frame_parms
.
ofdm_symbol_size
;
cset_start_sc
-=
frame_parms
->
ofdm_symbol_size
;
// Get cce_list indices by reg_idx in ascending order
// Get cce_list indices by reg_idx in ascending order
int
reg_list_index
=
0
;
int
reg_list_index
=
0
;
...
@@ -191,8 +191,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -191,8 +191,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
k
=
cset_start_sc
+
gNB
->
cce_list
[
d
][
cce_idx
].
reg_list
[
reg_in_cce_idx
].
start_sc_idx
;
k
=
cset_start_sc
+
gNB
->
cce_list
[
d
][
cce_idx
].
reg_list
[
reg_in_cce_idx
].
start_sc_idx
;
if
(
k
>=
frame_parms
.
ofdm_symbol_size
)
if
(
k
>=
frame_parms
->
ofdm_symbol_size
)
k
-=
frame_parms
.
ofdm_symbol_size
;
k
-=
frame_parms
->
ofdm_symbol_size
;
l
=
cset_start_symb
+
symbol_idx
;
l
=
cset_start_symb
+
symbol_idx
;
...
@@ -206,26 +206,26 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -206,26 +206,26 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
for
(
int
m
=
0
;
m
<
NR_NB_SC_PER_RB
;
m
++
)
{
for
(
int
m
=
0
;
m
<
NR_NB_SC_PER_RB
;
m
++
)
{
if
(
m
==
(
k_prime
<<
2
)
+
1
)
{
// DMRS if not already mapped
if
(
m
==
(
k_prime
<<
2
)
+
1
)
{
// DMRS if not already mapped
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
(
amp
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
amp
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
(
amp
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
#ifdef DEBUG_PDCCH_DMRS
#ifdef DEBUG_PDCCH_DMRS
printf
(
"PDCCH DMRS: l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
],
printf
(
"PDCCH DMRS: l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
],
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
#endif
#endif
dmrs_idx
++
;
dmrs_idx
++
;
k_prime
++
;
k_prime
++
;
}
else
{
// DCI payload
}
else
{
// DCI payload
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dci
[
dci_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dci
[
dci_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
amp
*
mod_dci
[(
dci_idx
<<
1
)
+
1
])
>>
15
;
(
amp
*
mod_dci
[(
dci_idx
<<
1
)
+
1
])
>>
15
;
#ifdef DEBUG_DCI
#ifdef DEBUG_DCI
printf
(
"PDCCH: l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
],
printf
(
"PDCCH: l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
],
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
->
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
#endif
#endif
dci_idx
++
;
dci_idx
++
;
...
@@ -233,8 +233,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
...
@@ -233,8 +233,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
k
++
;
k
++
;
if
(
k
>=
frame_parms
.
ofdm_symbol_size
)
if
(
k
>=
frame_parms
->
ofdm_symbol_size
)
k
-=
frame_parms
.
ofdm_symbol_size
;
k
-=
frame_parms
->
ofdm_symbol_size
;
}
// m
}
// m
}
// reg_in_cce_idx
}
// reg_in_cce_idx
...
@@ -254,7 +254,7 @@ void nr_generate_dci_top(PHY_VARS_gNB *gNB,
...
@@ -254,7 +254,7 @@ void nr_generate_dci_top(PHY_VARS_gNB *gNB,
uint32_t
**
gold_pdcch_dmrs
,
uint32_t
**
gold_pdcch_dmrs
,
int32_t
*
txdataF
,
int32_t
*
txdataF
,
int16_t
amp
,
int16_t
amp
,
NR_DL_FRAME_PARMS
frame_parms
)
{
NR_DL_FRAME_PARMS
*
frame_parms
)
{
AssertFatal
(
pdcch_pdu
!=
NULL
||
ul_dci_pdu
!=
NULL
,
"At least one pointer has to be !NULL
\n
"
);
AssertFatal
(
pdcch_pdu
!=
NULL
||
ul_dci_pdu
!=
NULL
,
"At least one pointer has to be !NULL
\n
"
);
...
...
openair1/PHY/NR_TRANSPORT/nr_dci.h
View file @
a05e595a
...
@@ -35,7 +35,7 @@ void nr_generate_dci_top(PHY_VARS_gNB *gNB,
...
@@ -35,7 +35,7 @@ void nr_generate_dci_top(PHY_VARS_gNB *gNB,
uint32_t
**
gold_pdcch_dmrs
,
uint32_t
**
gold_pdcch_dmrs
,
int32_t
*
txdataF
,
int32_t
*
txdataF
,
int16_t
amp
,
int16_t
amp
,
NR_DL_FRAME_PARMS
frame_parms
);
NR_DL_FRAME_PARMS
*
frame_parms
);
void
nr_pdcch_scrambling
(
uint32_t
*
in
,
void
nr_pdcch_scrambling
(
uint32_t
*
in
,
uint32_t
size
,
uint32_t
size
,
...
...
openair1/SCHED_NR/phy_procedures_nr_gNB.c
View file @
a05e595a
...
@@ -176,7 +176,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
...
@@ -176,7 +176,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
ul_pdcch_pdu_id
>=
0
?
&
gNB
->
ul_pdcch_pdu
[
ul_pdcch_pdu_id
].
pdcch_pdu
.
pdcch_pdu
:
NULL
,
ul_pdcch_pdu_id
>=
0
?
&
gNB
->
ul_pdcch_pdu
[
ul_pdcch_pdu_id
].
pdcch_pdu
.
pdcch_pdu
:
NULL
,
gNB
->
nr_gold_pdcch_dmrs
[
slot
],
gNB
->
nr_gold_pdcch_dmrs
[
slot
],
&
gNB
->
common_vars
.
txdataF
[
0
][
txdataF_offset
],
&
gNB
->
common_vars
.
txdataF
[
0
][
txdataF_offset
],
AMP
,
*
fp
);
AMP
,
fp
);
// free up entry in pdcch tables
// free up entry in pdcch tables
if
(
pdcch_pdu_id
>=
0
)
gNB
->
pdcch_pdu
[
pdcch_pdu_id
].
frame
=
-
1
;
if
(
pdcch_pdu_id
>=
0
)
gNB
->
pdcch_pdu
[
pdcch_pdu_id
].
frame
=
-
1
;
...
...
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