CR interleaved

openair1/PHY/NR_TRANSPORT/nr_dci_tools.c

@@ -32,8 +32,6 @@
 
 #include "nr_dci.h"
 
-
-
 void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) {
 
   nr_cce_t* cce;
@@ -50,7 +48,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
     AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
 
   N_cce = N_reg / NR_NB_REG_PER_CCE;
-  /*Max number of candidates per aggregation level*/
+  /*Max number of candidates per aggregation level -- SIB1 configured search space only*/
   M_s_max = (L==4)?4:(L==8)?2:1;
 
   if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON)
@@ -69,17 +67,37 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
     cce->cce_idx = tmp + cce_idx;
     LOG_D(PHY, "cce_idx %d\n", cce->cce_idx);
 
+    if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
+      LOG_I(PHY, "Interleaved CCE to REG mapping\n");
+      uint8_t j = cce->cce_idx, j_prime;
+      uint8_t r,c,idx;
+
+
       for (uint8_t reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
         reg = &cce->reg_list[reg_idx];
-      if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
-        
+        j_prime = 6*j/bsize + reg_idx;
+        r = j_prime%R;
+        c = (j_prime-r)/R;
+        idx = (r*C + c + n_shift)%(N_reg/bsize);
+        reg->reg_idx = idx;
+        LOG_I(PHY, "j = %d \t j_prime = %d \t r = %d \t c = %d \t idx = %d\n", j , j_prime, r, c, idx);
+        reg->start_sc_idx = (idx/pdcch_params->n_symb) * NR_NB_SC_PER_RB;
+        reg->symb_idx = idx % pdcch_params->n_symb;
+        LOG_I(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx);
+      }
     }
     else { // NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED
-        reg->start_sc_idx = (cce->cce_idx/pdcch_params->n_symb*NR_NB_REG_PER_CCE + reg_idx) * NR_NB_SC_PER_RB;
-        reg->symb_idx = cce->cce_idx % pdcch_params->n_symb;
-        LOG_I(PHY, "reg %d symbol %d start subcarrier %d\n", reg_idx, reg->symb_idx, reg->start_sc_idx);
+      LOG_D(PHY, "Non interleaved CCE to REG mapping\n");
+      for (uint8_t reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
+        reg = &cce->reg_list[reg_idx];
+        reg->reg_idx = cce->cce_idx*NR_NB_REG_PER_CCE + reg_idx;
+        reg->start_sc_idx = (reg->reg_idx/pdcch_params->n_symb) * NR_NB_SC_PER_RB;
+        reg->symb_idx = reg->reg_idx % pdcch_params->n_symb;
+        LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx);
       }
+
     }
+
   }
 }
 
@@ -149,7 +167,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
   n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)?
                       cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index;
   nr_fill_cce_list(dci_alloc, n_shift, cand_idx);
-  LOG_I(PHY, "DCI type %d payload (size %d) generated\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size);
+  LOG_I(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx);