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wangjie
OpenXG-RAN
Commits
ae8c8cf5
Commit
ae8c8cf5
authored
Dec 13, 2020
by
ChiehChun
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Check slot is DL slot to pre-schedule UL data
parent
2a70fcea
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
ae8c8cf5
...
@@ -685,6 +685,10 @@ void nr_schedule_ulsch(module_id_t module_id,
...
@@ -685,6 +685,10 @@ void nr_schedule_ulsch(module_id_t module_id,
int
num_slots_per_tdd
,
int
num_slots_per_tdd
,
int
ul_slots
,
int
ul_slots
,
uint64_t
ulsch_in_slot_bitmap
)
{
uint64_t
ulsch_in_slot_bitmap
)
{
if
(
is_xlsch_in_slot
(
ulsch_in_slot_bitmap
,
slot
%
num_slots_per_tdd
))
{
LOG_D
(
MAC
,
"Current slot %d is NOT DL slot, cannot schedule DCI0 for UL data
\n
"
,
slot
);
return
;
}
RC
.
nrmac
[
module_id
]
->
pre_processor_ul
(
RC
.
nrmac
[
module_id
]
->
pre_processor_ul
(
module_id
,
frame
,
slot
,
num_slots_per_tdd
,
ulsch_in_slot_bitmap
);
module_id
,
frame
,
slot
,
num_slots_per_tdd
,
ulsch_in_slot_bitmap
);
...
...
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