Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
O
OpenXG-RAN
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
wangjie
OpenXG-RAN
Commits
c2c46874
Commit
c2c46874
authored
Sep 24, 2020
by
Sakthivel Velumani
Committed by
Robert Schmidt
Oct 08, 2020
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fixed cce indexing to allow multiple pdcch on single coreset
parent
2a4153eb
Changes
8
Show whitespace changes
Inline
Side-by-side
Showing
8 changed files
with
109 additions
and
57 deletions
+109
-57
openair1/PHY/NR_TRANSPORT/nr_dci.c
openair1/PHY/NR_TRANSPORT/nr_dci.c
+26
-20
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+3
-0
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+7
-7
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+10
-5
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+23
-14
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+31
-9
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+3
-2
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+6
-0
No files found.
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @
c2c46874
...
...
@@ -64,11 +64,8 @@ void nr_pdcch_scrambling(uint32_t *in,
}
}
uint8_t
nr_generate_dci_top
(
PHY_VARS_gNB
*
gNB
,
nfapi_nr_dl_tti_pdcch_pdu
*
pdcch_pdu
,
nfapi_nr_dl_tti_pdcch_pdu
*
ul_dci_pdu
,
uint8_t
nr_generate_dci
(
PHY_VARS_gNB
*
gNB
,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu_rel15
,
uint32_t
**
gold_pdcch_dmrs
,
int32_t
*
txdataF
,
int16_t
amp
,
...
...
@@ -78,23 +75,12 @@ uint8_t nr_generate_dci_top(PHY_VARS_gNB *gNB,
uint16_t
cset_start_sc
;
uint8_t
cset_start_symb
,
cset_nsymb
;
int
k
,
l
,
k_prime
,
dci_idx
,
dmrs_idx
;
/*First iteration: single DCI*/
nfapi_nr_dl_tti_pdcch_pdu_rel15_t
*
pdcch_pdu_rel15
=
NULL
;
// find coreset descriptor
int
rb_offset
;
int
n_rb
;
AssertFatal
(
pdcch_pdu
!=
NULL
||
ul_dci_pdu
!=
NULL
,
"At least one pointer has to be !NULL
\n
"
);
AssertFatal
(
pdcch_pdu
==
NULL
||
ul_dci_pdu
==
NULL
,
"Can't handle both DL and UL DCI in same slot
\n
"
);
if
(
pdcch_pdu
)
pdcch_pdu_rel15
=
&
pdcch_pdu
->
pdcch_pdu_rel15
;
else
if
(
ul_dci_pdu
)
pdcch_pdu_rel15
=
&
ul_dci_pdu
->
pdcch_pdu_rel15
;
nr_fill_cce_list
(
gNB
,
0
,
pdcch_pdu_rel15
);
get_coreset_rballoc
(
pdcch_pdu_rel15
->
FreqDomainResource
,
&
n_rb
,
&
rb_offset
);
...
...
@@ -244,3 +230,23 @@ uint8_t nr_generate_dci_top(PHY_VARS_gNB *gNB,
return
0
;
}
uint8_t
nr_generate_dci_top
(
PHY_VARS_gNB
*
gNB
,
nfapi_nr_dl_tti_pdcch_pdu
*
pdcch_pdu
,
nfapi_nr_dl_tti_pdcch_pdu
*
ul_dci_pdu
,
uint32_t
**
gold_pdcch_dmrs
,
int32_t
*
txdataF
,
int16_t
amp
,
NR_DL_FRAME_PARMS
frame_parms
)
{
AssertFatal
(
pdcch_pdu
!=
NULL
||
ul_dci_pdu
!=
NULL
,
"At least one pointer has to be !NULL
\n
"
);
if
(
pdcch_pdu
&&
ul_dci_pdu
)
return
(
nr_generate_dci
(
gNB
,
&
pdcch_pdu
->
pdcch_pdu_rel15
,
gold_pdcch_dmrs
,
txdataF
,
amp
,
frame_parms
)
||
nr_generate_dci
(
gNB
,
&
ul_dci_pdu
->
pdcch_pdu_rel15
,
gold_pdcch_dmrs
,
txdataF
,
amp
,
frame_parms
));
else
if
(
pdcch_pdu
)
return
nr_generate_dci
(
gNB
,
&
pdcch_pdu
->
pdcch_pdu_rel15
,
gold_pdcch_dmrs
,
txdataF
,
amp
,
frame_parms
);
else
if
(
ul_dci_pdu
)
return
nr_generate_dci
(
gNB
,
&
ul_dci_pdu
->
pdcch_pdu_rel15
,
gold_pdcch_dmrs
,
txdataF
,
amp
,
frame_parms
);
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
c2c46874
...
...
@@ -440,6 +440,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coreset0
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coresetid 1
for
(
int
i
=
0
;
i
<
MAX_NUM_CORESET
;
i
++
)
RC
.
nrmac
[
module_idP
]
->
UE_info
.
num_pdcch_cand
[
UE_id
][
i
]
=
0
;
for
(
int
CC_id
=
0
;
CC_id
<
MAX_NUM_CCs
;
CC_id
++
)
{
//mbsfn_status[CC_id] = 0;
...
...
@@ -469,6 +471,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// This schedule RA procedure if not in phy_test mode
// Otherwise already consider 5G already connected
RC
.
nrmac
[
module_idP
]
->
current_slot
=
slot
;
if
(
get_softmodem_params
()
->
phy_test
==
0
)
{
nr_schedule_RA
(
module_idP
,
frame
,
slot
);
nr_schedule_reception_msg3
(
module_idP
,
0
,
frame
,
slot
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
c2c46874
...
...
@@ -674,13 +674,13 @@ void nr_generate_Msg2(module_id_t module_idP,
uint8_t
nr_of_candidates
,
aggregation_level
;
find_aggregation_candidates
(
&
aggregation_level
,
&
nr_of_candidates
,
ss
);
NR_ControlResourceSet_t
*
coreset
=
get_coreset
(
bwp
,
ss
,
0
/* common */
);
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
bwp
,
coreset
,
aggregation_level
,
0
,
/* n_RNTI 0: common search space */
0
);
// m
0
,
// Y
0
,
// m
nr_of_candidates
);
if
(
CCEIndex
<
0
)
{
LOG_E
(
MAC
,
"%s(): cannot find free CCE for RA RNTI %04x!
\n
"
,
__func__
,
ra
->
rnti
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
c2c46874
...
...
@@ -488,16 +488,21 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
sched_ctrl
->
search_space
);
sched_ctrl
->
coreset
=
get_coreset
(
sched_ctrl
->
active_bwp
,
sched_ctrl
->
search_space
,
1
/* dedicated */
);
int
cid
=
sched_ctrl
->
coreset
->
controlResourceSetId
;
const
uint16_t
Y
=
UE_info
->
Y
[
UE_id
][
cid
][
slot
];
const
int
m
=
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
];
sched_ctrl
->
cce_index
=
allocate_nr_CCEs
(
RC
.
nrmac
[
module_id
],
sched_ctrl
->
active_bwp
,
sched_ctrl
->
coreset
,
sched_ctrl
->
aggregation_level
,
UE_info
->
rnti
[
UE_id
],
0
);
// m
Y
,
m
,
nr_of_candidates
);
if
(
sched_ctrl
->
cce_index
<
0
)
{
LOG_E
(
MAC
,
"%s(): could not find CCE for UE %d
\n
"
,
__func__
,
UE_id
);
return
;
}
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
]
++
;
/* Find PUCCH occasion */
nr_update_pucch_scheduling
(
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
c2c46874
...
...
@@ -417,18 +417,23 @@ int configure_fapi_dl_pdu_phytest(int Mod_idP,
uint8_t
nr_of_candidates
,
aggregation_level
;
find_aggregation_candidates
(
&
aggregation_level
,
&
nr_of_candidates
,
ss
);
NR_ControlResourceSet_t
*
coreset
=
get_coreset
(
bwp
,
ss
,
1
/* dedicated */
);
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
const
int
cid
=
coreset
->
controlResourceSetId
;
const
uint16_t
Y
=
UE_info
->
Y
[
UE_id
][
cid
][
nr_mac
->
current_slot
];
const
int
m
=
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
];
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
bwp
,
coreset
,
aggregation_level
,
UE_info
->
rnti
[
UE_id
],
0
);
// m
Y
,
m
,
nr_of_candidates
);
if
(
CCEIndex
<
0
)
{
LOG_E
(
MAC
,
"%s(): CCE list not empty, couldn't schedule PDSCH
\n
"
,
__func__
);
free
(
dci_pdu_rel15
);
return
0
;
}
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
]
++
;
nr_configure_pdcch
(
nr_mac
,
pdcch_pdu_rel15
,
UE_info
->
rnti
[
UE_id
],
...
...
@@ -1126,19 +1131,23 @@ void schedule_fapi_ul_pdu(int Mod_idP,
uint8_t
nr_of_candidates
,
aggregation_level
;
find_aggregation_candidates
(
&
aggregation_level
,
&
nr_of_candidates
,
ss
);
NR_ControlResourceSet_t
*
coreset
=
get_coreset
(
bwp
,
ss
,
1
/* dedicated */
);
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
const
int
cid
=
coreset
->
controlResourceSetId
;
const
uint16_t
Y
=
UE_info
->
Y
[
UE_id
][
cid
][
nr_mac
->
current_slot
];
const
int
m
=
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
];
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
bwp
,
coreset
,
aggregation_level
,
UE_info
->
rnti
[
UE_id
],
0
);
// m
Y
,
m
,
nr_of_candidates
);
if
(
CCEIndex
<
0
)
{
LOG_E
(
MAC
,
"%s(): CCE list not empty, couldn't schedule PUSCH
\n
"
,
__func__
);
pusch_sched
->
active
=
false
;
return
;
}
else
{
UE_info
->
num_pdcch_cand
[
UE_id
][
cid
]
++
;
nr_configure_pdcch
(
nr_mac
,
pdcch_pdu_rel15
,
UE_info
->
rnti
[
UE_id
],
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
c2c46874
...
...
@@ -172,8 +172,9 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
NR_BWP_Downlink_t
*
bwp
,
NR_ControlResourceSet_t
*
coreset
,
int
aggregation
,
uint16_t
n_RNTI
,
int
m
)
{
uint16_t
Y
,
int
m
,
int
nr_of_candidates
)
{
// uncomment these when we allocate for common search space
// NR_COMMON_channels_t *cc = nr_mac->common_channels;
// NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
...
...
@@ -189,15 +190,19 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
n_rb
*=
6
;
uint16_t
N_reg
=
n_rb
*
coreset
->
duration
;
uint16_t
n_CI
=
0
;
const
uint32_t
A
[
3
]
=
{
39827
,
39829
,
39839
};
/* if n_RNTI is zero, this results in zero, too! */
uint16_t
Y
=
(
A
[
0
]
*
n_RNTI
)
%
65537
;
// Candidate 0, antenna port 0
uint16_t
n_CI
=
0
;
uint16_t
N_cce
=
N_reg
/
NR_NB_REG_PER_CCE
;
const
uint16_t
N_cce
=
N_reg
/
NR_NB_REG_PER_CCE
;
const
uint16_t
M_s_max
=
nr_of_candidates
;
uint16_t
M_s_max
=
(
aggregation
==
4
)
?
4
:
(
aggregation
==
8
)
?
2
:
1
;
int
first_cce
=
aggregation
*
((
Y
+
(
m
*
N_cce
)
/
(
aggregation
*
M_s_max
)
+
n_CI
)
%
CEILIDIV
(
N_cce
,
aggregation
));
AssertFatal
(
m
<
nr_of_candidates
,
"PDCCH candidate index %d in CORESET %d exceeds the maximum "
"number of PDCCH candidates (%d)
\n
"
,
m
,
coreset_id
,
nr_of_candidates
);
int
first_cce
=
aggregation
*
((
Y
+
CEILIDIV
((
m
*
N_cce
),(
aggregation
*
M_s_max
))
+
n_CI
)
%
CEILIDIV
(
N_cce
,
aggregation
));
for
(
int
i
=
0
;
i
<
aggregation
;
i
++
)
if
(
cce_list
[
first_cce
+
i
]
!=
0
)
return
(
-
1
);
...
...
@@ -1619,6 +1624,22 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP)
return
-
1
;
}
void
set_Y
(
NR_UE_list_t
*
UE_list
,
int
UE_id
)
{
int
A
[
3
]
=
{
39827
,
39829
,
39839
};
int
D
=
65537
;
int
s
=
0
;
UE_list
->
Y
[
UE_id
][
0
][
s
]
=
(
A
[
0
]
*
UE_list
->
rnti
[
UE_id
])
%
D
;
UE_list
->
Y
[
UE_id
][
1
][
s
]
=
(
A
[
1
]
*
UE_list
->
rnti
[
UE_id
])
%
D
;
UE_list
->
Y
[
UE_id
][
2
][
s
]
=
(
A
[
2
]
*
UE_list
->
rnti
[
UE_id
])
%
D
;
for
(
s
=
1
;
s
<
160
;
s
++
)
{
UE_list
->
Y
[
UE_id
][
0
][
s
]
=
(
A
[
0
]
*
UE_list
->
Y
[
UE_id
][
0
][
s
-
1
])
%
D
;
UE_list
->
Y
[
UE_id
][
1
][
s
]
=
(
A
[
1
]
*
UE_list
->
Y
[
UE_id
][
1
][
s
-
1
])
%
D
;
UE_list
->
Y
[
UE_id
][
2
][
s
]
=
(
A
[
2
]
*
UE_list
->
Y
[
UE_id
][
2
][
s
-
1
])
%
D
;
}
}
int
add_new_nr_ue
(
module_id_t
mod_idP
,
rnti_t
rntiP
){
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
mod_idP
]
->
UE_info
;
...
...
@@ -1642,6 +1663,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
UE_info
->
active
[
UE_id
]
=
true
;
UE_info
->
rnti
[
UE_id
]
=
rntiP
;
add_nr_ue_list
(
&
UE_info
->
list
,
UE_id
);
set_Y
(
UE_info
,
UE_id
);
memset
((
void
*
)
&
UE_info
->
UE_sched_ctrl
[
UE_id
],
0
,
sizeof
(
NR_UE_sched_ctrl_t
));
...
...
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
c2c46874
...
...
@@ -314,8 +314,9 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
NR_BWP_Downlink_t
*
bwp
,
NR_ControlResourceSet_t
*
coreset
,
int
aggregation
,
uint16_t
n_RNTI
,
int
m
);
uint16_t
Y
,
int
m
,
int
nr_of_candidates
);
int
get_dlscs
(
nfapi_nr_config_request_t
*
cfg
);
...
...
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @
c2c46874
...
...
@@ -380,6 +380,10 @@ typedef struct {
bool
active
[
MAX_MOBILES_PER_GNB
];
rnti_t
rnti
[
MAX_MOBILES_PER_GNB
];
NR_CellGroupConfig_t
*
secondaryCellGroup
[
MAX_MOBILES_PER_GNB
];
/// CCE indexing
int
Y
[
MAX_MOBILES_PER_GNB
][
3
][
160
];
int
m
[
MAX_MOBILES_PER_GNB
];
int
num_pdcch_cand
[
MAX_MOBILES_PER_GNB
][
MAX_NUM_CORESET
];
}
NR_UE_info_t
;
/*! \brief top level eNB MAC structure */
...
...
@@ -442,6 +446,8 @@ typedef struct gNB_MAC_INST_s {
time_stats_t
schedule_pch
;
/// CCE lists
int
cce_list
[
MAX_NUM_BWP
][
MAX_NUM_CORESET
][
MAX_NUM_CCE
];
/// current slot
int
current_slot
;
}
gNB_MAC_INST
;
#endif
/*__LAYER2_NR_MAC_GNB_H__ */
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment