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dma_ip_drivers
Commit 00b6d04a authored by Sujatha Banoth's avatar Sujatha Banoth
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2020.2 QDMA DPDK Driver Release 

2020.2 QDMA DPDK Driver Release
parent 5f12009e
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QDMA/DPDK/RELEASE
View file @ 00b6d04a
RELEASE: 2020.1 Patch RELEASE: 2020.2
===================== ===============
This release is based on DPDK v19.11 and contains QDMA poll mode driver and This release is based on DPDK v19.11 and contains QDMA poll mode driver and
QDMA test application. This release is validated on QDMA4.0 2020.1 Patch based QDMA test application.
example design.
This release is validated for VCU1525 and U200 devices on QDMA4.0 2020.2 based example design
and QDMA3.1 2020.2 based example design.
This release includes a patch file for dpdk-pktgen v19.12.0 that extends This release includes a patch file for dpdk-pktgen v19.12.0 that extends
dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes
and it disables the packet size classification logic in dpdk-pktgen to remove and it disables the packet size classification logic in dpdk-pktgen to remove
application overhead in performance measurement. application overhead in performance measurement.
This patch is used for performance testing with dpdk-pktgen application.
This patch is used for performance testing with dpdk-pktgen application.
The driver is validated against dpdk-pktgen and testpmd applications for API compliance. The driver is validated against dpdk-pktgen and testpmd applications for API compliance.
SUPPORTED FEATURES: SUPPORTED FEATURES:
...@@ -75,6 +77,14 @@ SUPPORTED FEATURES: ...@@ -75,6 +77,14 @@ SUPPORTED FEATURES:
- Verified QDMA DPDK software with IOVA=VA mode by enabling hugepage allocation matching support in DPDK - Verified QDMA DPDK software with IOVA=VA mode by enabling hugepage allocation matching support in DPDK
(i.e. by specifying the --match-allocations command-line switch to the EAL). (i.e. by specifying the --match-allocations command-line switch to the EAL).
2020.2 Updates
--------------
- Added support for detailed register dump
- Added support for post processing HW error messages
- Added support for Debug mode and Internal only mode
- Resolved the issue related to mbuf packet length
- Fixed VF FMAP programming of qmax issue by setting qmax to the actual user configured total queue number
KNOWN ISSUES: KNOWN ISSUES:
============= =============
- Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure - Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
......
QDMA/DPDK/drivers/net/qdma/Makefile
View file @ 00b6d04a
...@@ -83,7 +83,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_rxtx.c ...@@ -83,7 +83,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_rxtx.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_xdebug.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_xdebug.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_user.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_user.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/eqdma_soft_access/eqdma_soft_access.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/eqdma_soft_access/eqdma_soft_access.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_soft_access/qdma_soft_access.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_soft_access/qdma_soft_access.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_list.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_list.c
SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_resource_mgmt.c SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_resource_mgmt.c
......
QDMA/DPDK/drivers/net/qdma/qdma.h
View file @ 00b6d04a
...@@ -44,9 +44,6 @@ ...@@ -44,9 +44,6 @@
#include <rte_memzone.h> #include <rte_memzone.h>
#include <linux/pci.h> #include <linux/pci.h>
#include "qdma_user.h" #include "qdma_user.h"
#include "qdma_soft_reg.h"
#include "eqdma_soft_reg.h"
#include "qdma_s80_hard_reg.h"
#include "qdma_resource_mgmt.h" #include "qdma_resource_mgmt.h"
#include "qdma_mbox.h" #include "qdma_mbox.h"
#include "rte_pmd_qdma.h" #include "rte_pmd_qdma.h"
...@@ -84,6 +81,8 @@ ...@@ -84,6 +81,8 @@
#define RESET_TIMEOUT (60000) #define RESET_TIMEOUT (60000)
#define SHUTDOWN_TIMEOUT (60000) #define SHUTDOWN_TIMEOUT (60000)
#define QDMA_MAX_BUFLEN (2048 * 10)
#ifdef spin_lock_init #ifdef spin_lock_init
#undef spin_lock_init #undef spin_lock_init
#endif #endif
......
QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef EQDMA_ACCESS_H_ #ifndef __EQDMA_SOFT_ACCESS_H_
#define EQDMA_ACCESS_H_ #define __EQDMA_SOFT_ACCESS_H_
#include "qdma_access_common.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "qdma_platform.h"
/** /**
* enum qdma_error_idx - qdma errors * enum qdma_error_idx - qdma errors
*/ */
...@@ -191,8 +207,18 @@ struct eqdma_hw_err_info { ...@@ -191,8 +207,18 @@ struct eqdma_hw_err_info {
uint32_t stat_reg_addr; uint32_t stat_reg_addr;
uint32_t leaf_err_mask; uint32_t leaf_err_mask;
uint32_t global_err_mask; uint32_t global_err_mask;
void (*eqdma_hw_err_process)(void *dev_hndl);
}; };
#define EQDMA_OFFSET_VF_VERSION 0x5014
#define EQDMA_OFFSET_VF_USER_BAR 0x5018
#define EQDMA_OFFSET_MBOX_BASE_PF 0x22400
#define EQDMA_OFFSET_MBOX_BASE_VF 0x5000
#define EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38)
#define EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6)
#define EQDMA_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2)
int eqdma_init_ctxt_memory(void *dev_hndl); int eqdma_init_ctxt_memory(void *dev_hndl);
...@@ -259,19 +285,38 @@ int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, ...@@ -259,19 +285,38 @@ int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf,
uint8_t func_id, uint8_t *user_bar); uint8_t func_id, uint8_t *user_bar);
int eqdma_dump_config_reg_list(void *dev_hndl, int eqdma_dump_config_reg_list(void *dev_hndl,
uint32_t num_regs, uint32_t total_regs,
struct qdma_reg_data *reg_list, struct qdma_reg_data *reg_list,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf,
uint16_t reg_rd_slot, uint16_t reg_rd_group,
uint16_t *total_regs, uint16_t *total_regs,
struct qdma_reg_data *reg_list); struct qdma_reg_data *reg_list);
int eqdma_set_default_global_csr(void *dev_hndl); int eqdma_set_default_global_csr(void *dev_hndl);
int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count,
uint32_t *csr_val,
enum qdma_global_csr_type csr_type,
enum qdma_hw_access_type access_type);
int eqdma_global_writeback_interval_conf(void *dev_hndl,
enum qdma_wrb_interval *wb_int,
enum qdma_hw_access_type access_type);
int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h,
uint8_t enable);
int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr,
uint32_t num_regs, char *buf, uint32_t buflen);
uint32_t eqdma_get_config_num_regs(void);
struct xreg_info *eqdma_get_config_regs(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* EQDMA_ACCESS_H_ */ #endif /* __EQDMA_SOFT_ACCESS_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_ACCESS_COMMON_H_ #ifndef __QDMA_ACCESS_COMMON_H_
#define QDMA_ACCESS_COMMON_H_ #define __QDMA_ACCESS_COMMON_H_
#include "qdma_access_export.h"
#include "qdma_access_errors.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "qdma_access_export.h"
#include "qdma_access_errors.h"
/* QDMA HW version string array length */ /* QDMA HW version string array length */
#define QDMA_HW_VERSION_STRING_LEN 32 #define QDMA_HW_VERSION_STRING_LEN 32
#define ENABLE_INIT_CTXT_MEMORY 1 #define ENABLE_INIT_CTXT_MEMORY 1
#ifdef GCC_COMPILER
static inline uint32_t get_trailing_zeros(uint64_t x)
{
uint32_t rv =
__builtin_ffsll(x) - 1;
return rv;
}
#else
static inline uint32_t get_trailing_zeros(uint64_t value)
{
uint32_t pos = 0;
if ((value & 0xffffffff) == 0) {
pos += 32;
value >>= 32;
}
if ((value & 0xffff) == 0) {
pos += 16;
value >>= 16;
}
if ((value & 0xff) == 0) {
pos += 8;
value >>= 8;
}
if ((value & 0xf) == 0) {
pos += 4;
value >>= 4;
}
if ((value & 0x3) == 0) {
pos += 2;
value >>= 2;
}
if ((value & 0x1) == 0)
pos += 1;
return pos;
}
#endif
#define FIELD_SHIFT(mask) get_trailing_zeros(mask)
#define FIELD_SET(mask, val) ((val << FIELD_SHIFT(mask)) & mask)
#define FIELD_GET(mask, reg) ((reg & mask) >> FIELD_SHIFT(mask))
/* CSR Default values */ /* CSR Default values */
#define DEFAULT_MAX_DSC_FETCH 6 #define DEFAULT_MAX_DSC_FETCH 6
#define DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 #define DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128
...@@ -50,6 +110,66 @@ extern "C" { ...@@ -50,6 +110,66 @@ extern "C" {
*/ */
#define QDMA_NUM_DATA_VEC_FOR_INTR_CXT 1 #define QDMA_NUM_DATA_VEC_FOR_INTR_CXT 1
enum ind_ctxt_cmd_op {
QDMA_CTXT_CMD_CLR,
QDMA_CTXT_CMD_WR,
QDMA_CTXT_CMD_RD,
QDMA_CTXT_CMD_INV
};
enum ind_ctxt_cmd_sel {
QDMA_CTXT_SEL_SW_C2H,
QDMA_CTXT_SEL_SW_H2C,
QDMA_CTXT_SEL_HW_C2H,
QDMA_CTXT_SEL_HW_H2C,
QDMA_CTXT_SEL_CR_C2H,
QDMA_CTXT_SEL_CR_H2C,
QDMA_CTXT_SEL_CMPT,
QDMA_CTXT_SEL_PFTCH,
QDMA_CTXT_SEL_INT_COAL,
QDMA_CTXT_SEL_PASID_RAM_LOW,
QDMA_CTXT_SEL_PASID_RAM_HIGH,
QDMA_CTXT_SEL_TIMER,
QDMA_CTXT_SEL_FMAP,
};
/* polling a register */
#define QDMA_REG_POLL_DFLT_INTERVAL_US 10 /* 10us per poll */
#define QDMA_REG_POLL_DFLT_TIMEOUT_US (500*1000) /* 500ms */
/** Constants */
#define QDMA_NUM_RING_SIZES 16
#define QDMA_NUM_C2H_TIMERS 16
#define QDMA_NUM_C2H_BUFFER_SIZES 16
#define QDMA_NUM_C2H_COUNTERS 16
#define QDMA_MM_CONTROL_RUN 0x1
#define QDMA_MM_CONTROL_STEP 0x100
#define QDMA_MAGIC_NUMBER 0x1fd3
#define QDMA_PIDX_STEP 0x10
#define QDMA_CMPT_CIDX_STEP 0x10
#define QDMA_INT_CIDX_STEP 0x10
/** QDMA_IND_REG_SEL_PFTCH */
#define QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK GENMASK(15, 3)
#define QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK GENMASK(2, 0)
/** QDMA_IND_REG_SEL_CMPT */
#define QDMA_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 38)
#define QDMA_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(37, 12)
#define QDMA_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 4)
#define QDMA_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(3, 0)
#define QDMA_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 61)
#define QDMA_INTR_CTXT_BADDR_GET_M_MASK GENMASK_ULL(60, 29)
#define QDMA_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(28, 12)
#define QDMA_GLBL2_MM_CMPT_EN_MASK BIT(2)
#define QDMA_GLBL2_FLR_PRESENT_MASK BIT(1)
#define QDMA_GLBL2_MAILBOX_EN_MASK BIT(0)
#define QDMA_REG_IND_CTXT_REG_COUNT 8
/* ------------------------ indirect register context fields -----------*/ /* ------------------------ indirect register context fields -----------*/
union qdma_ind_ctxt_cmd { union qdma_ind_ctxt_cmd {
uint32_t word; uint32_t word;
...@@ -294,8 +414,6 @@ struct qdma_descq_cmpt_ctxt { ...@@ -294,8 +414,6 @@ struct qdma_descq_cmpt_ctxt {
uint32_t pasid; uint32_t pasid;
/** @pasid_en - PASID Enable */ /** @pasid_en - PASID Enable */
uint8_t pasid_en; uint8_t pasid_en;
/** @virtio_dsc_base - Virtio Desc Base Address */
uint8_t base_addr;
/** @vio_eop - Virtio End-of-packet */ /** @vio_eop - Virtio End-of-packet */
uint8_t vio_eop; uint8_t vio_eop;
/** @sh_cmpt - Shared Completion Queue */ /** @sh_cmpt - Shared Completion Queue */
...@@ -518,11 +636,16 @@ void qdma_memset(void *to, uint8_t val, uint32_t size); ...@@ -518,11 +636,16 @@ void qdma_memset(void *to, uint8_t val, uint32_t size);
int qdma_acc_reg_dump_buf_len(void *dev_hndl, int qdma_acc_reg_dump_buf_len(void *dev_hndl,
enum qdma_ip_type ip_type, int *buflen); enum qdma_ip_type ip_type, int *buflen);
int qdma_acc_reg_info_len(void *dev_hndl,
enum qdma_ip_type ip_type, int *buflen, int *num_regs);
int qdma_acc_context_buf_len(void *dev_hndl, int qdma_acc_context_buf_len(void *dev_hndl,
enum qdma_ip_type ip_type, uint8_t st, enum qdma_ip_type ip_type, uint8_t st,
enum qdma_dev_q_type q_type, uint32_t *buflen); enum qdma_dev_q_type q_type, uint32_t *buflen);
int qdma_acc_get_num_config_regs(void *dev_hndl,
enum qdma_ip_type ip_type, uint32_t *num_regs);
/* /*
* struct qdma_hw_access - Structure to hold HW access function pointers * struct qdma_hw_access - Structure to hold HW access function pointers
*/ */
...@@ -592,6 +715,10 @@ struct qdma_hw_access { ...@@ -592,6 +715,10 @@ struct qdma_hw_access {
int (*qdma_hw_error_process)(void *dev_hndl); int (*qdma_hw_error_process)(void *dev_hndl);
int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf, int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf,
uint32_t buflen); uint32_t buflen);
int (*qdma_dump_reg_info)(void *dev_hndl, uint32_t reg_addr,
uint32_t num_regs,
char *buf,
uint32_t buflen);
int (*qdma_dump_queue_context)(void *dev_hndl, int (*qdma_dump_queue_context)(void *dev_hndl,
uint8_t st, uint8_t st,
enum qdma_dev_q_type q_type, enum qdma_dev_q_type q_type,
...@@ -622,6 +749,7 @@ struct qdma_hw_access { ...@@ -622,6 +749,7 @@ struct qdma_hw_access {
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
uint32_t mbox_base_pf; uint32_t mbox_base_pf;
uint32_t mbox_base_vf; uint32_t mbox_base_vf;
uint32_t qdma_max_errors;
}; };
/*****************************************************************************/ /*****************************************************************************/
...@@ -643,6 +771,21 @@ struct qdma_hw_access { ...@@ -643,6 +771,21 @@ struct qdma_hw_access {
int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf,
struct qdma_hw_access *hw_access); struct qdma_hw_access *hw_access);
/*****************************************************************************/
/**
* qdma_acc_dump_config_regs() - Function to get qdma config registers
*
* @dev_hndl: device handle
* @is_vf: Whether PF or VF
* @ip_type: QDMA IP Type
* @reg_data: pointer to register data to be filled
*
* Return: Length up-till the buffer is filled -success and < 0 - failure
*****************************************************************************/
int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf,
enum qdma_ip_type ip_type,
uint32_t *reg_data);
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_acc_dump_config_regs() - Function to get qdma config register dump in a * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a
...@@ -660,6 +803,23 @@ int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, ...@@ -660,6 +803,23 @@ int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf,
enum qdma_ip_type ip_type, enum qdma_ip_type ip_type,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
/*****************************************************************************/
/**
* qdma_acc_dump_reg_info() - Function to get qdma reg info in a buffer
*
* @dev_hndl: device handle
* @ip_type: QDMA IP Type
* @reg_addr: Register Address
* @num_regs: Number of Registers
* @buf : pointer to buffer to be filled
* @buflen : Length of the buffer
*
* Return: Length up-till the buffer is filled -success and < 0 - failure
*****************************************************************************/
int qdma_acc_dump_reg_info(void *dev_hndl,
enum qdma_ip_type ip_type, uint32_t reg_addr,
uint32_t num_regs, char *buf, uint32_t buflen);
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_acc_dump_queue_context() - Function to dump qdma queue context data in a * qdma_acc_dump_queue_context() - Function to dump qdma queue context data in a
......
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_ACCESS_ERRORS_H_ #ifndef __QDMA_ACCESS_ERRORS_H_
#define QDMA_ACCESS_ERRORS_H_ #define __QDMA_ACCESS_ERRORS_H_
#ifdef __cplusplus
extern "C" {
#endif
/** /**
* DOC: QDMA common library error codes definitions * DOC: QDMA common library error codes definitions
...@@ -62,4 +81,8 @@ enum qdma_access_error_codes { ...@@ -62,4 +81,8 @@ enum qdma_access_error_codes {
QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 25 */ QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 25 */
}; };
#endif /* QDMA_ACCESS_H_ */ #ifdef __cplusplus
}
#endif
#endif /* __QDMA_ACCESS_ERRORS_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_ACCESS_EXPORT_H_ #ifndef __QDMA_ACCESS_EXPORT_H_
#define QDMA_ACCESS_EXPORT_H_ #define __QDMA_ACCESS_EXPORT_H_
#include "qdma_platform_env.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "qdma_platform_env.h"
/** QDMA Global CSR array size */ /** QDMA Global CSR array size */
#define QDMA_GLOBAL_CSR_ARRAY_SZ 16 #define QDMA_GLOBAL_CSR_ARRAY_SZ 16
...@@ -44,6 +60,12 @@ struct qdma_dev_attributes { ...@@ -44,6 +60,12 @@ struct qdma_dev_attributes {
uint8_t mm_cmpt_en:1; uint8_t mm_cmpt_en:1;
/** @mailbox_en - Mailbox supported or not? */ /** @mailbox_en - Mailbox supported or not? */
uint8_t mailbox_en:1; uint8_t mailbox_en:1;
/** @debug_mode - Debug mode is enabled/disabled for IP */
uint8_t debug_mode:1;
/** @desc_eng_mode - Descriptor Engine mode:
* Internal only/Bypass only/Internal & Bypass
*/
uint8_t desc_eng_mode:2;
/** @mm_channel_max - Num of MM channels */ /** @mm_channel_max - Num of MM channels */
uint8_t mm_channel_max; uint8_t mm_channel_max;
...@@ -202,6 +224,8 @@ enum qdma_vivado_release_id { ...@@ -202,6 +224,8 @@ enum qdma_vivado_release_id {
QDMA_VIVADO_2019_2, QDMA_VIVADO_2019_2,
/** @QDMA_VIVADO_2020_1 - Vivado version 2020.1 */ /** @QDMA_VIVADO_2020_1 - Vivado version 2020.1 */
QDMA_VIVADO_2020_1, QDMA_VIVADO_2020_1,
/** @QDMA_VIVADO_2020_2 - Vivado version 2020.2 */
QDMA_VIVADO_2020_2,
/** @QDMA_VIVADO_NONE - Not a valid Vivado version*/ /** @QDMA_VIVADO_NONE - Not a valid Vivado version*/
QDMA_VIVADO_NONE QDMA_VIVADO_NONE
}; };
...@@ -229,137 +253,19 @@ enum qdma_device_type { ...@@ -229,137 +253,19 @@ enum qdma_device_type {
QDMA_DEVICE_NONE QDMA_DEVICE_NONE
}; };
/** enum qdma_desc_eng_mode {
* enum qdma_error_idx - qdma errors /** @QDMA_DESC_ENG_INTERNAL_BYPASS - Internal and Bypass mode */
*/ QDMA_DESC_ENG_INTERNAL_BYPASS,
enum qdma_error_idx { /** @QDMA_DESC_ENG_BYPASS_ONLY - Only Bypass mode */
/* Descriptor errors */ QDMA_DESC_ENG_BYPASS_ONLY,
QDMA_DSC_ERR_POISON, /** @QDMA_DESC_ENG_INTERNAL_ONLY - Only Internal mode */
QDMA_DSC_ERR_UR_CA, QDMA_DESC_ENG_INTERNAL_ONLY,
QDMA_DSC_ERR_PARAM, /** @QDMA_DESC_ENG_MODE_MAX - Max of desc engine modes */
QDMA_DSC_ERR_ADDR, QDMA_DESC_ENG_MODE_MAX
QDMA_DSC_ERR_TAG,
QDMA_DSC_ERR_FLR,
QDMA_DSC_ERR_TIMEOUT,
QDMA_DSC_ERR_DAT_POISON,
QDMA_DSC_ERR_FLR_CANCEL,
QDMA_DSC_ERR_DMA,
QDMA_DSC_ERR_DSC,
QDMA_DSC_ERR_RQ_CANCEL,
QDMA_DSC_ERR_DBE,
QDMA_DSC_ERR_SBE,
QDMA_DSC_ERR_ALL,
/* TRQ Errors */
QDMA_TRQ_ERR_UNMAPPED,
QDMA_TRQ_ERR_QID_RANGE,
QDMA_TRQ_ERR_VF_ACCESS,
QDMA_TRQ_ERR_TCP_TIMEOUT,
QDMA_TRQ_ERR_ALL,
/* C2H Errors */
QDMA_ST_C2H_ERR_MTY_MISMATCH,
QDMA_ST_C2H_ERR_LEN_MISMATCH,
QDMA_ST_C2H_ERR_QID_MISMATCH,
QDMA_ST_C2H_ERR_DESC_RSP_ERR,
QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
QDMA_ST_C2H_ERR_MSI_INT_FAIL,
QDMA_ST_C2H_ERR_ERR_DESC_CNT,
QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH,
QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR,
QDMA_ST_C2H_ERR_CMPT_QFULL_ERR,
QDMA_ST_C2H_ERR_CMPT_CIDX_ERR,
QDMA_ST_C2H_ERR_CMPT_PRTY_ERR,
QDMA_ST_C2H_ERR_ALL,
/* Fatal Errors */
QDMA_ST_FATAL_ERR_MTY_MISMATCH,
QDMA_ST_FATAL_ERR_LEN_MISMATCH,
QDMA_ST_FATAL_ERR_QID_MISMATCH,
QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE,
QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_WPL_DATA_PAR,
QDMA_ST_FATAL_ERR_ALL,
/* H2C Errors */
QDMA_ST_H2C_ERR_ZERO_LEN_DESC,
QDMA_ST_H2C_ERR_CSI_MOP,
QDMA_ST_H2C_ERR_NO_DMA_DSC,
QDMA_ST_H2C_ERR_SBE,
QDMA_ST_H2C_ERR_DBE,
QDMA_ST_H2C_ERR_ALL,
/* Single bit errors */
QDMA_SBE_ERR_MI_H2C0_DAT,
QDMA_SBE_ERR_MI_C2H0_DAT,
QDMA_SBE_ERR_H2C_RD_BRG_DAT,
QDMA_SBE_ERR_H2C_WR_BRG_DAT,
QDMA_SBE_ERR_C2H_RD_BRG_DAT,
QDMA_SBE_ERR_C2H_WR_BRG_DAT,
QDMA_SBE_ERR_FUNC_MAP,
QDMA_SBE_ERR_DSC_HW_CTXT,
QDMA_SBE_ERR_DSC_CRD_RCV,
QDMA_SBE_ERR_DSC_SW_CTXT,
QDMA_SBE_ERR_DSC_CPLI,
QDMA_SBE_ERR_DSC_CPLD,
QDMA_SBE_ERR_PASID_CTXT_RAM,
QDMA_SBE_ERR_TIMER_FIFO_RAM,
QDMA_SBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_SBE_ERR_QID_FIFO_RAM,
QDMA_SBE_ERR_TUSER_FIFO_RAM,
QDMA_SBE_ERR_WRB_COAL_DATA_RAM,
QDMA_SBE_ERR_INT_QID2VEC_RAM,
QDMA_SBE_ERR_INT_CTXT_RAM,
QDMA_SBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_SBE_ERR_PFCH_CTXT_RAM,
QDMA_SBE_ERR_WRB_CTXT_RAM,
QDMA_SBE_ERR_PFCH_LL_RAM,
QDMA_SBE_ERR_H2C_PEND_FIFO,
QDMA_SBE_ERR_ALL,
/* Double bit Errors */
QDMA_DBE_ERR_MI_H2C0_DAT,
QDMA_DBE_ERR_MI_C2H0_DAT,
QDMA_DBE_ERR_H2C_RD_BRG_DAT,
QDMA_DBE_ERR_H2C_WR_BRG_DAT,
QDMA_DBE_ERR_C2H_RD_BRG_DAT,
QDMA_DBE_ERR_C2H_WR_BRG_DAT,
QDMA_DBE_ERR_FUNC_MAP,
QDMA_DBE_ERR_DSC_HW_CTXT,
QDMA_DBE_ERR_DSC_CRD_RCV,
QDMA_DBE_ERR_DSC_SW_CTXT,
QDMA_DBE_ERR_DSC_CPLI,
QDMA_DBE_ERR_DSC_CPLD,
QDMA_DBE_ERR_PASID_CTXT_RAM,
QDMA_DBE_ERR_TIMER_FIFO_RAM,
QDMA_DBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_DBE_ERR_QID_FIFO_RAM,
QDMA_DBE_ERR_TUSER_FIFO_RAM,
QDMA_DBE_ERR_WRB_COAL_DATA_RAM,
QDMA_DBE_ERR_INT_QID2VEC_RAM,
QDMA_DBE_ERR_INT_CTXT_RAM,
QDMA_DBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_DBE_ERR_PFCH_CTXT_RAM,
QDMA_DBE_ERR_WRB_CTXT_RAM,
QDMA_DBE_ERR_PFCH_LL_RAM,
QDMA_DBE_ERR_H2C_PEND_FIFO,
QDMA_DBE_ERR_ALL,
QDMA_ERRS_ALL
}; };
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* QDMA_ACCESS_EXPORT_H_ */ #endif /* __QDMA_ACCESS_EXPORT_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_VERSION_H_ #ifndef __QDMA_ACCESS_VERSION_H_
#define QDMA_VERSION_H_ #define __QDMA_ACCESS_VERSION_H_
#define QDMA_VERSION_MAJOR 2020 #define QDMA_VERSION_MAJOR 2020
#define QDMA_VERSION_MINOR 1 #define QDMA_VERSION_MINOR 2
#define QDMA_VERSION_PATCH 1 #define QDMA_VERSION_PATCH 0
#define QDMA_VERSION_STR \ #define QDMA_VERSION_STR \
__stringify(QDMA_VERSION_MAJOR) "." \ __stringify(QDMA_VERSION_MAJOR) "." \
...@@ -33,4 +49,4 @@ ...@@ -33,4 +49,4 @@
QDMA_VERSION_PATCH) QDMA_VERSION_PATCH)
#endif /* COMMON_QDMA_VERSION_H_ */ #endif /* __QDMA_ACCESS_VERSION_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "qdma_list.h" #include "qdma_list.h"
......
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License, *
* version 2, as published by the Free Software Foundation. * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* This program is distributed in the hope that it will be useful, but WITHOUT * are met:
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * * Redistributions of source code must retain the above copyright
* more details. * notice, this list of conditions and the following disclaimer.
* * * Redistributions in binary form must reproduce the above copyright
* The full GNU General Public License is included in this distribution in * notice, this list of conditions and the following disclaimer in
* the file called "COPYING". * the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_LIST_H_ #ifndef __QDMA_LIST_H_
#define QDMA_LIST_H_ #define __QDMA_LIST_H_
#ifdef __cplusplus
extern "C" {
#endif
/** /**
* DOC: QDMA common library provided list implementation definitions * DOC: QDMA common library provided list implementation definitions
...@@ -114,4 +134,8 @@ void qdma_list_insert_after(struct qdma_list_head *new_node, ...@@ -114,4 +134,8 @@ void qdma_list_insert_after(struct qdma_list_head *new_node,
*****************************************************************************/ *****************************************************************************/
void qdma_list_del(struct qdma_list_head *node); void qdma_list_del(struct qdma_list_head *node);
#endif /* QDMA_LIST_H_ */ #ifdef __cplusplus
}
#endif
#endif /* __QDMA_LIST_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "qdma_mbox_protocol.h" #include "qdma_mbox_protocol.h"
#include "qdma_platform.h"
#include "qdma_resource_mgmt.h"
/** mailbox function status */ /** mailbox function status */
#define MBOX_FN_STATUS 0x0 #define MBOX_FN_STATUS 0x0
...@@ -381,9 +395,9 @@ static inline void mbox_pf_hw_clear_func_ack(void *dev_hndl, uint16_t func_id) ...@@ -381,9 +395,9 @@ static inline void mbox_pf_hw_clear_func_ack(void *dev_hndl, uint16_t func_id)
(1 << bit)); (1 << bit));
} }
static void qdma_mbox_memcpy(void *to, void *from, uint32_t size) static void qdma_mbox_memcpy(void *to, void *from, uint8_t size)
{ {
uint32_t i; uint8_t i;
uint8_t *_to = (uint8_t *)to; uint8_t *_to = (uint8_t *)to;
uint8_t *_from = (uint8_t *)from; uint8_t *_from = (uint8_t *)from;
...@@ -391,9 +405,9 @@ static void qdma_mbox_memcpy(void *to, void *from, uint32_t size) ...@@ -391,9 +405,9 @@ static void qdma_mbox_memcpy(void *to, void *from, uint32_t size)
_to[i] = _from[i]; _to[i] = _from[i];
} }
static void qdma_mbox_memset(void *to, uint8_t val, uint32_t size) static void qdma_mbox_memset(void *to, uint8_t val, uint8_t size)
{ {
uint32_t i; uint8_t i;
uint8_t *_to = (uint8_t *)to; uint8_t *_to = (uint8_t *)to;
for (i = 0; i < size; i++) for (i = 0; i < size; i++)
...@@ -1079,7 +1093,7 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, ...@@ -1079,7 +1093,7 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index,
case MBOX_OP_CSR: case MBOX_OP_CSR:
{ {
struct mbox_msg_csr *rsp_csr = &resp->csr; struct mbox_msg_csr *rsp_csr = &resp->csr;
struct qdma_dev_attributes *dev_cap; struct qdma_dev_attributes dev_cap;
uint32_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; uint32_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
uint32_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; uint32_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
...@@ -1093,9 +1107,9 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, ...@@ -1093,9 +1107,9 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index,
if (rv < 0) if (rv < 0)
goto exit_func; goto exit_func;
qdma_get_device_attr(dev_hndl, &dev_cap); hw->qdma_get_device_attributes(dev_hndl, &dev_cap);
if (dev_cap->st_en) { if (dev_cap.st_en) {
rv = hw->qdma_global_csr_conf(dev_hndl, 0, rv = hw->qdma_global_csr_conf(dev_hndl, 0,
QDMA_GLOBAL_CSR_ARRAY_SZ, bufsz, QDMA_GLOBAL_CSR_ARRAY_SZ, bufsz,
QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ);
...@@ -1104,7 +1118,7 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, ...@@ -1104,7 +1118,7 @@ int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index,
goto exit_func; goto exit_func;
} }
if (dev_cap->st_en || dev_cap->mm_cmpt_en) { if (dev_cap.st_en || dev_cap.mm_cmpt_en) {
rv = hw->qdma_global_csr_conf(dev_hndl, 0, rv = hw->qdma_global_csr_conf(dev_hndl, 0,
QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th, QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th,
QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ);
......
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License, *
* version 2, as published by the Free Software Foundation. * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* This program is distributed in the hope that it will be useful, but WITHOUT * are met:
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * * Redistributions of source code must retain the above copyright
* more details. * notice, this list of conditions and the following disclaimer.
* * * Redistributions in binary form must reproduce the above copyright
* The full GNU General Public License is included in this distribution in * notice, this list of conditions and the following disclaimer in
* the file called "COPYING". * the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_MBOX_PROTOCOL_H_ #ifndef __QDMA_MBOX_PROTOCOL_H_
#define QDMA_MBOX_PROTOCOL_H_ #define __QDMA_MBOX_PROTOCOL_H_
#ifdef __cplusplus
extern "C" {
#endif
/** /**
* DOC: QDMA message box handling interface definitions * DOC: QDMA message box handling interface definitions
...@@ -24,10 +44,10 @@ ...@@ -24,10 +44,10 @@
* signatures exported for QDMA Mbox message handling. * signatures exported for QDMA Mbox message handling.
*/ */
#include "qdma_platform_env.h" #include "qdma_platform.h"
#include "qdma_access_common.h"
#include "qdma_resource_mgmt.h" #include "qdma_resource_mgmt.h"
#define QDMA_MBOX_VF_ONLINE (1) #define QDMA_MBOX_VF_ONLINE (1)
#define QDMA_MBOX_VF_OFFLINE (-1) #define QDMA_MBOX_VF_OFFLINE (-1)
#define QDMA_MBOX_VF_RESET (2) #define QDMA_MBOX_VF_RESET (2)
...@@ -154,7 +174,7 @@ void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf); ...@@ -154,7 +174,7 @@ void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf);
/** /**
* qdma_mbox_pf_rcv_msg_handler(): handles the raw message received in pf * qdma_mbox_pf_rcv_msg_handler(): handles the raw message received in pf
* *
* @pci_bus_num: pci bus number * @dma_device_index: pci bus number
* @dev_hndl: device handle * @dev_hndl: device handle
* @func_id: own function id * @func_id: own function id
* @rcv_msg: received raw message * @rcv_msg: received raw message
...@@ -162,7 +182,7 @@ void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf); ...@@ -162,7 +182,7 @@ void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf);
* *
* Return: 0 : success and < 0: failure * Return: 0 : success and < 0: failure
*****************************************************************************/ *****************************************************************************/
int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t pci_bus_num, int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index,
uint16_t func_id, uint32_t *rcv_msg, uint16_t func_id, uint32_t *rcv_msg,
uint32_t *resp_msg); uint32_t *resp_msg);
...@@ -683,4 +703,8 @@ int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg); ...@@ -683,4 +703,8 @@ int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg);
*****************************************************************************/ *****************************************************************************/
uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf); uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf);
#endif /* QDMA_MBOX_PROTOCOL_H_ */ #ifdef __cplusplus
}
#endif
#endif /* __QDMA_MBOX_PROTOCOL_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License, *
* version 2, as published by the Free Software Foundation. * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* This program is distributed in the hope that it will be useful, but WITHOUT * are met:
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * * Redistributions of source code must retain the above copyright
* more details. * notice, this list of conditions and the following disclaimer.
* * * Redistributions in binary form must reproduce the above copyright
* The full GNU General Public License is included in this distribution in * notice, this list of conditions and the following disclaimer in
* the file called "COPYING". * the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef LIBQDMA_QDMA_PLATFORM_H_ #ifndef __QDMA_PLATFORM_H_
#define LIBQDMA_QDMA_PLATFORM_H_ #define __QDMA_PLATFORM_H_
#include "qdma_access_common.h"
#include "qdma_platform_env.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
...@@ -31,6 +44,8 @@ extern "C" { ...@@ -31,6 +44,8 @@ extern "C" {
* required to be implemented by platform specific drivers. * required to be implemented by platform specific drivers.
*/ */
#include "qdma_access_common.h"
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_calloc(): allocate memory and initialize with 0 * qdma_calloc(): allocate memory and initialize with 0
...@@ -130,28 +145,6 @@ int qdma_reg_access_release(void *dev_hndl); ...@@ -130,28 +145,6 @@ int qdma_reg_access_release(void *dev_hndl);
*****************************************************************************/ *****************************************************************************/
void qdma_udelay(uint32_t delay_usec); void qdma_udelay(uint32_t delay_usec);
/*****************************************************************************/
/**
* qdma_hw_error_handler() - function to handle the hardware errors
*
* @dev_hndl: device handle
* @err_idx: error index
*
* Return: 0 - success and < 0 - failure
*****************************************************************************/
void qdma_hw_error_handler(void *dev_hndl, enum qdma_error_idx err_idx);
/*****************************************************************************/
/**
* qdma_get_device_attr() - function to get the device attributes
*
* @dev_hndl: device handle
* @dev_cap: pointer to hold the device capabilities
*
* Return: 0 - success and < 0 - failure
*****************************************************************************/
void qdma_get_device_attr(void *dev_hndl, struct qdma_dev_attributes **dev_cap);
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_get_hw_access() - function to get the qdma_hw_access * qdma_get_hw_access() - function to get the qdma_hw_access
...@@ -188,4 +181,4 @@ int qdma_get_err_code(int acc_err_code); ...@@ -188,4 +181,4 @@ int qdma_get_err_code(int acc_err_code);
} }
#endif #endif
#endif /* LIBQDMA_QDMA_PLATFORM_H_ */ #endif /* __QDMA_PLATFORM_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef __QDMA_REG_DUMP_H__ #ifndef __QDMA_REG_DUMP_H__
#define __QDMA_REG_DUMP_H__ #define __QDMA_REG_DUMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "qdma_platform_env.h" #include "qdma_platform_env.h"
#include "qdma_access_common.h" #include "qdma_access_common.h"
#define DEBUGFS_DEV_INFO_SZ (300) #define DEBUGFS_DEV_INFO_SZ (300)
#define QDMA_REG_NAME_LENGTH 64
#define DEBUGFS_INTR_CNTX_SZ (2048 * 2) #define DEBUGFS_INTR_CNTX_SZ (2048 * 2)
#define DBGFS_ERR_BUFLEN (64) #define DBGFS_ERR_BUFLEN (64)
#define DEBGFS_LINE_SZ (81) #define DEBGFS_LINE_SZ (81)
...@@ -50,19 +71,28 @@ ...@@ -50,19 +71,28 @@
(st_en << QDMA_ST_EN_SHIFT) | \ (st_en << QDMA_ST_EN_SHIFT) | \
(mailbox_en << QDMA_MAILBOX_EN_SHIFT)) (mailbox_en << QDMA_MAILBOX_EN_SHIFT))
struct regfield_info {
const char *field_name;
uint32_t field_mask;
};
struct xreg_info { struct xreg_info {
char name[32]; const char *name;
uint32_t addr; uint32_t addr;
uint32_t repeat; uint32_t repeat;
uint32_t step; uint32_t step;
uint8_t shift; uint8_t shift;
uint8_t len; uint8_t len;
uint8_t is_debug_reg;
uint8_t mode; uint8_t mode;
uint8_t read_type; uint8_t read_type;
uint8_t num_bitfields;
struct regfield_info *bitfields;
}; };
extern struct xreg_info qdma_config_regs[MAX_QDMA_CFG_REGS]; #ifdef __cplusplus
extern struct xreg_info qdma_cpm_config_regs[MAX_QDMA_CFG_REGS]; }
#endif
#endif #endif
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "qdma_resource_mgmt.h" #include "qdma_resource_mgmt.h"
......
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License, *
* version 2, as published by the Free Software Foundation. * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* This program is distributed in the hope that it will be useful, but WITHOUT * are met:
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * * Redistributions of source code must retain the above copyright
* more details. * notice, this list of conditions and the following disclaimer.
* * * Redistributions in binary form must reproduce the above copyright
* The full GNU General Public License is included in this distribution in * notice, this list of conditions and the following disclaimer in
* the file called "COPYING". * the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_RESOURCE_MGMT_H_ #ifndef __QDMA_RESOURCE_MGMT_H_
#define QDMA_RESOURCE_MGMT_H_ #define __QDMA_RESOURCE_MGMT_H_
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
...@@ -27,6 +43,7 @@ extern "C" { ...@@ -27,6 +43,7 @@ extern "C" {
* Header file *qdma_resource_mgmt.h* defines data structures and function * Header file *qdma_resource_mgmt.h* defines data structures and function
* signatures exported for QDMA queue management. * signatures exported for QDMA queue management.
*/ */
#include "qdma_platform_env.h" #include "qdma_platform_env.h"
#include "qdma_access_export.h" #include "qdma_access_export.h"
...@@ -209,4 +226,4 @@ int qdma_get_device_active_queue_count(uint32_t dma_device_index, ...@@ -209,4 +226,4 @@ int qdma_get_device_active_queue_count(uint32_t dma_device_index,
} }
#endif #endif
#endif /* LIBQDMA_QDMA_RESOURCE_MGMT_H_ */ #endif /* __QDMA_RESOURCE_MGMT_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_S80_HARD_ACCESS_H_ #ifndef __QDMA_S80_HARD_ACCESS_H_
#define QDMA_S80_HARD_ACCESS_H_ #define __QDMA_S80_HARD_ACCESS_H_
#include "qdma_access_common.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "qdma_platform.h"
/**
* enum qdma_error_idx - qdma errors
*/
enum qdma_s80_hard_error_idx {
/* Descriptor errors */
QDMA_S80_HARD_DSC_ERR_POISON,
QDMA_S80_HARD_DSC_ERR_UR_CA,
QDMA_S80_HARD_DSC_ERR_PARAM,
QDMA_S80_HARD_DSC_ERR_ADDR,
QDMA_S80_HARD_DSC_ERR_TAG,
QDMA_S80_HARD_DSC_ERR_FLR,
QDMA_S80_HARD_DSC_ERR_TIMEOUT,
QDMA_S80_HARD_DSC_ERR_DAT_POISON,
QDMA_S80_HARD_DSC_ERR_FLR_CANCEL,
QDMA_S80_HARD_DSC_ERR_DMA,
QDMA_S80_HARD_DSC_ERR_DSC,
QDMA_S80_HARD_DSC_ERR_RQ_CANCEL,
QDMA_S80_HARD_DSC_ERR_DBE,
QDMA_S80_HARD_DSC_ERR_SBE,
QDMA_S80_HARD_DSC_ERR_ALL,
/* TRQ Errors */
QDMA_S80_HARD_TRQ_ERR_UNMAPPED,
QDMA_S80_HARD_TRQ_ERR_QID_RANGE,
QDMA_S80_HARD_TRQ_ERR_VF_ACCESS_ERR,
QDMA_S80_HARD_TRQ_ERR_TCP_TIMEOUT,
QDMA_S80_HARD_TRQ_ERR_ALL,
/* C2H Errors */
QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH,
QDMA_S80_HARD_ST_C2H_ERR_LEN_MISMATCH,
QDMA_S80_HARD_ST_C2H_ERR_QID_MISMATCH,
QDMA_S80_HARD_ST_C2H_ERR_DESC_RSP_ERR,
QDMA_S80_HARD_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
QDMA_S80_HARD_ST_C2H_ERR_MSI_INT_FAIL,
QDMA_S80_HARD_ST_C2H_ERR_ERR_DESC_CNT,
QDMA_S80_HARD_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
QDMA_S80_HARD_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH,
QDMA_S80_HARD_ST_C2H_ERR_WRB_INV_Q_ERR,
QDMA_S80_HARD_ST_C2H_ERR_WRB_QFULL_ERR,
QDMA_S80_HARD_ST_C2H_ERR_WRB_CIDX_ERR,
QDMA_S80_HARD_ST_C2H_ERR_WRB_PRTY_ERR,
QDMA_S80_HARD_ST_C2H_ERR_ALL,
/* Fatal Errors */
QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH,
QDMA_S80_HARD_ST_FATAL_ERR_LEN_MISMATCH,
QDMA_S80_HARD_ST_FATAL_ERR_QID_MISMATCH,
QDMA_S80_HARD_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
QDMA_S80_HARD_ST_FATAL_ERR_WPL_DATA_PAR_ERR,
QDMA_S80_HARD_ST_FATAL_ERR_ALL,
/* H2C Errors */
QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR,
QDMA_S80_HARD_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR,
QDMA_S80_HARD_ST_H2C_ERR_NO_DMA_DSC,
QDMA_S80_HARD_ST_H2C_ERR_DBE,
QDMA_S80_HARD_ST_H2C_ERR_SBE,
QDMA_S80_HARD_ST_H2C_ERR_ALL,
/* Single bit errors */
QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT,
QDMA_S80_HARD_SBE_ERR_MI_C2H0_DAT,
QDMA_S80_HARD_SBE_ERR_H2C_RD_BRG_DAT,
QDMA_S80_HARD_SBE_ERR_H2C_WR_BRG_DAT,
QDMA_S80_HARD_SBE_ERR_C2H_RD_BRG_DAT,
QDMA_S80_HARD_SBE_ERR_C2H_WR_BRG_DAT,
QDMA_S80_HARD_SBE_ERR_FUNC_MAP,
QDMA_S80_HARD_SBE_ERR_DSC_HW_CTXT,
QDMA_S80_HARD_SBE_ERR_DSC_CRD_RCV,
QDMA_S80_HARD_SBE_ERR_DSC_SW_CTXT,
QDMA_S80_HARD_SBE_ERR_DSC_CPLI,
QDMA_S80_HARD_SBE_ERR_DSC_CPLD,
QDMA_S80_HARD_SBE_ERR_PASID_CTXT_RAM,
QDMA_S80_HARD_SBE_ERR_TIMER_FIFO_RAM,
QDMA_S80_HARD_SBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_S80_HARD_SBE_ERR_QID_FIFO_RAM,
QDMA_S80_HARD_SBE_ERR_TUSER_FIFO_RAM,
QDMA_S80_HARD_SBE_ERR_WRB_COAL_DATA_RAM,
QDMA_S80_HARD_SBE_ERR_INT_QID2VEC_RAM,
QDMA_S80_HARD_SBE_ERR_INT_CTXT_RAM,
QDMA_S80_HARD_SBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_S80_HARD_SBE_ERR_PFCH_CTXT_RAM,
QDMA_S80_HARD_SBE_ERR_WRB_CTXT_RAM,
QDMA_S80_HARD_SBE_ERR_PFCH_LL_RAM,
QDMA_S80_HARD_SBE_ERR_ALL,
/* Double bit Errors */
QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT,
QDMA_S80_HARD_DBE_ERR_MI_C2H0_DAT,
QDMA_S80_HARD_DBE_ERR_H2C_RD_BRG_DAT,
QDMA_S80_HARD_DBE_ERR_H2C_WR_BRG_DAT,
QDMA_S80_HARD_DBE_ERR_C2H_RD_BRG_DAT,
QDMA_S80_HARD_DBE_ERR_C2H_WR_BRG_DAT,
QDMA_S80_HARD_DBE_ERR_FUNC_MAP,
QDMA_S80_HARD_DBE_ERR_DSC_HW_CTXT,
QDMA_S80_HARD_DBE_ERR_DSC_CRD_RCV,
QDMA_S80_HARD_DBE_ERR_DSC_SW_CTXT,
QDMA_S80_HARD_DBE_ERR_DSC_CPLI,
QDMA_S80_HARD_DBE_ERR_DSC_CPLD,
QDMA_S80_HARD_DBE_ERR_PASID_CTXT_RAM,
QDMA_S80_HARD_DBE_ERR_TIMER_FIFO_RAM,
QDMA_S80_HARD_DBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_S80_HARD_DBE_ERR_QID_FIFO_RAM,
QDMA_S80_HARD_DBE_ERR_WRB_COAL_DATA_RAM,
QDMA_S80_HARD_DBE_ERR_INT_QID2VEC_RAM,
QDMA_S80_HARD_DBE_ERR_INT_CTXT_RAM,
QDMA_S80_HARD_DBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_S80_HARD_DBE_ERR_PFCH_CTXT_RAM,
QDMA_S80_HARD_DBE_ERR_WRB_CTXT_RAM,
QDMA_S80_HARD_DBE_ERR_PFCH_LL_RAM,
QDMA_S80_HARD_DBE_ERR_ALL,
QDMA_S80_HARD_ERRS_ALL
};
struct qdma_s80_hard_hw_err_info {
enum qdma_s80_hard_error_idx idx;
const char *err_name;
uint32_t mask_reg_addr;
uint32_t stat_reg_addr;
uint32_t leaf_err_mask;
uint32_t global_err_mask;
void (*qdma_s80_hard_hw_err_process)(void *dev_hndl);
};
int qdma_s80_hard_init_ctxt_memory(void *dev_hndl); int qdma_s80_hard_init_ctxt_memory(void *dev_hndl);
int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
...@@ -77,11 +230,15 @@ int qdma_s80_hard_get_device_attributes(void *dev_hndl, ...@@ -77,11 +230,15 @@ int qdma_s80_hard_get_device_attributes(void *dev_hndl,
uint32_t qdma_s80_hard_reg_dump_buf_len(void); uint32_t qdma_s80_hard_reg_dump_buf_len(void);
int qdma_s80_hard_context_buf_len(uint8_t st, int qdma_s80_hard_context_buf_len(uint8_t st,
enum qdma_dev_q_type q_type, uint32_t *buflen); enum qdma_dev_q_type q_type, uint32_t *req_buflen);
int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf, int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
int qdma_s80_hard_hw_error_process(void *dev_hndl);
const char *qdma_s80_hard_hw_get_error_name(uint32_t err_idx);
int qdma_s80_hard_hw_error_enable(void *dev_hndl, uint32_t err_idx);
int qdma_s80_hard_dump_queue_context(void *dev_hndl, int qdma_s80_hard_dump_queue_context(void *dev_hndl,
uint8_t st, uint8_t st,
enum qdma_dev_q_type q_type, enum qdma_dev_q_type q_type,
...@@ -100,17 +257,38 @@ int qdma_s80_hard_read_dump_queue_context(void *dev_hndl, ...@@ -100,17 +257,38 @@ int qdma_s80_hard_read_dump_queue_context(void *dev_hndl,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
int qdma_s80_hard_dump_config_reg_list(void *dev_hndl, int qdma_s80_hard_dump_config_reg_list(void *dev_hndl,
uint32_t num_regs, uint32_t total_regs,
struct qdma_reg_data *reg_list, struct qdma_reg_data *reg_list,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf, int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf,
uint16_t reg_rd_group, uint16_t reg_rd_slot,
uint16_t *total_regs, uint16_t *total_regs,
struct qdma_reg_data *reg_list); struct qdma_reg_data *reg_list);
int qdma_s80_hard_global_csr_conf(void *dev_hndl, uint8_t index,
uint8_t count,
uint32_t *csr_val,
enum qdma_global_csr_type csr_type,
enum qdma_hw_access_type access_type);
int qdma_s80_hard_global_writeback_interval_conf(void *dev_hndl,
enum qdma_wrb_interval *wb_int,
enum qdma_hw_access_type access_type);
int qdma_s80_hard_mm_channel_conf(void *dev_hndl, uint8_t channel,
uint8_t is_c2h,
uint8_t enable);
int qdma_s80_hard_dump_reg_info(void *dev_hndl, uint32_t reg_addr,
uint32_t num_regs, char *buf, uint32_t buflen);
uint32_t qdma_s80_hard_get_config_num_regs(void);
struct xreg_info *qdma_s80_hard_get_config_regs(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* QDMA_S80_HARD_ACCESS_H_ */ #endif /* __QDMA_S80_HARD_ACCESS_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_ACCESS_H_ #ifndef __QDMA_SOFT_ACCESS_H_
#define QDMA_ACCESS_H_ #define __QDMA_SOFT_ACCESS_H_
#include "qdma_access_export.h"
#include "qdma_platform_env.h"
#include "qdma_access_errors.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
...@@ -31,6 +44,136 @@ extern "C" { ...@@ -31,6 +44,136 @@ extern "C" {
* exported by QDMA common library. * exported by QDMA common library.
*/ */
#include "qdma_platform.h"
/**
* enum qdma_error_idx - qdma errors
*/
enum qdma_error_idx {
/* Descriptor errors */
QDMA_DSC_ERR_POISON,
QDMA_DSC_ERR_UR_CA,
QDMA_DSC_ERR_PARAM,
QDMA_DSC_ERR_ADDR,
QDMA_DSC_ERR_TAG,
QDMA_DSC_ERR_FLR,
QDMA_DSC_ERR_TIMEOUT,
QDMA_DSC_ERR_DAT_POISON,
QDMA_DSC_ERR_FLR_CANCEL,
QDMA_DSC_ERR_DMA,
QDMA_DSC_ERR_DSC,
QDMA_DSC_ERR_RQ_CANCEL,
QDMA_DSC_ERR_DBE,
QDMA_DSC_ERR_SBE,
QDMA_DSC_ERR_ALL,
/* TRQ Errors */
QDMA_TRQ_ERR_UNMAPPED,
QDMA_TRQ_ERR_QID_RANGE,
QDMA_TRQ_ERR_VF_ACCESS,
QDMA_TRQ_ERR_TCP_TIMEOUT,
QDMA_TRQ_ERR_ALL,
/* C2H Errors */
QDMA_ST_C2H_ERR_MTY_MISMATCH,
QDMA_ST_C2H_ERR_LEN_MISMATCH,
QDMA_ST_C2H_ERR_QID_MISMATCH,
QDMA_ST_C2H_ERR_DESC_RSP_ERR,
QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
QDMA_ST_C2H_ERR_MSI_INT_FAIL,
QDMA_ST_C2H_ERR_ERR_DESC_CNT,
QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH,
QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR,
QDMA_ST_C2H_ERR_CMPT_QFULL_ERR,
QDMA_ST_C2H_ERR_CMPT_CIDX_ERR,
QDMA_ST_C2H_ERR_CMPT_PRTY_ERR,
QDMA_ST_C2H_ERR_ALL,
/* Fatal Errors */
QDMA_ST_FATAL_ERR_MTY_MISMATCH,
QDMA_ST_FATAL_ERR_LEN_MISMATCH,
QDMA_ST_FATAL_ERR_QID_MISMATCH,
QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE,
QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
QDMA_ST_FATAL_ERR_WPL_DATA_PAR,
QDMA_ST_FATAL_ERR_ALL,
/* H2C Errors */
QDMA_ST_H2C_ERR_ZERO_LEN_DESC,
QDMA_ST_H2C_ERR_CSI_MOP,
QDMA_ST_H2C_ERR_NO_DMA_DSC,
QDMA_ST_H2C_ERR_SBE,
QDMA_ST_H2C_ERR_DBE,
QDMA_ST_H2C_ERR_ALL,
/* Single bit errors */
QDMA_SBE_ERR_MI_H2C0_DAT,
QDMA_SBE_ERR_MI_C2H0_DAT,
QDMA_SBE_ERR_H2C_RD_BRG_DAT,
QDMA_SBE_ERR_H2C_WR_BRG_DAT,
QDMA_SBE_ERR_C2H_RD_BRG_DAT,
QDMA_SBE_ERR_C2H_WR_BRG_DAT,
QDMA_SBE_ERR_FUNC_MAP,
QDMA_SBE_ERR_DSC_HW_CTXT,
QDMA_SBE_ERR_DSC_CRD_RCV,
QDMA_SBE_ERR_DSC_SW_CTXT,
QDMA_SBE_ERR_DSC_CPLI,
QDMA_SBE_ERR_DSC_CPLD,
QDMA_SBE_ERR_PASID_CTXT_RAM,
QDMA_SBE_ERR_TIMER_FIFO_RAM,
QDMA_SBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_SBE_ERR_QID_FIFO_RAM,
QDMA_SBE_ERR_TUSER_FIFO_RAM,
QDMA_SBE_ERR_WRB_COAL_DATA_RAM,
QDMA_SBE_ERR_INT_QID2VEC_RAM,
QDMA_SBE_ERR_INT_CTXT_RAM,
QDMA_SBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_SBE_ERR_PFCH_CTXT_RAM,
QDMA_SBE_ERR_WRB_CTXT_RAM,
QDMA_SBE_ERR_PFCH_LL_RAM,
QDMA_SBE_ERR_H2C_PEND_FIFO,
QDMA_SBE_ERR_ALL,
/* Double bit Errors */
QDMA_DBE_ERR_MI_H2C0_DAT,
QDMA_DBE_ERR_MI_C2H0_DAT,
QDMA_DBE_ERR_H2C_RD_BRG_DAT,
QDMA_DBE_ERR_H2C_WR_BRG_DAT,
QDMA_DBE_ERR_C2H_RD_BRG_DAT,
QDMA_DBE_ERR_C2H_WR_BRG_DAT,
QDMA_DBE_ERR_FUNC_MAP,
QDMA_DBE_ERR_DSC_HW_CTXT,
QDMA_DBE_ERR_DSC_CRD_RCV,
QDMA_DBE_ERR_DSC_SW_CTXT,
QDMA_DBE_ERR_DSC_CPLI,
QDMA_DBE_ERR_DSC_CPLD,
QDMA_DBE_ERR_PASID_CTXT_RAM,
QDMA_DBE_ERR_TIMER_FIFO_RAM,
QDMA_DBE_ERR_PAYLOAD_FIFO_RAM,
QDMA_DBE_ERR_QID_FIFO_RAM,
QDMA_DBE_ERR_TUSER_FIFO_RAM,
QDMA_DBE_ERR_WRB_COAL_DATA_RAM,
QDMA_DBE_ERR_INT_QID2VEC_RAM,
QDMA_DBE_ERR_INT_CTXT_RAM,
QDMA_DBE_ERR_DESC_REQ_FIFO_RAM,
QDMA_DBE_ERR_PFCH_CTXT_RAM,
QDMA_DBE_ERR_WRB_CTXT_RAM,
QDMA_DBE_ERR_PFCH_LL_RAM,
QDMA_DBE_ERR_H2C_PEND_FIFO,
QDMA_DBE_ERR_ALL,
QDMA_ERRS_ALL
};
struct qdma_hw_err_info { struct qdma_hw_err_info {
enum qdma_error_idx idx; enum qdma_error_idx idx;
const char *err_name; const char *err_name;
...@@ -38,6 +181,7 @@ struct qdma_hw_err_info { ...@@ -38,6 +181,7 @@ struct qdma_hw_err_info {
uint32_t stat_reg_addr; uint32_t stat_reg_addr;
uint32_t leaf_err_mask; uint32_t leaf_err_mask;
uint32_t global_err_mask; uint32_t global_err_mask;
void (*qdma_hw_err_process)(void *dev_hndl);
}; };
...@@ -98,6 +242,10 @@ int qdma_dump_intr_context(void *dev_hndl, ...@@ -98,6 +242,10 @@ int qdma_dump_intr_context(void *dev_hndl,
uint32_t qdma_soft_reg_dump_buf_len(void); uint32_t qdma_soft_reg_dump_buf_len(void);
uint32_t qdma_get_config_num_regs(void);
struct xreg_info *qdma_get_config_regs(void);
int qdma_soft_context_buf_len(uint8_t st, int qdma_soft_context_buf_len(uint8_t st,
enum qdma_dev_q_type q_type, uint32_t *buflen); enum qdma_dev_q_type q_type, uint32_t *buflen);
...@@ -129,7 +277,7 @@ int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, ...@@ -129,7 +277,7 @@ int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf,
uint8_t func_id, uint8_t *user_bar); uint8_t func_id, uint8_t *user_bar);
int qdma_soft_dump_config_reg_list(void *dev_hndl, int qdma_soft_dump_config_reg_list(void *dev_hndl,
uint32_t num_regs, uint32_t total_regs,
struct qdma_reg_data *reg_list, struct qdma_reg_data *reg_list,
char *buf, uint32_t buflen); char *buf, uint32_t buflen);
...@@ -138,9 +286,23 @@ int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, ...@@ -138,9 +286,23 @@ int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf,
uint16_t *total_regs, uint16_t *total_regs,
struct qdma_reg_data *reg_list); struct qdma_reg_data *reg_list);
int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count,
uint32_t *csr_val,
enum qdma_global_csr_type csr_type,
enum qdma_hw_access_type access_type);
int qdma_global_writeback_interval_conf(void *dev_hndl,
enum qdma_wrb_interval *wb_int,
enum qdma_hw_access_type access_type);
int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h,
uint8_t enable);
int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr,
uint32_t num_regs, char *buf, uint32_t buflen);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* QDMA_ACCESS_H_ */ #endif /* __QDMA_SOFT_ACCESS_H_ */
QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h
View file @ 00b6d04a
/* /*
* Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved. * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * BSD LICENSE
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * Redistribution and use in source and binary forms, with or without
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * modification, are permitted provided that the following conditions
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * are met:
* more details.
* *
* The full GNU General Public License is included in this distribution in * * Redistributions of source code must retain the above copyright
* the file called "COPYING". * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef QDMA_SOFT_REG_H__ #ifndef __QDMA_SOFT_REG_H__
#define QDMA_SOFT_REG_H__ #define __QDMA_SOFT_REG_H__
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
...@@ -65,56 +81,7 @@ extern "C" { ...@@ -65,56 +81,7 @@ extern "C" {
(0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h))))
/* #define DEBGFS_LINE_SZ (81)
* Returns the number of trailing 0s in x, starting at LSB.
* Same as gcc __builtin_ffsll function
*/
#ifdef GCC_COMPILER
static inline uint32_t get_trailing_zeros(uint64_t x)
{
uint32_t rv =
__builtin_ffsll(x) - 1;
return rv;
}
#else
static inline uint32_t get_trailing_zeros(uint64_t value)
{
uint32_t pos = 0;
if ((value & 0xffffffff) == 0) {
pos += 32;
value >>= 32;
}
if ((value & 0xffff) == 0) {
pos += 16;
value >>= 16;
}
if ((value & 0xff) == 0) {
pos += 8;
value >>= 8;
}
if ((value & 0xf) == 0) {
pos += 4;
value >>= 4;
}
if ((value & 0x3) == 0) {
pos += 2;
value >>= 2;
}
if ((value & 0x1) == 0)
pos += 1;
return pos;
}
#endif
#define FIELD_SHIFT(mask) get_trailing_zeros(mask)
#define FIELD_SET(mask, val) ((val << FIELD_SHIFT(mask)) & mask)
#define FIELD_GET(mask, reg) ((reg & mask) >> FIELD_SHIFT(mask))
/* polling a register */
#define QDMA_REG_POLL_DFLT_INTERVAL_US 10 /* 10us per poll */
#define QDMA_REG_POLL_DFLT_TIMEOUT_US (500*1000) /* 500ms */
#define QDMA_H2C_THROT_DATA_THRESH 0x4000 #define QDMA_H2C_THROT_DATA_THRESH 0x4000
...@@ -125,28 +92,6 @@ static inline uint32_t get_trailing_zeros(uint64_t value) ...@@ -125,28 +92,6 @@ static inline uint32_t get_trailing_zeros(uint64_t value)
/* /*
* Q Context programming (indirect) * Q Context programming (indirect)
*/ */
enum ind_ctxt_cmd_op {
QDMA_CTXT_CMD_CLR,
QDMA_CTXT_CMD_WR,
QDMA_CTXT_CMD_RD,
QDMA_CTXT_CMD_INV
};
enum ind_ctxt_cmd_sel {
QDMA_CTXT_SEL_SW_C2H,
QDMA_CTXT_SEL_SW_H2C,
QDMA_CTXT_SEL_HW_C2H,
QDMA_CTXT_SEL_HW_H2C,
QDMA_CTXT_SEL_CR_C2H,
QDMA_CTXT_SEL_CR_H2C,
QDMA_CTXT_SEL_CMPT,
QDMA_CTXT_SEL_PFTCH,
QDMA_CTXT_SEL_INT_COAL,
QDMA_CTXT_SEL_PASID_RAM_LOW,
QDMA_CTXT_SEL_PASID_RAM_HIGH,
QDMA_CTXT_SEL_TIMER,
QDMA_CTXT_SEL_FMAP,
};
#define QDMA_REG_IND_CTXT_REG_COUNT 8 #define QDMA_REG_IND_CTXT_REG_COUNT 8
#define QDMA_REG_IND_CTXT_WCNT_1 1 #define QDMA_REG_IND_CTXT_WCNT_1 1
...@@ -197,9 +142,7 @@ enum ind_ctxt_cmd_sel { ...@@ -197,9 +142,7 @@ enum ind_ctxt_cmd_sel {
#define QDMA_SW_CTXT_W0_IRQ_ARM_MASK BIT(16) #define QDMA_SW_CTXT_W0_IRQ_ARM_MASK BIT(16)
#define QDMA_SW_CTXT_W0_PIDX GENMASK(15, 0) #define QDMA_SW_CTXT_W0_PIDX GENMASK(15, 0)
/** QDMA_IND_REG_SEL_PFTCH */
#define QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK GENMASK(15, 3)
#define QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK GENMASK(2, 0)
#define QDMA_PFTCH_CTXT_W1_VALID_MASK BIT(13) #define QDMA_PFTCH_CTXT_W1_VALID_MASK BIT(13)
#define QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK GENMASK(12, 0) #define QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK GENMASK(12, 0)
...@@ -211,11 +154,8 @@ enum ind_ctxt_cmd_sel { ...@@ -211,11 +154,8 @@ enum ind_ctxt_cmd_sel {
#define QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) #define QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1)
#define QDMA_PFTCH_CTXT_W0_BYPASS_MASK BIT(0) #define QDMA_PFTCH_CTXT_W0_BYPASS_MASK BIT(0)
/** QDMA_IND_REG_SEL_CMPT */
#define QDMA_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 38)
#define QDMA_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(37, 12)
#define QDMA_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 4)
#define QDMA_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(3, 0)
#define QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK BIT(15) #define QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK BIT(15)
#define QDMA_COMPL_CTXT_W4_INTR_VEC_MASK GENMASK(14, 4) #define QDMA_COMPL_CTXT_W4_INTR_VEC_MASK GENMASK(14, 4)
...@@ -256,9 +196,7 @@ enum ind_ctxt_cmd_sel { ...@@ -256,9 +196,7 @@ enum ind_ctxt_cmd_sel {
#define QDMA_CR_CTXT_W0_CREDT_MASK GENMASK(15, 0) #define QDMA_CR_CTXT_W0_CREDT_MASK GENMASK(15, 0)
/** QDMA_IND_REG_SEL_INTR */ /** QDMA_IND_REG_SEL_INTR */
#define QDMA_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 61)
#define QDMA_INTR_CTXT_BADDR_GET_M_MASK GENMASK_ULL(60, 29)
#define QDMA_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(28, 12)
#define QDMA_INTR_CTXT_W2_AT_MASK BIT(18) #define QDMA_INTR_CTXT_W2_AT_MASK BIT(18)
#define QDMA_INTR_CTXT_W2_PIDX_MASK GENMASK(17, 6) #define QDMA_INTR_CTXT_W2_PIDX_MASK GENMASK(17, 6)
...@@ -271,17 +209,9 @@ enum ind_ctxt_cmd_sel { ...@@ -271,17 +209,9 @@ enum ind_ctxt_cmd_sel {
#define QDMA_INTR_CTXT_W0_VEC_ID_MASK GENMASK(11, 1) #define QDMA_INTR_CTXT_W0_VEC_ID_MASK GENMASK(11, 1)
#define QDMA_INTR_CTXT_W0_VALID_MASK BIT(0) #define QDMA_INTR_CTXT_W0_VALID_MASK BIT(0)
/** Constants */
#define QDMA_NUM_RING_SIZES 16
#define QDMA_NUM_C2H_TIMERS 16
#define QDMA_NUM_C2H_BUFFER_SIZES 16
#define QDMA_NUM_C2H_COUNTERS 16
#define QDMA_MM_CONTROL_RUN 0x1
#define QDMA_MM_CONTROL_STEP 0x100
#define QDMA_MAGIC_NUMBER 0x1fd3
#define QDMA_PIDX_STEP 0x10
#define QDMA_CMPT_CIDX_STEP 0x10
#define QDMA_INT_CIDX_STEP 0x10
/* ------------------------ QDMA_TRQ_SEL_GLBL (0x00200)-------------------*/ /* ------------------------ QDMA_TRQ_SEL_GLBL (0x00200)-------------------*/
#define QDMA_OFFSET_GLBL_RNG_SZ 0x204 #define QDMA_OFFSET_GLBL_RNG_SZ 0x204
...@@ -459,9 +389,7 @@ enum ind_ctxt_cmd_sel { ...@@ -459,9 +389,7 @@ enum ind_ctxt_cmd_sel {
#define QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET 0x12C #define QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET 0x12C
#define QDMA_OFFSET_GLBL2_SYSTEM_ID 0x130 #define QDMA_OFFSET_GLBL2_SYSTEM_ID 0x130
#define QDMA_OFFSET_GLBL2_MISC_CAP 0x134 #define QDMA_OFFSET_GLBL2_MISC_CAP 0x134
#define QDMA_GLBL2_MM_CMPT_EN_MASK BIT(2)
#define QDMA_GLBL2_FLR_PRESENT_MASK BIT(1)
#define QDMA_GLBL2_MAILBOX_EN_MASK BIT(0)
#define QDMA_GLBL2_DEVICE_ID_MASK GENMASK(31, 28) #define QDMA_GLBL2_DEVICE_ID_MASK GENMASK(31, 28)
#define QDMA_GLBL2_VIVADO_RELEASE_MASK GENMASK(27, 24) #define QDMA_GLBL2_VIVADO_RELEASE_MASK GENMASK(27, 24)
#define QDMA_GLBL2_VERSAL_IP_MASK GENMASK(23, 20) #define QDMA_GLBL2_VERSAL_IP_MASK GENMASK(23, 20)
...@@ -667,4 +595,4 @@ enum ind_ctxt_cmd_sel { ...@@ -667,4 +595,4 @@ enum ind_ctxt_cmd_sel {
} }
#endif #endif
#endif /* ifndef QDMA_SOFT_REG_H__ */ #endif /* __QDMA_SOFT_REG_H__ */
QDMA/DPDK/drivers/net/qdma/qdma_common.c
View file @ 00b6d04a
...@@ -544,7 +544,7 @@ int qdma_identify_bars(struct rte_eth_dev *dev) ...@@ -544,7 +544,7 @@ int qdma_identify_bars(struct rte_eth_dev *dev)
return -1; return -1;
} }
/* Find user bar*/ /* Find AXI Master Lite(user bar) */
ret = dma_priv->hw_access->qdma_get_user_bar(dev, ret = dma_priv->hw_access->qdma_get_user_bar(dev,
dma_priv->is_vf, dma_priv->func_id, &usr_bar); dma_priv->is_vf, dma_priv->func_id, &usr_bar);
if ((ret != QDMA_SUCCESS) || if ((ret != QDMA_SUCCESS) ||
...@@ -556,12 +556,12 @@ int qdma_identify_bars(struct rte_eth_dev *dev) ...@@ -556,12 +556,12 @@ int qdma_identify_bars(struct rte_eth_dev *dev)
dma_priv->user_bar_idx = 1; dma_priv->user_bar_idx = 1;
} else { } else {
dma_priv->user_bar_idx = -1; dma_priv->user_bar_idx = -1;
PMD_DRV_LOG(INFO, "Cannot find User BAR"); PMD_DRV_LOG(INFO, "Cannot find AXI Master Lite BAR");
} }
} else } else
dma_priv->user_bar_idx = usr_bar; dma_priv->user_bar_idx = usr_bar;
/* Find bypass bar*/ /* Find AXI Bridge Master bar(bypass bar) */
for (i = 0; i < QDMA_NUM_BARS; i++) { for (i = 0; i < QDMA_NUM_BARS; i++) {
bar_len = pci_dev->mem_resource[i].len; bar_len = pci_dev->mem_resource[i].len;
if (!bar_len) /* Bar not enabled ? */ if (!bar_len) /* Bar not enabled ? */
...@@ -575,8 +575,9 @@ int qdma_identify_bars(struct rte_eth_dev *dev) ...@@ -575,8 +575,9 @@ int qdma_identify_bars(struct rte_eth_dev *dev)
PMD_DRV_LOG(INFO, "QDMA config bar idx :%d\n", PMD_DRV_LOG(INFO, "QDMA config bar idx :%d\n",
dma_priv->config_bar_idx); dma_priv->config_bar_idx);
PMD_DRV_LOG(INFO, "QDMA user bar idx :%d\n", dma_priv->user_bar_idx); PMD_DRV_LOG(INFO, "QDMA AXI Master Lite bar idx :%d\n",
PMD_DRV_LOG(INFO, "QDMA bypass bar idx :%d\n", dma_priv->user_bar_idx);
PMD_DRV_LOG(INFO, "QDMA AXI Bridge Master bar idx :%d\n",
dma_priv->bypass_bar_idx); dma_priv->bypass_bar_idx);
return 0; return 0;
...@@ -590,7 +591,7 @@ int qdma_get_hw_version(struct rte_eth_dev *dev) ...@@ -590,7 +591,7 @@ int qdma_get_hw_version(struct rte_eth_dev *dev)
dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; dma_priv = (struct qdma_pci_dev *)dev->data->dev_private;
ret = dma_priv->hw_access->qdma_get_version(dev, ret = dma_priv->hw_access->qdma_get_version(dev,
dma_priv->is_vf, &version_info); dma_priv->is_vf, &version_info);
if (ret != QDMA_SUCCESS) if (ret < 0)
return dma_priv->hw_access->qdma_get_error_code(ret); return dma_priv->hw_access->qdma_get_error_code(ret);
dma_priv->rtl_version = version_info.rtl_version; dma_priv->rtl_version = version_info.rtl_version;
......
QDMA/DPDK/drivers/net/qdma/qdma_devops.c
View file @ 00b6d04a
...@@ -169,7 +169,10 @@ int qdma_pf_csr_read(struct rte_eth_dev *dev) ...@@ -169,7 +169,10 @@ int qdma_pf_csr_read(struct rte_eth_dev *dev)
"returned %d", ret); "returned %d", ret);
} }
if (ret < 0)
return qdma_dev->hw_access->qdma_get_error_code(ret); return qdma_dev->hw_access->qdma_get_error_code(ret);
return ret;
} }
static int qdma_pf_fmap_prog(struct rte_eth_dev *dev) static int qdma_pf_fmap_prog(struct rte_eth_dev *dev)
...@@ -185,7 +188,7 @@ static int qdma_pf_fmap_prog(struct rte_eth_dev *dev) ...@@ -185,7 +188,7 @@ static int qdma_pf_fmap_prog(struct rte_eth_dev *dev)
fmap_cfg.qmax = qdma_dev->qsets_en; fmap_cfg.qmax = qdma_dev->qsets_en;
ret = qdma_dev->hw_access->qdma_fmap_conf(dev, ret = qdma_dev->hw_access->qdma_fmap_conf(dev,
qdma_dev->func_id, &fmap_cfg, QDMA_HW_ACCESS_WRITE); qdma_dev->func_id, &fmap_cfg, QDMA_HW_ACCESS_WRITE);
if (ret != QDMA_SUCCESS) if (ret < 0)
return qdma_dev->hw_access->qdma_get_error_code(ret); return qdma_dev->hw_access->qdma_get_error_code(ret);
return ret; return ret;
...@@ -421,6 +424,28 @@ int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, ...@@ -421,6 +424,28 @@ int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
RTE_PMD_QDMA_RX_BYPASS_SIMPLE) RTE_PMD_QDMA_RX_BYPASS_SIMPLE)
rxq->en_bypass_prefetch = 1; rxq->en_bypass_prefetch = 1;
if (qdma_dev->ip_type == EQDMA_SOFT_IP &&
qdma_dev->vivado_rel >= QDMA_VIVADO_2020_2) {
if (qdma_dev->dev_cap.desc_eng_mode ==
QDMA_DESC_ENG_BYPASS_ONLY) {
PMD_DRV_LOG(ERR,
"Bypass only mode design "
"is not supported\n");
return -ENOTSUP;
}
if (rxq->en_bypass &&
(qdma_dev->dev_cap.desc_eng_mode ==
QDMA_DESC_ENG_INTERNAL_ONLY)) {
PMD_DRV_LOG(ERR,
"Rx qid %d config in bypass "
"mode not supported on "
"internal only mode design\n",
rx_queue_id);
return -ENOTSUP;
}
}
if (rxq->en_bypass) { if (rxq->en_bypass) {
rxq->bypass_desc_sz = rxq->bypass_desc_sz =
qdma_dev->q_info[rx_queue_id].rx_bypass_desc_sz; qdma_dev->q_info[rx_queue_id].rx_bypass_desc_sz;
...@@ -753,6 +778,28 @@ int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, ...@@ -753,6 +778,28 @@ int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
goto tx_setup_err; goto tx_setup_err;
} }
if (qdma_dev->ip_type == EQDMA_SOFT_IP &&
qdma_dev->vivado_rel >= QDMA_VIVADO_2020_2) {
if (qdma_dev->dev_cap.desc_eng_mode ==
QDMA_DESC_ENG_BYPASS_ONLY) {
PMD_DRV_LOG(ERR,
"Bypass only mode design "
"is not supported\n");
return -ENOTSUP;
}
if (txq->en_bypass &&
(qdma_dev->dev_cap.desc_eng_mode ==
QDMA_DESC_ENG_INTERNAL_ONLY)) {
PMD_DRV_LOG(ERR,
"Tx qid %d config in bypass "
"mode not supported on "
"internal only mode design\n",
tx_queue_id);
return -ENOTSUP;
}
}
/* Allocate memory for TX descriptor ring */ /* Allocate memory for TX descriptor ring */
if (txq->st_mode) { if (txq->st_mode) {
if (!qdma_dev->dev_cap.st_en) { if (!qdma_dev->dev_cap.st_en) {
...@@ -1104,6 +1151,7 @@ void qdma_dev_close(struct rte_eth_dev *dev) ...@@ -1104,6 +1151,7 @@ void qdma_dev_close(struct rte_eth_dev *dev)
struct qdma_cmpt_queue *cmptq; struct qdma_cmpt_queue *cmptq;
uint32_t qid; uint32_t qid;
struct qdma_fmap_cfg fmap_cfg; struct qdma_fmap_cfg fmap_cfg;
int ret = 0;
PMD_DRV_LOG(INFO, "PF-%d(DEVFN) DEV Close\n", qdma_dev->func_id); PMD_DRV_LOG(INFO, "PF-%d(DEVFN) DEV Close\n", qdma_dev->func_id);
...@@ -1189,8 +1237,14 @@ void qdma_dev_close(struct rte_eth_dev *dev) ...@@ -1189,8 +1237,14 @@ void qdma_dev_close(struct rte_eth_dev *dev)
} }
} }
qdma_dev->qsets_en = 0; qdma_dev->qsets_en = 0;
qdma_dev_update(qdma_dev->dma_device_index, qdma_dev->func_id, ret = qdma_dev_update(qdma_dev->dma_device_index, qdma_dev->func_id,
qdma_dev->qsets_en, (int *)&qdma_dev->queue_base); qdma_dev->qsets_en, (int *)&qdma_dev->queue_base);
if (ret != QDMA_SUCCESS) {
PMD_DRV_LOG(ERR, "PF-%d(DEVFN) qmax update failed: %d\n",
qdma_dev->func_id, ret);
return;
}
qdma_dev->init_q_range = 0; qdma_dev->init_q_range = 0;
rte_free(qdma_dev->q_info); rte_free(qdma_dev->q_info);
qdma_dev->q_info = NULL; qdma_dev->q_info = NULL;
...@@ -1451,7 +1505,7 @@ int qdma_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid) ...@@ -1451,7 +1505,7 @@ int qdma_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid)
err = hw_access->qdma_sw_ctx_conf(dev, 0, err = hw_access->qdma_sw_ctx_conf(dev, 0,
(qid + queue_base), &q_sw_ctxt, (qid + queue_base), &q_sw_ctxt,
QDMA_HW_ACCESS_WRITE); QDMA_HW_ACCESS_WRITE);
if (err != QDMA_SUCCESS) if (err < 0)
return qdma_dev->hw_access->qdma_get_error_code(err); return qdma_dev->hw_access->qdma_get_error_code(err);
txq->q_pidx_info.pidx = 0; txq->q_pidx_info.pidx = 0;
...@@ -1557,20 +1611,20 @@ int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid) ...@@ -1557,20 +1611,20 @@ int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid)
/* Set SW Context */ /* Set SW Context */
err = hw_access->qdma_sw_ctx_conf(dev, 1, (qid + queue_base), err = hw_access->qdma_sw_ctx_conf(dev, 1, (qid + queue_base),
&q_sw_ctxt, QDMA_HW_ACCESS_WRITE); &q_sw_ctxt, QDMA_HW_ACCESS_WRITE);
if (err != QDMA_SUCCESS) if (err < 0)
return qdma_dev->hw_access->qdma_get_error_code(err); return qdma_dev->hw_access->qdma_get_error_code(err);
if (rxq->st_mode) { if (rxq->st_mode) {
/* Set Prefetch Context */ /* Set Prefetch Context */
err = hw_access->qdma_pfetch_ctx_conf(dev, (qid + queue_base), err = hw_access->qdma_pfetch_ctx_conf(dev, (qid + queue_base),
&q_prefetch_ctxt, QDMA_HW_ACCESS_WRITE); &q_prefetch_ctxt, QDMA_HW_ACCESS_WRITE);
if (err != QDMA_SUCCESS) if (err < 0)
return qdma_dev->hw_access->qdma_get_error_code(err); return qdma_dev->hw_access->qdma_get_error_code(err);
/* Set Completion Context */ /* Set Completion Context */
err = hw_access->qdma_cmpt_ctx_conf(dev, (qid + queue_base), err = hw_access->qdma_cmpt_ctx_conf(dev, (qid + queue_base),
&q_cmpt_ctxt, QDMA_HW_ACCESS_WRITE); &q_cmpt_ctxt, QDMA_HW_ACCESS_WRITE);
if (err != QDMA_SUCCESS) if (err < 0)
return qdma_dev->hw_access->qdma_get_error_code(err); return qdma_dev->hw_access->qdma_get_error_code(err);
rte_wmb(); rte_wmb();
...@@ -1707,26 +1761,37 @@ int ...@@ -1707,26 +1761,37 @@ int
qdma_dev_get_regs(struct rte_eth_dev *dev, qdma_dev_get_regs(struct rte_eth_dev *dev,
struct rte_dev_reg_info *regs) struct rte_dev_reg_info *regs)
{ {
struct qdma_pci_dev *qdma_dev = dev->data->dev_private;
uint32_t *data = regs->data; uint32_t *data = regs->data;
uint32_t count = 0; uint32_t reg_length = 0;
uint32_t reg_length = (sizeof(qdma_config_regs) / int ret = 0;
sizeof(qdma_config_regs[0])) - 1;
ret = qdma_acc_get_num_config_regs(dev,
(enum qdma_ip_type)qdma_dev->ip_type,
&reg_length);
if (ret < 0 || reg_length == 0) {
PMD_DRV_LOG(ERR, "%s: Failed to get number of config registers\n",
__func__);
return ret;
}
if (data == NULL) { if (data == NULL) {
regs->length = reg_length; regs->length = reg_length - 1;
regs->width = sizeof(uint32_t); regs->width = sizeof(uint32_t);
return 0; return 0;
} }
/* Support only full register dump */ /* Support only full register dump */
if ((regs->length == 0) || if ((regs->length == 0) ||
(regs->length == reg_length)) { (regs->length == (reg_length - 1))) {
regs->version = 1; regs->version = 1;
for (count = 0; count < reg_length; count++) { ret = qdma_acc_get_config_regs(dev, qdma_dev->is_vf,
data[count] = qdma_reg_read(dev, (enum qdma_ip_type)qdma_dev->ip_type, data);
qdma_config_regs[count].addr); if (ret < 0) {
PMD_DRV_LOG(ERR, "%s: Failed to get config registers\n",
__func__);
} }
return 0; return ret;
} }
PMD_DRV_LOG(ERR, "%s: Unsupported length (0x%x) requested\n", PMD_DRV_LOG(ERR, "%s: Unsupported length (0x%x) requested\n",
......
QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
View file @ 00b6d04a
...@@ -61,6 +61,8 @@ ...@@ -61,6 +61,8 @@
#define PCI_CONFIG_BRIDGE_DEVICE (6) #define PCI_CONFIG_BRIDGE_DEVICE (6)
#define PCI_CONFIG_CLASS_CODE_SHIFT (16) #define PCI_CONFIG_CLASS_CODE_SHIFT (16)
#define MAX_PCIE_CAPABILITY (48)
static void qdma_device_attributes_get(struct rte_eth_dev *dev); static void qdma_device_attributes_get(struct rte_eth_dev *dev);
/* Poll for any QDMA errors */ /* Poll for any QDMA errors */
...@@ -273,23 +275,25 @@ static inline uint8_t pcie_find_cap(const struct rte_pci_device *pci_dev, ...@@ -273,23 +275,25 @@ static inline uint8_t pcie_find_cap(const struct rte_pci_device *pci_dev,
{ {
uint8_t pcie_cap_pos = 0; uint8_t pcie_cap_pos = 0;
uint8_t pcie_cap_id = 0; uint8_t pcie_cap_id = 0;
int ttl = MAX_PCIE_CAPABILITY;
int ret;
if (rte_pci_read_config(pci_dev, &pcie_cap_pos, sizeof(uint8_t), ret = rte_pci_read_config(pci_dev, &pcie_cap_pos, sizeof(uint8_t),
PCI_CAPABILITY_LIST) < 0) { PCI_CAPABILITY_LIST);
if (ret < 0) {
PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); PMD_DRV_LOG(ERR, "PCIe config space read failed..\n");
return 0; return 0;
} }
if (pcie_cap_pos < 0x40) while (ttl-- && pcie_cap_pos >= PCI_STD_HEADER_SIZEOF) {
return 0;
while (pcie_cap_pos >= 0x40) {
pcie_cap_pos &= ~3; pcie_cap_pos &= ~3;
if (rte_pci_read_config(pci_dev, &pcie_cap_id, sizeof(uint8_t), ret = rte_pci_read_config(pci_dev,
pcie_cap_pos + PCI_CAP_LIST_ID) < 0) { &pcie_cap_id, sizeof(uint8_t),
(pcie_cap_pos + PCI_CAP_LIST_ID));
if (ret < 0) {
PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); PMD_DRV_LOG(ERR, "PCIe config space read failed..\n");
goto ret; return 0;
} }
if (pcie_cap_id == 0xff) if (pcie_cap_id == 0xff)
...@@ -298,14 +302,15 @@ static inline uint8_t pcie_find_cap(const struct rte_pci_device *pci_dev, ...@@ -298,14 +302,15 @@ static inline uint8_t pcie_find_cap(const struct rte_pci_device *pci_dev,
if (pcie_cap_id == cap) if (pcie_cap_id == cap)
return pcie_cap_pos; return pcie_cap_pos;
if (rte_pci_read_config(pci_dev, &pcie_cap_pos, sizeof(uint8_t), ret = rte_pci_read_config(pci_dev,
pcie_cap_pos + PCI_CAP_LIST_NEXT) < 0) { &pcie_cap_pos, sizeof(uint8_t),
(pcie_cap_pos + PCI_CAP_LIST_NEXT));
if (ret < 0) {
PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); PMD_DRV_LOG(ERR, "PCIe config space read failed..\n");
goto ret; return 0;
} }
} }
ret:
return 0; return 0;
} }
...@@ -402,16 +407,10 @@ static int parse_pci_addr_format(const char *buf, ...@@ -402,16 +407,10 @@ static int parse_pci_addr_format(const char *buf,
*splitaddr.function++ = '\0'; *splitaddr.function++ = '\0';
/* now convert to int values */ /* now convert to int values */
errno = 0;
addr->domain = strtoul(splitaddr.domain, NULL, 16); addr->domain = strtoul(splitaddr.domain, NULL, 16);
addr->bus = strtoul(splitaddr.bus, NULL, 16); addr->bus = strtoul(splitaddr.bus, NULL, 16);
addr->devid = strtoul(splitaddr.devid, NULL, 16); addr->devid = strtoul(splitaddr.devid, NULL, 16);
addr->function = strtoul(splitaddr.function, NULL, 10); addr->function = strtoul(splitaddr.function, NULL, 10);
if (errno != 0) {
PMD_DRV_LOG(ERR,
"Failed to convert pci address to int values\n");
goto error;
}
free(buf_copy); /* free the copy made with strdup */ free(buf_copy); /* free the copy made with strdup */
return 0; return 0;
...@@ -440,8 +439,8 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus) ...@@ -440,8 +439,8 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus)
/* Open pci devices directory */ /* Open pci devices directory */
dir = opendir(rte_pci_get_sysfs_path()); dir = opendir(rte_pci_get_sysfs_path());
if (dir == NULL) { if (dir == NULL) {
PMD_DRV_LOG(ERR, "%s(): opendir failed: %s\n", PMD_DRV_LOG(ERR, "%s(): opendir failed\n",
__func__, strerror(errno)); __func__);
return -1; return -1;
} }
...@@ -471,8 +470,8 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus) ...@@ -471,8 +470,8 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus)
"%s/config", dirname); "%s/config", dirname);
fd = open(cfgname, O_RDWR); fd = open(cfgname, O_RDWR);
if (fd < 0) { if (fd < 0) {
PMD_DRV_LOG(ERR, "Failed to open %s: %s\n", PMD_DRV_LOG(ERR, "Failed to open %s\n",
cfgname, strerror(errno)); cfgname);
goto error; goto error;
} }
...@@ -493,7 +492,6 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus) ...@@ -493,7 +492,6 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus)
close(fd); close(fd);
goto error; goto error;
} }
close(fd);
/* Get max bus number by checking if given bus number /* Get max bus number by checking if given bus number
* falls in between secondary and subordinate bus * falls in between secondary and subordinate bus
...@@ -502,9 +500,12 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus) ...@@ -502,9 +500,12 @@ static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus)
if ((start_bus >= sec_bus_num) && if ((start_bus >= sec_bus_num) &&
(start_bus <= sub_bus_num)) { (start_bus <= sub_bus_num)) {
*end_bus = sub_bus_num; *end_bus = sub_bus_num;
close(fd);
closedir(dir); closedir(dir);
return 0; return 0;
} }
close(fd);
} }
} }
...@@ -621,7 +622,7 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev) ...@@ -621,7 +622,7 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev)
return -EINVAL; return -EINVAL;
} }
/* Store BAR address and length of User BAR */ /* Store BAR address and length of AXI Master Lite BAR(user bar) */
if (dma_priv->user_bar_idx >= 0) { if (dma_priv->user_bar_idx >= 0) {
baseaddr = (uint8_t *) baseaddr = (uint8_t *)
pci_dev->mem_resource[dma_priv->user_bar_idx].addr; pci_dev->mem_resource[dma_priv->user_bar_idx].addr;
...@@ -699,8 +700,23 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev) ...@@ -699,8 +700,23 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev)
} }
} }
dma_priv->hw_access->qdma_init_ctxt_memory(dev); ret = dma_priv->hw_access->qdma_init_ctxt_memory(dev);
dma_priv->hw_access->qdma_hw_error_enable(dev, QDMA_ERRS_ALL); if (ret < 0) {
PMD_DRV_LOG(ERR,
"%s: Failed to initialize ctxt memory, err = %d\n",
__func__, ret);
return -EINVAL;
}
dma_priv->hw_access->qdma_hw_error_enable(dev,
dma_priv->hw_access->qdma_max_errors);
if (ret < 0) {
PMD_DRV_LOG(ERR,
"%s: Failed to enable hw errors, err = %d\n",
__func__, ret);
return -EINVAL;
}
rte_eal_alarm_set(QDMA_ERROR_POLL_FRQ, qdma_check_errors, rte_eal_alarm_set(QDMA_ERROR_POLL_FRQ, qdma_check_errors,
(void *)dev); (void *)dev);
dma_priv->is_master = 1; dma_priv->is_master = 1;
......
QDMA/DPDK/drivers/net/qdma/qdma_platform.c
View file @ 00b6d04a
...@@ -202,41 +202,6 @@ void qdma_udelay(uint32_t delay_usec) ...@@ -202,41 +202,6 @@ void qdma_udelay(uint32_t delay_usec)
rte_delay_us(delay_usec); rte_delay_us(delay_usec);
} }
/*****************************************************************************/
/**
* qdma_hw_error_handler() - function to handle the hardware errors
*
* @dev_hndl: device handle
* @err_idx: error index
*
* Return: None
*****************************************************************************/
void qdma_hw_error_handler(void *dev_hndl, enum qdma_error_idx err_idx)
{
struct qdma_pci_dev *qdma_dev;
qdma_dev = ((struct rte_eth_dev *)dev_hndl)->data->dev_private;
rte_log(RTE_LOG_ERR, RTE_LOGTYPE_PMD,
"%s(): Detected %s\n", __func__,
qdma_dev->hw_access->qdma_hw_get_error_name(err_idx));
}
/*****************************************************************************/
/**
* qdma_get_device_attr() - function to retrive device attributes
*
* @dev_hndl: device handle
* @dev_cap: pointer to the device attributes structure
*
* Return: None
*****************************************************************************/
void qdma_get_device_attr(void *dev_hndl, struct qdma_dev_attributes **dev_cap)
{
struct qdma_pci_dev *qdma_dev;
qdma_dev = ((struct rte_eth_dev *)dev_hndl)->data->dev_private;
*dev_cap = &qdma_dev->dev_cap;
}
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_get_hw_access() - function to get the qdma_hw_access * qdma_get_hw_access() - function to get the qdma_hw_access
...@@ -270,11 +235,16 @@ void qdma_strncpy(char *dest, const char *src, size_t n) ...@@ -270,11 +235,16 @@ void qdma_strncpy(char *dest, const char *src, size_t n)
/** /**
* qdma_get_err_code() - function to get the qdma access mapped error code * qdma_get_err_code() - function to get the qdma access mapped error code
* *
* @acc_err_code: qdma access error code * @acc_err_code: qdma access error code which is a negative input value
* *
* Return: returns the platform specific error code * Return: returns the platform specific error code
*****************************************************************************/ *****************************************************************************/
int qdma_get_err_code(int acc_err_code) int qdma_get_err_code(int acc_err_code)
{ {
/* Multiply acc_err_code with -1 to convert it to a postive number
* and use it as an array index for error codes.
*/
acc_err_code *= -1;
return -(error_code_map_list[acc_err_code].err_code); return -(error_code_map_list[acc_err_code].err_code);
} }
QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
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QDMA/DPDK/drivers/net/qdma/qdma_user.c
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QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
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QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
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QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
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QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
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QDMA/DPDK/drivers/net/qdma/version.h
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QDMA/DPDK/examples/qdma_testapp/Makefile
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QDMA/DPDK/examples/qdma_testapp/commands.c
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QDMA/DPDK/examples/qdma_testapp/commands.h
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QDMA/DPDK/examples/qdma_testapp/pcierw.c
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QDMA/DPDK/examples/qdma_testapp/pcierw.h
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QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
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QDMA/DPDK/examples/qdma_testapp/testapp.c
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QDMA/DPDK/examples/qdma_testapp/testapp.h
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