2020.2 XVSEC Driver Release Supporting the MCAP functionality for US/US+ and Versal Devices

2020.2 XVSEC Driver Release - Supports the MCAP functionality for US/US+ and Versal Devices

XVSEC/linux-kernel/RELEASE

-Release: 2018.3
-===========================
+Release: 2020.2
+============================
 
 NOTE:
-	This release is based on the 2018.3 XVSEC-MCAP Design
-
-	XVSEC driver is implemented as a single character device per PCIe Device
+	This release is based on the 2020.2 XVSEC-MCAP Design.
 
-
-DRIVER LIMITATIONS:
-===================
-- Unique character device per VSEC functionality is not implemented
+	XVSEC driver is implemented to support Ultrascale, Ultrascale+, and Versal devices.
 
 SUPPORTED FEATURES:
 ===================
+
+Release: 2020.2
+---------------
+- The XVSEC kernel driver 2020.2 Supports
+	- US/US+ devices (MCAP Rev 0 and 1)
+	- Versal device (MCAP Rev 2)
+- Supports Multiple VSECs on the same device
+- Supports Multiple devices connected on the same host
+
+- Generic VSEC functionality
+	- Lists the supported VSECs by the device
+	- Verbose information about the device
+
+- The following MCAP operations supported for Versal devices
+	- MCAP Module Reset
+	- List MCAP Register set
+	- File Download at user specified address
+		- Fixed Address download for FIFO devices
+		- Increment Address download
+		- 32b mode download for 32b supported devices
+		- 128b mode download for 128b suppported devices
+		- Slow and Fast download mode supported
+	- File Upload from user specified address
+		- Fixed Address upload for FIFO devices
+		- Increment Address upload
+	- Access(Read/Write) any MCAP register by providing offset
+	- Access(Read/Write) any Device register connected to AXI bus by providing address
+	- Set the AXI cache and protections bits
+
+Release: 2018.3
+---------------
+- The XVSEC kernel driver 2018.3 Supports
+	- US/US+ devices (MCAP Rev 0 and 1)
+
 - MCAP VSEC functionality is implemented as part of the XVSEC driver
 - Multiple Devices on the Same Host supported
 	- Unique character device gets created per device
@@ -31,6 +60,10 @@ SUPPORTED FEATURES:
 	- Program partial clear bitstream
 	- Program Stage-2/partial reconfigurable bitstream
 
-KNOWN BUGS:
+DRIVER LIMITATIONS:
+===================
+- Only MCAP VSEC is supported
+
+KNOWN Issues:
 ===========
-None
+XVSEC kernel driver 2020.2 does not support Fast download mode for Versal devices.
\ No newline at end of file

XVSEC/linux-kernel/drv/Makefile

@@ -4,21 +4,35 @@ XVSEC_KVER := $(shell uname -r)
 build_path := ../build
 module_path := $(build_path)/modules
 obj-m += xvsec.o
-xvsec-objs := xvsec_cdev.o xvsec_drv.o
+xvsec-objs := xvsec_drv.o xvsec_cdev.o xvsec_util.o
+xvsec-objs += ./xvsec_mcap/xvsec_mcap.o
+xvsec-objs += ./xvsec_mcap/us/xvsec_mcap_us.o
+xvsec-objs += ./xvsec_mcap/versal/xvsec_mcap_versal.o
+
+ccflags-y := -I$(PWD) -I$(PWD)/xvsec_mcap
+ccflags-y += -I$(PWD)/xvsec_mcap/us
+ccflags-y += -I$(PWD)/xvsec_mcap/versal
 
 all:
 	@mkdir -p -m 755 $(build_path)
 	@mkdir -p -m 755 $(module_path)
 	@mkdir -p -m 755 $(module_path)/obj
+	@mkdir -p -m 755 $(module_path)/obj/xvsec_mcap
+	@mkdir -p -m 755 $(module_path)/obj/xvsec_mcap/us
+	@mkdir -p -m 755 $(module_path)/obj/xvsec_mcap/versal
 	make -C /lib/modules/$(XVSEC_KVER)/build M=$(XVSEC_HOME) modules
 	@mv *.ko $(module_path)/
-	@cp xvsec_cdev.h $(module_path)/
+	@cp xvsec_drv.h $(module_path)/
+	@cp ./xvsec_mcap/xvsec_mcap.h $(module_path)/
 	@mv *.o  $(module_path)/obj/
 	@mv .*cmd $(module_path)/obj/
 	@mv *.symvers $(module_path)/obj/
 	@mv *.mod* $(module_path)/obj/
 	@mv *.order* $(module_path)/obj/
 	@mv .tmp* $(module_path)/obj/
+	@mv ./xvsec_mcap/*.o $(module_path)/obj/xvsec_mcap/
+	@mv ./xvsec_mcap/us/*.o $(module_path)/obj/xvsec_mcap/us/
+	@mv ./xvsec_mcap/versal/*.o $(module_path)/obj/xvsec_mcap/versal/
 
 clean:
 	@rm -rf $(module_path)

XVSEC/linux-kernel/drv/version.h

 /*
  * This file is part of the XVSEC driver for Linux
  *
- * Copyright (c) 2018,  Xilinx, Inc.
+ * Copyright (c) 2018-2020,  Xilinx, Inc.
  * All rights reserved.
  *
  * This source code is free software; you can redistribute it and/or modify it
@@ -23,8 +23,8 @@
 #define XVSEC_MODULE_NAME	"xvsec"
 #define XVSEC_MODULE_DESC	"Xilinx VSEC Library"
 
-#define XVSEC_VERSION_MAJOR	2018
-#define XVSEC_VERSION_MINOR	3
+#define XVSEC_VERSION_MAJOR	2020
+#define XVSEC_VERSION_MINOR	2
 #define XVSEC_VERSION_PATCH	0
 
 #define XVSEC_DRV_VERSION	\

XVSEC/linux-kernel/drv/xvsec_cdev.h

 /*
  * This file is part of the XVSEC driver for Linux
  *
- * Copyright (c) 2018,  Xilinx, Inc.
+ * Copyright (c) 2018-2020,  Xilinx, Inc.
  * All rights reserved.
  *
  * This source code is free software; you can redistribute it and/or modify it
@@ -21,273 +21,59 @@
 #define __XVSEC_CDEV_H__
 
 /**
- * @file
- * @brief This file contains the interface declarations of XVSEC driver
+ * @file xvsec_cdev.h
  *
+ * Xilinx XVSEC Driver Library Definitions
+ *
+ * Header file *xvsec_cdev.h* defines data structures neeed for
+ * character device implementation by the driver
+ *
+ * These data structures are purely internal to the driver
+ * and not meant to user
  */
 
-/**
- * XVSEC ioctl magic character
- */
-#define XVSEC_IOC_MAGIC				'm'
-/**
- * XVSEC char device first minor number
- */
-#define XVSEC_MINOR_BASE			(0)
-/**
- * XVSEC char device total minor numbers count
- */
-#define XVSEC_MINOR_COUNT			(1)
-/**
- * XILINX PCIe vendor ID
+
+/** @defgroup xvsec_enums Enumerations
  */
-#define XILINX_VENDOR_ID			(uint16_t)(0x10ee)
-/**
- * XILINX PCIe vendor specific capability ID
+/** @defgroup xvsec_struct Data Structures
  */
-#define MCAP_EXT_CAP_ID				(uint16_t)(0x000B)
 /**
- * Maximum Supported capabilities by the driver
+ * @defgroup xvsec_defines Definitions
+ * @{
  */
-#define MAX_CAPABILITIES_SUPPORTED		10
 
-/**
- * @enum - bitstream_program_status
- * @brief	program status(Success/Failure)
- */
-enum bitstream_program_status {
-	/** Programming Success Indication */
-	MCAP_BITSTREAM_PROGRAM_SUCCESS = 0,
-	/** Programming Failure Indication */
-	MCAP_BITSTREAM_PROGRAM_FAILURE = 1
-};
 
-/**
- * @struct - mcap_regs
- * @brief	MCAP register set
- */
-struct mcap_regs {
-	/** Valid flag to indicate registers validity */
-	uint32_t	valid;
-	/** Extended capability header register */
-	uint32_t	ext_cap_header;
-	/** Vendor Specific header register */
-	uint32_t	vendor_header;
-	/** FPGA JTAG ID register */
-	uint32_t	fpga_jtag_id;
-	/** FPGA bit-stream version register */
-	uint32_t	fpga_bit_ver;
-	/** Status Register */
-	uint32_t	status_reg;
-	/** Control Register */
-	uint32_t	control_reg;
-	/** Write Data Register */
-	uint32_t	wr_data_reg;
-	/** Read Data Register: 4 data words */
-	uint32_t	rd_data_reg[4];
-};
+#define XVSEC_CDEV_NAME_MAX_LEN		(20)
 
-/**
- * @struct - bitstream_file
- * @brief	MCAP bitstream parameters for programming
- */
-struct bitstream_file {
-	/** Partial clear bitstream file to program ultrascale devices */
-	char *partial_clr_file;
-	/** bitstream file to program */
-	char *bitstream_file;
-	/** Status of the bitstream programming */
-	enum bitstream_program_status status;
-};
+#define XVSEC_NODE_NAME			"xvsec"
 
 /**
- * @struct - cfg_data
- * @brief	MCAP configuration parameters to perform read and writes
- */
-struct cfg_data {
-	/** access field. 'b' for byte access, 'h'for half word access,
-	 *  'w' for word access
-	 */
-	char		access;
-	/** VSEC address offset */
-	uint16_t	offset;
-	/** data field holds the information to write into the provided offset
-	 *  for Write operation.
-	 *  Holds the information at the provided offset for read operation
+ * XVSEC char device first minor number
  */
-	uint32_t	data;
-};
-
+#define XVSEC_MINOR_BASE			(0)
 /**
- * @struct - fpga_cfg_reg
- * @brief	FPGA configuration parameters to perform read and writes
- */
-struct fpga_cfg_reg {
-	/** FPGA configuration register number */
-	uint16_t	offset;
-	/** data field holds the information to write into the provided offset
-	 *  for Write operation.
-	 *  Holds the information at the provided offset for read operation
+ * XVSEC char device total minor numbers count
  */
-	uint32_t	data;
-};
+#define XVSEC_MINOR_COUNT			(1)
 
-/**
- * @struct - fpga_cfg_regs
- * @brief	FPGA configuration register set(See UG570 for more information)
- */
-struct fpga_cfg_regs {
-	/** Valid flag to indicate registers validity */
-	uint32_t valid;
-	/** CRC Register */
-	uint32_t crc;
-	/** Frame Address Register */
-	uint32_t far;
-	/** Frame Data Register, Input Register (write configuration data) */
-	uint32_t fdri;
-	/** Frame Data Register, Output Register (read configuration data) */
-	uint32_t fdro;
-	/** Command Register */
-	uint32_t cmd;
-	/** Control Register 0 */
-	uint32_t ctl0;
-	/** Mask Register for CTL0 and CTL1 Registers */
-	uint32_t mask;
-	/** Status Register */
-	uint32_t stat;
-	/** Legacy Output Register for Daisy Chain */
-	uint32_t lout;
-	/** Configuration Option Register 0 */
-	uint32_t cor0;
-	/** Multi Frame Write Register */
-	uint32_t mfwr;
-	/** Initial CBC Value Register */
-	uint32_t cbc;
-	/** Device ID Register */
-	uint32_t idcode;
-	/** User Access Register */
-	uint32_t axss;
-	/** Configuration Option Register 1 */
-	uint32_t cor1;
-	/** Warm Boot Start Address Register */
-	uint32_t wbstar;
-	/** Watchdog Timer Register */
-	uint32_t timer;
-	/** Scratch Pad Register for Dummy Read and Writes */
-	uint32_t scratchpad;
-	/** Boot History Status Register */
-	uint32_t bootsts;
-	/** Control Register 1 */
-	uint32_t ctl1;
-	/** BPI/SPI Configuration Options Register */
-	uint32_t bspi;
-};
 
-/**
- * @struct - device_info
- * @brief	PCIe device information for verbose option
- */
-struct device_info {
-	/** PCIe Vendor Identifier */
-	uint16_t vendor_id;
-	/** PCIe Device Identifier */
-	uint16_t device_id;
-	/** PCIe Device number */
-	uint16_t device_no;
-	/** PCIe Device function */
-	uint16_t device_fn;
-	/** PCIe Subsystem Vendor Identifier */
-	uint16_t subsystem_vendor;
-	/** PCIe Subsystem Device Identifier */
-	uint16_t subsystem_device;
-	/** PCIe Class Identifier */
-	uint16_t class_id;
-	/** Flag which indicates MSI enabled status */
-	uint32_t is_msi_enabled;
-	/** Flag which indicates MSIx enabled status */
-	uint32_t is_msix_enabled;
-	/** Size of the PCIe Device configuration space */
-	int      cfg_size;
-};
+/** @} */
 
-/**
- * @struct - xvsec_capabilities
- * @brief	Xilinx Vendor Specific Capabilities
- */
-struct xvsec_capabilities {
-	/** Number of VSEC capabilities supported by the device */
-	uint16_t	no_of_caps;
-	/** Capability ID Info */
-	uint16_t	capability_id[MAX_CAPABILITIES_SUPPORTED];
-	/** Capability Offset Info in PCIe configuration space */
-	uint16_t	capability_offset[MAX_CAPABILITIES_SUPPORTED];
+struct cdev_info {
+	dev_t		dev_no;
+	int		major_no;
+	char		name[XVSEC_CDEV_NAME_MAX_LEN];
+	struct cdev	cdev;
+	struct device	*sys_device;
 };
 
-/**
- * ioctl code for retrieving the XVSEC capability list
- */
-#define IOC_XVSEC_GET_CAP_LIST			\
-	_IOW(XVSEC_IOC_MAGIC, 0, struct xvsec_capabilities *)
-/**
- * ioctl code for performing MCAP configuration logic reset
- */
-#define IOC_MCAP_RESET					\
-	_IO(XVSEC_IOC_MAGIC, 1)
-/**
- * ioctl code for performing MCAP Module reset
- */
-#define IOC_MCAP_MODULE_RESET			\
-	_IO(XVSEC_IOC_MAGIC, 2)
-/**
- * ioctl code for performing both configuration logic & Module reset
- */
-#define IOC_MCAP_FULL_RESET				\
-	_IO(XVSEC_IOC_MAGIC, 3)
-/**
- * ioctl code for retrieving the MCAP Read Data Registers
- */
-#define IOC_MCAP_GET_DATA_REGISTERS		\
-	_IOR(XVSEC_IOC_MAGIC, 4, uint32_t *)
-/**
- * ioctl code for retrieving the MCAP Registers
- */
-#define IOC_MCAP_GET_REGISTERS			\
-	_IOR(XVSEC_IOC_MAGIC, 5, struct mcap_regs *)
-/**
- * ioctl code for retrieving the FPGA configuration Registers
- */
-#define IOC_MCAP_GET_FPGA_REGISTERS			\
-	_IOR(XVSEC_IOC_MAGIC, 6, struct mcap_regs *)
-/**
- * ioctl code for programming the bitstream
- */
-#define IOC_MCAP_PROGRAM_BITSTREAM		\
-	_IOWR(XVSEC_IOC_MAGIC, 7, struct bitstream_file *)
-/**
- * ioctl code for reading an MCAP VSEC register
- */
-#define IOC_MCAP_READ_DEV_CFG_REG		\
-	_IOWR(XVSEC_IOC_MAGIC, 8, struct cfg_data *)
-/**
- * ioctl code for Writing to an MCAP VSEC register
- */
-#define IOC_MCAP_WRITE_DEV_CFG_REG	\
-	_IOWR(XVSEC_IOC_MAGIC, 9, struct cfg_data *)
-/**
- * ioctl code for reading an FPGA CFG register
- */
-#define IOC_MCAP_READ_FPGA_CFG_REG \
-	_IOWR(XVSEC_IOC_MAGIC, 10, struct fpga_cfg_reg *)
-/**
- * ioctl code for writing to an FPGA CFG register
- */
-#define IOC_MCAP_WRITE_FPGA_CFG_REG \
-	_IOWR(XVSEC_IOC_MAGIC, 11, struct fpga_cfg_reg *)
-/**
- * ioctl code for retrieving the Device information
- */
-#define IOC_GET_DEVICE_INFO \
-	_IOWR(XVSEC_IOC_MAGIC, 12, struct device_info *)
+int xvsec_cdev_create(
+	struct pci_dev *pdev,
+	struct cdev_info *char_dev,
+	const struct file_operations *fops,
+	const char *dev_name);
 
+void xvsec_cdev_remove(
+	struct cdev_info *char_dev);
 
 #endif /* __XVSEC_CDEV_H__ */

XVSEC/linux-kernel/drv/xvsec_drv.h

+/*
+ * This file is part of the XVSEC driver for Linux
+ *
+ * Copyright (c) 2020,  Xilinx, Inc.
+ * All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef __XVSEC_DRV_H__
+#define __XVSEC_DRV_H__
+
+/**
+ * @file xvsec_drv.h
+ *
+ * Xilinx XVSEC Driver Library Interface Definitions
+ *
+ * Header file *xvsec_drv.h* defines data structures and ioctl codes
+ * exported by Xilinx XVSEC driver for common VSEC operations.
+ *
+ * These data structures and ioctl codes can be used by user space
+ * applications to carry-out the XVSEC functionality
+ */
+
+/** @defgroup xvsec_enums Enumerations
+ */
+/** @defgroup xvsec_struct Data Structures
+ */
+/** @defgroup xvsec_union Data Structures
+ */
+/**
+ * @defgroup xvsec_defines Definitions
+ * @{
+ */
+
+/**
+ * XVSEC ioctl magic character
+ */
+#define XVSEC_IOC_MAGIC		'v'
+
+/**
+ * Maximum Supported capabilities by the driver
+ */
+#define MAX_CAPABILITIES_SUPPORTED		10
+
+/**
+ * Maximum Vsec string length
+ */
+#define MAX_VSEC_STR_LEN		20
+
+/**
+ * Unknown VSEC Revision ID
+ */
+#define VSEC_REV_UNKNOWN		(0xFF)
+
+/** @} */
+
+/**
+ * @struct - device_info
+ * @brief	PCIe device information for verbose option
+ *
+ * @ingroup xvsec_union
+ */
+union device_info {
+	struct {
+		/** PCIe Vendor Identifier */
+		uint16_t vendor_id;
+		/** PCIe Device Identifier */
+		uint16_t device_id;
+		/** PCIe Device number */
+		uint16_t device_no;
+		/** PCIe Device function */
+		uint16_t device_fn;
+		/** PCIe Subsystem Vendor Identifier */
+		uint16_t subsystem_vendor;
+		/** PCIe Subsystem Device Identifier */
+		uint16_t subsystem_device;
+		/** PCIe Class Identifier */
+		uint16_t class_id;
+		/** Flag which indicates MSI enabled status */
+		uint32_t is_msi_enabled;
+		/** Flag which indicates MSIx enabled status */
+		uint32_t is_msix_enabled;
+		/** Size of the PCIe Device configuration space */
+		int      cfg_size;
+	};
+};
+
+/**
+ * @struct - xvsec_vsec_info
+ * @brief       Xilinx Vendor Specific Capabilities device information
+ *
+ * @ingroup xvsec_struct
+ */
+struct xvsec_vsec_info {
+	/** Capability ID Info */
+	uint16_t	cap_id;
+	/** VSEC revision Info */
+	uint16_t	rev_id;
+	/** Capability Offset Info in PCIe configuration space */
+	uint16_t	offset;
+	/** VSEC Capability name */
+	char	name[MAX_VSEC_STR_LEN];
+	/** info to check capability supported by this drv or not*/
+	bool	is_supported;
+};
+
+/**
+ * @struct - xvsec_capabilities
+ * @brief	Xilinx Vendor Specific Capabilities present in the device
+ *
+ * @ingroup xvsec_struct
+ */
+struct xvsec_capabilities {
+	/** Number of VSEC capabilities supported by the device */
+	uint16_t	no_of_caps;
+	/** Vsec inforamtion */
+	struct xvsec_vsec_info vsec_info[MAX_CAPABILITIES_SUPPORTED];
+};
+
+/**
+ * Capability list operation code to use in ioctls
+ */
+#define CODE_XVSEC_GET_CAP_LIST			0
+
+/**
+ * Device Info operation code to use in ioctls
+ */
+#define CODE_XVSEC_GET_DEV_INFO			1
+
+/**
+ * ioctl code for retrieving the XVSEC capability list
+ */
+#define IOC_XVSEC_GET_CAP_LIST \
+	_IOW(XVSEC_IOC_MAGIC, CODE_XVSEC_GET_CAP_LIST, \
+	struct xvsec_capabilities *)
+
+/**
+ * ioctl code for retrieving the Device information
+ */
+#define IOC_XVSEC_GET_DEVICE_INFO \
+	_IOWR(XVSEC_IOC_MAGIC, CODE_XVSEC_GET_DEV_INFO, \
+	union device_info *)
+
+#endif /* __XVSEC_DRV_H__ */

XVSEC/linux-kernel/drv/xvsec_drv_int.h

+/*
+ * This file is part of the XVSEC driver for Linux
+ *
+ * Copyright (c) 2020,  Xilinx, Inc.
+ * All rights reserved.
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef __XVSEC_DRV_INT_H__
+#define __XVSEC_DRV_INT_H__
+
+#include "xvsec_cdev.h"
+
+/**
+ * @file xvsec_drv_int.h
+ *
+ * Xilinx XVSEC Driver Library Definitions
+ *
+ * Header file *xvsec_drv_int.h* defines data structures
+ * needed for driver implementation
+ *
+ * These data structures are purely internal to the driver
+ * and not meant to user
+ */
+
+/**
+ * XILINX PCIe vendor ID
+ */
+#define XILINX_VENDOR_ID		(uint16_t)(0x10ee)
+
+#define XVSEC_EXT_CAP_VSEC_ID		(0x000B)
+
+#define XVSEC_MCAP_VSEC_ID		(0x0001)
+#define XVSEC_XVC_DEBUG_VSEC_ID		(0x0008)
+#define XVSEC_SCID_VSEC_ID		(0x0010)
+#define XVSEC_ALF_VSEC_ID		(0x0020)
+#define XVSEC_SWITCH_VSEC_ID		(0x0040)
+#define XVSEC_NULL_VSEC_ID		(0xFFFF)
+
+
+#define INVALID_DEVICE_INDEX		(uint8_t)(255)
+#define INVALID_OFFSET			(0xFFFF)
+
+/**
+ * Extended Capability Header Offset
+ */
+#define XVSEC_EXTENDED_HEADER_OFFSET	(0x0000)
+/**
+ * Vendor Specific Header Offset
+ *
+ * provides details about the VSEC information
+ */
+#define XVSEC_VENDOR_HEADER_OFFSET	(0x0004)
+#define XVSEC_VSEC_ID_SHIFT		0
+#define XVSEC_REV_ID_SHIFT		16
+#define XVSEC_VSEC_ID_POS		(0xFFFF << XVSEC_VSEC_ID_SHIFT)
+#define XVSEC_REV_ID_POS		(0xF << XVSEC_REV_ID_SHIFT)
+#define XVSEC_MCAP_ID			(0x0001)
+
+
+struct file_priv {
+	void *dev_ctx;
+};
+
+struct xvsec_ioctl_ops {
+	uint32_t cmd;
+	long (*fpfunction)(struct file *filep, uint32_t cmd, unsigned long arg);
+};
+
+struct vsec_context {
+	struct pci_dev		*pdev;
+	spinlock_t		lock;
+	struct cdev_info	char_dev;
+	int			fopen_cnt;
+	uint16_t		vsec_offset;
+	struct vsec_ops		*vsec_ops;
+	void			*vsec_priv;
+};
+
+struct vsec_ops {
+	uint32_t	vsec_id;
+	int (*vsec_module_init)(struct vsec_context *vsec_ctx);
+	void (*vsec_module_exit)(struct vsec_context *vsec_ctx);
+};
+
+struct context {
+	struct pci_dev			*pdev;
+	int				fopen_cnt;
+	spinlock_t			lock;
+	struct cdev_info		generic_cdev;
+	uint16_t			vsec_supported_cnt;
+	struct vsec_context		*vsec_ctx;
+	struct xvsec_capabilities	capabilities;
+};
+
+struct xvsec_dev {
+	uint32_t	dev_cnt;
+	struct context	*ctx;
+};
+
+extern struct class		*g_xvsec_class;
+
+int xvsec_mcap_module_init(struct vsec_context *dev_ctx);
+void xvsec_mcap_module_exit(struct vsec_context *dev_ctx);
+
+#endif /* __XVSEC_DRV_INT_H__ */

XVSEC/linux-kernel/drv/xvsec_cdev_int.h → XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.h

 /*
  * This file is part of the XVSEC driver for Linux
  *
- * Copyright (c) 2018,  Xilinx, Inc.
+ * Copyright (c) 2020,  Xilinx, Inc.
  * All rights reserved.
  *
  * This source code is free software; you can redistribute it and/or modify it
@@ -17,14 +17,21 @@
  * the file called "COPYING".
  */
 
-#ifndef __XVSEC_CDEV_INT_H__
-#define __XVSEC_CDEV_INT_H__
+#ifndef __XVSEC_MCAP_US_H__
+#define __XVSEC_MCAP_US_H__
+
+/**
+ * @file xvsec_mcap_us.h
+ *
+ * Xilinx XVSEC MCAP US/US+ Driver Library  Definitions
+ *
+ * Header file *xvsec_mcap_us.h* defines data structures & register
+ * definitions needed to implement the MCAP version 1 driver
+ *
+ * These data structures and register definitions can be used by
+ * XVSEC MCAP common driver
+ */
 
-#define XVSEC_NODE_NAME			"xvsec"
-#define INVALID_DEVICE_INDEX		(uint8_t)(255)
-#define INVALID_OFFSET			(0xFFFF)
-#define XVSEC_EXT_CAP_VSEC_ID		(0x000B)
-#define XVSEC_MCAP_VSEC_ID		(0x0001)
 
 #define MAX_FLEN						(300)
 #define RBT_WORD_LEN					(32)
@@ -58,6 +65,13 @@
 #define XVSEC_MCAP_READ_DATA_REG2	(0x0024)
 #define XVSEC_MCAP_READ_DATA_REG3	(0x0028)
 
+#define XVSEC_MCAP_DATA_REG_CNT		4
+
+#define XVSEC_MCAP_VSEC_ID_SHIFT	0
+#define XVSEC_MCAP_REV_ID_SHIFT		16
+#define XVSEC_MCAP_VSEC_ID_POS		(0xFFFF << XVSEC_MCAP_VSEC_ID_SHIFT)
+#define XVSEC_MCAP_REV_ID_POS		(0xF << XVSEC_MCAP_REV_ID_SHIFT)
+
 /* CTRL REG FIELDS */
 #define XVSEC_MCAP_CTRL_ENABLE		(1 << 0)
 #define XVSEC_MCAP_CTRL_RD_ENABLE	(1 << 1)
@@ -107,38 +121,38 @@ union type1_header {
 	uint32_t data;
 };
 
-struct context {
-	dev_t				dev_no;
-	int				major_no;
-	char				name[20];
-	struct class			*class;
-	struct cdev			cdev;
-	struct device			*sys_device;
-
-	struct pci_dev			*pdev;
-	int				mcap_cap_offset;
-	int				fopen_cnt;
-	struct xvsec_capabilities	capabilities;
-};
-
-struct xvsec_dev {
-	uint32_t	dev_cnt;
-	struct context	*ctx;
-};
-
-struct file_priv {
-	void *ctx;
-};
-
-struct ioctl_ops {
-	uint32_t cmd;
-	long (*fpfunction)(struct file *filep, uint32_t cmd, unsigned long arg);
-};
-
-
-extern struct xvsec_dev xvsec_dev;
-extern struct class *g_xvsec_class;
-extern int xvsec_initialize(struct pci_dev *pdev, uint32_t dev_idx);
-extern int xvsec_deinitialize(uint32_t dev_idx);
 
-#endif /* __XVSEC_CDEV_INT_H__ */
+int xvsec_mcap_reset(struct vsec_context *mcap_ctx);
+int xvsec_mcap_module_reset(struct vsec_context *mcap_ctx);
+int xvsec_mcap_full_reset(struct vsec_context *mcap_ctx);
+int xvsec_mcap_get_data_regs(struct vsec_context *mcap_ctx,
+	uint32_t regs[4]);
+int xvsec_mcap_get_regs(struct vsec_context *mcap_ctx,
+	union mcap_regs *regs);
+int xvsec_mcap_get_fpga_regs(struct vsec_context *mcap_ctx,
+	union fpga_cfg_regs *regs);
+int xvsec_mcap_program_bitstream(struct vsec_context *mcap_ctx,
+	union bitstream_file *bit_files);
+int xvsec_mcap_rd_cfg_addr(struct vsec_context *mcap_ctx,
+	union cfg_data *data);
+int xvsec_mcap_wr_cfg_addr(struct vsec_context *mcap_ctx,
+	union cfg_data *data);
+int xvsec_fpga_rd_cfg_addr(struct vsec_context *mcap_ctx,
+	union fpga_cfg_reg *cfg_reg);
+int xvsec_fpga_wr_cfg_addr(struct vsec_context *mcap_ctx,
+	union fpga_cfg_reg *cfg_reg);
+
+/*unsupported for US/US+ */
+int xvsec_mcapv1_axi_rd_addr(struct vsec_context *mcap_ctx,
+	union axi_reg_data *cfg_reg);
+int xvsec_mcapv1_axi_wr_addr(struct vsec_context *mcap_ctx,
+	union axi_reg_data *cfg_reg);
+int xvsec_mcapv1_file_download(struct vsec_context *mcap_ctx,
+	union file_download_upload *file);
+int xvsec_mcapv1_file_upload(struct vsec_context *mcap_ctx,
+	union file_download_upload *file);
+int xvsec_mcapv1_set_axi_cache_attr(struct vsec_context *mcap_ctx,
+	union axi_cache_attr *attr);
+
+
+#endif /* __XVSEC_MCAP_US_H__ */

XVSEC/linux-kernel/libxvsec/Makefile

@@ -2,7 +2,7 @@ SHELL = /bin/bash
 build_dir = $(PWD)/../build
 lib_dir = $(build_dir)/lib
 CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes
-CFLAGS += -I. -I../include -I../drv/
+CFLAGS += -I. -I../include -I../drv/ -I../drv/xvsec_mcap/
 CFLAGS += $(EXTRA_FLAGS)
 
 XVSEC = libxvsec

XVSEC/linux-kernel/libxvsec/version.h

@@ -2,7 +2,7 @@
  * This file is part of the XVSEC userspace library which provides the
  * userspace APIs to enable the XSEC driver functionality
  *
- * Copyright (c) 2018,  Xilinx, Inc.
+ * Copyright (c) 2018-2020,  Xilinx, Inc.
  * All rights reserved.
  *
  * This source code is licensed under BSD-style license (found in the
@@ -19,8 +19,8 @@
 #define XVSEC_LIB_MODULE_NAME	"xvsec"
 #define XVSEC_LIB_MODULE_DESC	"Xilinx VSEC Library"
 
-#define XVSEC_LIB_VERSION_MAJOR	2018
-#define XVSEC_LIB_VERSION_MINOR	3
+#define XVSEC_LIB_VERSION_MAJOR	2020
+#define XVSEC_LIB_VERSION_MINOR	2
 #define XVSEC_LIB_VERSION_PATCH	0
 
 #define XVSEC_LIB_VERSION	\