2020.1 QDMA Drivers Release

2020.1 QDMA Linux, DPDK and Windows Drivers are common drivers which supports the QDMA4.0 and QDMA3.1 Designs

QDMA/DPDK/RELEASE.txt

-RELEASE: 2019.2
+RELEASE: 2020.1
 ===============
 
-This release is based on DPDK v18.11 and contains QDMA poll mode driver and
-QDMA test application. This release is validated on QDMA 2019.2 patch based
-example design and QDMA 2019.1 based example design.
+This release is based on DPDK v19.11 in IOVA=PA mode and contains QDMA poll mode driver and
+QDMA test application. This release is validated on QDMA4.0 2020.1 based example design
+and QDMA3.1 2019.2 patch based example design.
 
-This release includes a patch file for dpdk-pktgen v3.6.1 that extends
+This release includes a patch file for dpdk-pktgen v19.12.0 that extends
 dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes
 and it disables the packet size classification logic in dpdk-pktgen to remove
 application overhead in performance measurement.
@@ -59,12 +59,24 @@ SUPPORTED FEATURES:
 	- Fix dma_from_device command in qdma_testapp application that requests more data from user logic than specified
 	- Fix memory offset calculation in dma_from_device and dma_to_device command in qdma_testapp application for MM mode
 
+2020.1 Updates
+---------------
+- Support DPDK v19.11 LTS
+- Support QDMA4.0 context and register changes
+- Common driver to support QDMA3.1 and QDMA4.0 designs
+- Updated and validated the example design with marker changes for QDMA4.0 and without marker changes for QDMA3.1
+- Added support for more than 256 functions 
+- Support multiple bus numbers on single card
+- CPU resource optimization in Tx and Rx data path
+
 KNOWN ISSUES:
 =============
-- Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors
+- On QDMA3.1 2019.2 design, sometimes completions are not received when C2H PIDX updates are held for 64 descriptors
+- On QDMA4.0 2020.1 design, HW errors are observed in dmesg console while validating the MM only design.
 - Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
 
 DRIVER LIMITATIONS:
 ===================
 - Big endian systems are not supported
 - For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
+- QDMA DPDK 2020.1 software is verified with IOVA=PA mode only
\ No newline at end of file

QDMA/DPDK/drivers/net/qdma/Makefile

 #   BSD LICENSE
 #
-#   Copyright(c) 2017-2019 Xilinx, Inc. All rights reserved.
+#   Copyright(c) 2017-2020 Xilinx, Inc. All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
 #   modification, are permitted provided that the following conditions
@@ -48,12 +48,23 @@ EXPORT_MAP := rte_pmd_qdma_version.map
 
 CFLAGS += -O3 -DDMA_BRAM_SIZE=$(BRAM_SIZE)
 #CFLAGS += -g
+ifeq ($(CONFIG_RTE_LIBRTE_QDMA_GCOV),y)
+  CFLAGS += -ftest-coverage -fprofile-arcs
+endif
 CFLAGS += $(WERROR_FLAGS)
 CFLAGS += -I$(RTE_SDK)/drivers/net/qdma/qdma_access/
+CFLAGS += -I$(RTE_SDK)/drivers/net/qdma/qdma_access/qdma_soft_access/
+CFLAGS += -I$(RTE_SDK)/drivers/net/qdma/qdma_access/eqdma_soft_access/
+CFLAGS += -I$(RTE_SDK)/drivers/net/qdma/qdma_access/qdma_s80_hard_access/
 CFLAGS += -I$(RTE_SDK)/drivers/net/qdma/
 ifeq ($(TEST_64B_DESC_BYPASS),1)
   CFLAGS += -DTEST_64B_DESC_BYPASS
 endif
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+  CFLAGS += -DQDMA_RX_VEC_X86_64
+  CFLAGS += -DQDMA_TX_VEC_X86_64
+endif
+CFLAGS += -DQDMA_LATENCY_OPTIMIZED
 
 # this lib depends upon:
 LDLIBS += -lpthread
@@ -71,13 +82,13 @@ SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_common.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_rxtx.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_xdebug.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_user.c
-SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/eqdma_soft_access/eqdma_soft_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_soft_access/qdma_soft_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_list.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_resource_mgmt.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_mbox_protocol.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_access_common.c
-SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_cpm_access.c
-SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_access/qdma_reg_dump.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_mbox.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += qdma_platform.c
 SRCS-$(CONFIG_RTE_LIBRTE_QDMA_PMD) += rte_pmd_qdma.c

QDMA/DPDK/drivers/net/qdma/qdma.h

 /*-
  * BSD LICENSE
  *
- * Copyright(c) 2017-2019 Xilinx, Inc. All rights reserved.
+ * Copyright(c) 2017-2020 Xilinx, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -36,13 +36,17 @@
 #include <stdbool.h>
 #include <rte_dev.h>
 #include <rte_ethdev.h>
+#include <rte_ethdev_driver.h>
 #include <rte_spinlock.h>
 #include <rte_log.h>
+#include <rte_cycles.h>
 #include <rte_byteorder.h>
 #include <rte_memzone.h>
 #include <linux/pci.h>
 #include "qdma_user.h"
-#include "qdma_reg.h"
+#include "qdma_soft_reg.h"
+#include "eqdma_soft_reg.h"
+#include "qdma_s80_hard_reg.h"
 #include "qdma_resource_mgmt.h"
 #include "qdma_mbox.h"
 #include "rte_pmd_qdma.h"
@@ -53,17 +57,11 @@
 #define DEFAULT_VF_CONFIG_BAR  (0)
 #define BAR_ID_INVALID         (-1)
 
-/* QDMA IP absolute maximum */
-#define QDMA_PF_MAX             4       /* 4 PFs */
-#define QDMA_VF_MAX             252
-#define QDMA_FUNC_ID_INVALID    (QDMA_PF_MAX + QDMA_VF_MAX)
+#define QDMA_FUNC_ID_INVALID    0xFFFF
 
 #define DEFAULT_QUEUE_BASE	(0)
-#define QDMA_QUEUES_NUM_MAX (2048)
-#define CPM_DEFAULT_QUEUE_BASE	(1)
-#define CPM_QDMA_QUEUES_NUM_MAX (2047)
 
-#define QDMA_MAX_BURST_SIZE (256)
+#define QDMA_MAX_BURST_SIZE (128)
 #define QDMA_MIN_RXBUFF_SIZE	(256)
 
 /* Descriptor Rings aligned to 4KB boundaries - only supported value */
@@ -170,7 +168,7 @@ struct qdma_cmpt_queue {
 struct qdma_rx_queue {
 	struct rte_mempool	*mb_pool; /**< mbuf pool to populate RX ring. */
 	void			*rx_ring; /**< RX ring virtual address */
-	struct qdma_ul_st_cmpt_ring	*cmpt_ring;
+	union qdma_ul_st_cmpt_ring	*cmpt_ring;
 	struct wb_status	*wb_status;
 	struct rte_mbuf		**sw_ring; /**< address of RX software ring. */
 	struct rte_eth_dev	*dev;
@@ -181,26 +179,28 @@ struct qdma_rx_queue {
 	uint16_t		nb_rx_desc; /**< number of RX descriptors. */
 	uint16_t		nb_rx_cmpt_desc;
 	uint32_t		queue_id; /**< RX queue index. */
+	uint64_t		mbuf_initializer; /**< value to init mbufs */
 
 	struct qdma_q_pidx_reg_info	q_pidx_info;
 	struct qdma_q_cmpt_cidx_reg_info cmpt_cidx_info;
 	struct qdma_pkt_stats	stats;
 
-	uint32_t		ep_addr;
+	uint16_t		port_id; /**< Device port identifier. */
 	uint8_t			status:1;
 	uint8_t			err:1;
 	uint8_t			st_mode:1; /**< dma-mode: MM or ST */
+	uint8_t			dump_immediate_data:1;
 	uint8_t			rx_deferred_start:1;
 	uint8_t			en_prefetch:1;
 	uint8_t			en_bypass:1;
-	uint8_t			dump_immediate_data:1;
 	uint8_t			en_bypass_prefetch:1;
 	uint8_t			dis_overflow_check:1;
 
-	enum rte_pmd_qdma_bypass_desc_len	bypass_desc_sz:7;
+	union qdma_ul_st_cmpt_ring cmpt_data[QDMA_MAX_BURST_SIZE];
 
-	uint16_t		port_id; /**< Device port identifier. */
+	enum rte_pmd_qdma_bypass_desc_len	bypass_desc_sz:7;
 	uint8_t			func_id; /**< RX queue index. */
+	uint32_t		ep_addr;
 
 	int8_t			ringszidx;
 	int8_t			cmpt_ringszidx;
@@ -208,9 +208,23 @@ struct qdma_rx_queue {
 	int8_t			threshidx;
 	int8_t			timeridx;
 	int8_t			triggermode;
+
 	const struct rte_memzone *rx_mz;
 	/* C2H stream mode, completion descriptor result */
 	const struct rte_memzone *rx_cmpt_mz;
+
+#ifdef QDMA_LATENCY_OPTIMIZED
+	/**< pend_pkt_moving_avg: average rate of packets received */
+	unsigned int pend_pkt_moving_avg;
+	/**< pend_pkt_avg_thr_hi: higher average threshold */
+	unsigned int pend_pkt_avg_thr_hi;
+	/**< pend_pkt_avg_thr_lo: lower average threshold */
+	unsigned int pend_pkt_avg_thr_lo;
+	/**< sorted_c2h_cntr_idx: sorted c2h counter index */
+	unsigned char sorted_c2h_cntr_idx;
+	/**< c2h_cntr_monitor_cnt: c2h counter stagnant monitor count */
+	unsigned char c2h_cntr_monitor_cnt;
+#endif //QDMA_LATENCY_OPTIMIZED
 };
 
 /**
@@ -226,6 +240,7 @@ struct qdma_tx_queue {
 	uint16_t			nb_tx_desc; /* No of TX descriptors.*/
 	rte_spinlock_t			pidx_update_lock;
 	struct qdma_q_pidx_reg_info	q_pidx_info;
+	uint64_t			offloads; /* Tx offloads */
 
 	uint8_t				st_mode:1;/* dma-mode: MM or ST */
 	uint8_t				tx_deferred_start:1;
@@ -273,6 +288,11 @@ struct qdma_pci_dev {
 	uint32_t queue_base;
 	uint8_t func_id;  /* Function id */
 
+	/* DMA identifier used by the resource manager
+	 * for the DMA instances used by this driver
+	 */
+	uint32_t dma_device_index;
+
 	/* Device capabilities */
 	struct qdma_dev_attributes dev_cap;
 
@@ -288,13 +308,14 @@ struct qdma_pci_dev {
 	uint8_t en_desc_prefetch:1;
 
 	/* Reset state */
+	uint8_t reset_in_progress;
 	enum reset_state_t reset_state;
 
 	/* Hardware version info*/
 	uint32_t vivado_rel:4;
 	uint32_t rtl_version:4;
 	uint32_t device_type:4;
-	uint32_t versal_ip_type:4;
+	uint32_t ip_type:4;
 
 	struct queue_info *q_info;
 	struct qdma_dev_mbox mbox;
@@ -304,42 +325,32 @@ struct qdma_pci_dev {
 	uint32_t g_c2h_cnt_th[QDMA_NUM_C2H_COUNTERS];
 	uint32_t g_c2h_buf_sz[QDMA_NUM_C2H_BUFFER_SIZES];
 	uint32_t g_c2h_timer_cnt[QDMA_NUM_C2H_TIMERS];
+#ifdef QDMA_LATENCY_OPTIMIZED
+	uint32_t sorted_idx_c2h_cnt_th[QDMA_NUM_C2H_COUNTERS];
+#endif //QDMA_LATENCY_OPTIMIZED
 	void	**cmpt_queues;
 	/*Pointer to QDMA access layer function pointers*/
 	struct qdma_hw_access *hw_access;
 
 	struct qdma_vf_info *vfinfo;
 	uint8_t vf_online_count;
+
+	int16_t tx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
+	int16_t rx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 };
 
 void qdma_dev_ops_init(struct rte_eth_dev *dev);
-uint32_t qdma_read_reg(uint64_t addr);
-void qdma_write_reg(uint64_t addr, uint32_t val);
+uint32_t qdma_read_reg(uint64_t reg_addr);
+void qdma_write_reg(uint64_t reg_addr, uint32_t val);
 void qdma_txq_pidx_update(void *arg);
 int qdma_pf_csr_read(struct rte_eth_dev *dev);
 int qdma_vf_csr_read(struct rte_eth_dev *dev);
 
-void qdma_dev_close(struct rte_eth_dev *dev);
-int qdma_dev_stats_get(struct rte_eth_dev *dev,
-			      struct rte_eth_stats *eth_stats);
-int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
-				uint16_t nb_rx_desc, unsigned int socket_id,
-				const struct rte_eth_rxconf *rx_conf,
-				struct rte_mempool *mb_pool);
-int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
-				uint16_t nb_tx_desc, unsigned int socket_id,
-				const struct rte_eth_txconf *tx_conf);
-void qdma_dev_rx_queue_release(void *rqueue);
-void qdma_dev_tx_queue_release(void *tqueue);
 uint8_t qmda_get_desc_sz_idx(enum rte_pmd_qdma_bypass_desc_len);
-int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-int qdma_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-int qdma_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
-int qdma_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
-int qdma_vf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-int qdma_vf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-int qdma_vf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
-int qdma_vf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
+int qdma_vf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid);
+int qdma_vf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qid);
+int qdma_vf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid);
+int qdma_vf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid);
 
 int qdma_init_rx_queue(struct qdma_rx_queue *rxq);
 void qdma_reset_tx_queue(struct qdma_tx_queue *txq);
@@ -355,18 +366,12 @@ void qdma_inv_tx_queue_ctxts(struct rte_eth_dev *dev, uint32_t qid,
 				uint32_t mode);
 int qdma_identify_bars(struct rte_eth_dev *dev);
 int qdma_get_hw_version(struct rte_eth_dev *dev);
-/* implemented in rxtx.c */
-uint16_t qdma_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
-				uint16_t nb_pkts);
-uint16_t qdma_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
-				uint16_t nb_pkts);
-int qdma_dev_rx_descriptor_done(void *rx_queue, uint16_t exp_count);
 
+/* implemented in rxtx.c */
 uint16_t qdma_recv_pkts_st(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 				uint16_t nb_pkts);
 uint16_t qdma_recv_pkts_mm(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 				uint16_t nb_pkts);
-
 uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
 				uint16_t nb_pkts);
 uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
@@ -389,7 +394,7 @@ struct rte_memzone *qdma_zone_reserve(struct rte_eth_dev *dev,
 					int socket_id)
 {
 	char z_name[RTE_MEMZONE_NAMESIZE];
-	snprintf(z_name, sizeof(z_name), "%s%s%d_%d",
+	snprintf(z_name, sizeof(z_name), "%s%s%d_%u",
 			dev->device->driver->name, ring_name,
 			dev->data->port_id, queue_id);
 	return rte_memzone_reserve_aligned(z_name, (uint64_t)ring_size,

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h

+/*
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
+ */
+
+#ifndef EQDMA_ACCESS_H_
+#define EQDMA_ACCESS_H_
+
+#include "qdma_access_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * enum qdma_error_idx - qdma errors
+ */
+enum eqdma_error_idx {
+	/* Descriptor errors */
+	EQDMA_DSC_ERR_POISON,
+	EQDMA_DSC_ERR_UR_CA,
+	EQDMA_DSC_ERR_BCNT,
+	EQDMA_DSC_ERR_PARAM,
+	EQDMA_DSC_ERR_ADDR,
+	EQDMA_DSC_ERR_TAG,
+	EQDMA_DSC_ERR_FLR,
+	EQDMA_DSC_ERR_TIMEOUT,
+	EQDMA_DSC_ERR_DAT_POISON,
+	EQDMA_DSC_ERR_FLR_CANCEL,
+	EQDMA_DSC_ERR_DMA,
+	EQDMA_DSC_ERR_DSC,
+	EQDMA_DSC_ERR_RQ_CANCEL,
+	EQDMA_DSC_ERR_DBE,
+	EQDMA_DSC_ERR_SBE,
+	EQDMA_DSC_ERR_ALL,
+
+	/* TRQ Errors */
+	EQDMA_TRQ_ERR_CSR_UNMAPPED,
+	EQDMA_TRQ_ERR_VF_ACCESS,
+	EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT,
+	EQDMA_TRQ_ERR_QSPC_UNMAPPED,
+	EQDMA_TRQ_ERR_QID_RANGE,
+	EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT,
+	EQDMA_TRQ_ERR_ALL,
+
+	/* C2H Errors */
+	EQDMA_ST_C2H_ERR_MTY_MISMATCH,
+	EQDMA_ST_C2H_ERR_LEN_MISMATCH,
+	EQDMA_ST_C2H_ERR_SH_CMPT_DSC,
+	EQDMA_ST_C2H_ERR_QID_MISMATCH,
+	EQDMA_ST_C2H_ERR_DESC_RSP_ERR,
+	EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
+	EQDMA_ST_C2H_ERR_MSI_INT_FAIL,
+	EQDMA_ST_C2H_ERR_ERR_DESC_CNT,
+	EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
+	EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR,
+	EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR,
+	EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR,
+	EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR,
+	EQDMA_ST_C2H_ERR_AVL_RING_DSC,
+	EQDMA_ST_C2H_ERR_HDR_ECC_UNC,
+	EQDMA_ST_C2H_ERR_HDR_ECC_COR,
+	EQDMA_ST_C2H_ERR_ALL,
+
+	/* Fatal Errors */
+	EQDMA_ST_FATAL_ERR_MTY_MISMATCH,
+	EQDMA_ST_FATAL_ERR_LEN_MISMATCH,
+	EQDMA_ST_FATAL_ERR_QID_MISMATCH,
+	EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_WPL_DATA_PAR,
+	EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE,
+	EQDMA_ST_FATAL_ERR_HDR_ECC_UNC,
+	EQDMA_ST_FATAL_ERR_ALL,
+
+	/* H2C Errors */
+	EQDMA_ST_H2C_ERR_ZERO_LEN_DESC,
+	EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP,
+	EQDMA_ST_H2C_ERR_NO_DMA_DSC,
+	EQDMA_ST_H2C_ERR_SBE,
+	EQDMA_ST_H2C_ERR_DBE,
+	EQDMA_ST_H2C_ERR_PAR,
+	EQDMA_ST_H2C_ERR_ALL,
+
+	/* Single bit errors */
+	EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM,
+	EQDMA_SBE_1_ERR_TAG_ODD_RAM,
+	EQDMA_SBE_1_ERR_TAG_EVEN_RAM,
+	EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0,
+	EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1,
+	EQDMA_SBE_1_ERR_ALL,
+
+	/* Single bit errors */
+	EQDMA_SBE_ERR_MI_H2C0_DAT,
+	EQDMA_SBE_ERR_MI_H2C1_DAT,
+	EQDMA_SBE_ERR_MI_H2C2_DAT,
+	EQDMA_SBE_ERR_MI_H2C3_DAT,
+	EQDMA_SBE_ERR_MI_C2H0_DAT,
+	EQDMA_SBE_ERR_MI_C2H1_DAT,
+	EQDMA_SBE_ERR_MI_C2H2_DAT,
+	EQDMA_SBE_ERR_MI_C2H3_DAT,
+	EQDMA_SBE_ERR_H2C_RD_BRG_DAT,
+	EQDMA_SBE_ERR_H2C_WR_BRG_DAT,
+	EQDMA_SBE_ERR_C2H_RD_BRG_DAT,
+	EQDMA_SBE_ERR_C2H_WR_BRG_DAT,
+	EQDMA_SBE_ERR_FUNC_MAP,
+	EQDMA_SBE_ERR_DSC_HW_CTXT,
+	EQDMA_SBE_ERR_DSC_CRD_RCV,
+	EQDMA_SBE_ERR_DSC_SW_CTXT,
+	EQDMA_SBE_ERR_DSC_CPLI,
+	EQDMA_SBE_ERR_DSC_CPLD,
+	EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM,
+	EQDMA_SBE_ERR_TIMER_FIFO_RAM,
+	EQDMA_SBE_ERR_QID_FIFO_RAM,
+	EQDMA_SBE_ERR_WRB_COAL_DATA_RAM,
+	EQDMA_SBE_ERR_INT_CTXT_RAM,
+	EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM,
+	EQDMA_SBE_ERR_PFCH_CTXT_RAM,
+	EQDMA_SBE_ERR_WRB_CTXT_RAM,
+	EQDMA_SBE_ERR_PFCH_LL_RAM,
+	EQDMA_SBE_ERR_PEND_FIFO_RAM,
+	EQDMA_SBE_ERR_RC_RRQ_ODD_RAM,
+	EQDMA_SBE_ERR_ALL,
+
+	/* Double bit Errors */
+	EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM,
+	EQDMA_DBE_1_ERR_TAG_ODD_RAM,
+	EQDMA_DBE_1_ERR_TAG_EVEN_RAM,
+	EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0,
+	EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1,
+	EQDMA_DBE_1_ERR_ALL,
+
+	/* Double bit Errors */
+	EQDMA_DBE_ERR_MI_H2C0_DAT,
+	EQDMA_DBE_ERR_MI_H2C1_DAT,
+	EQDMA_DBE_ERR_MI_H2C2_DAT,
+	EQDMA_DBE_ERR_MI_H2C3_DAT,
+	EQDMA_DBE_ERR_MI_C2H0_DAT,
+	EQDMA_DBE_ERR_MI_C2H1_DAT,
+	EQDMA_DBE_ERR_MI_C2H2_DAT,
+	EQDMA_DBE_ERR_MI_C2H3_DAT,
+	EQDMA_DBE_ERR_H2C_RD_BRG_DAT,
+	EQDMA_DBE_ERR_H2C_WR_BRG_DAT,
+	EQDMA_DBE_ERR_C2H_RD_BRG_DAT,
+	EQDMA_DBE_ERR_C2H_WR_BRG_DAT,
+	EQDMA_DBE_ERR_FUNC_MAP,
+	EQDMA_DBE_ERR_DSC_HW_CTXT,
+	EQDMA_DBE_ERR_DSC_CRD_RCV,
+	EQDMA_DBE_ERR_DSC_SW_CTXT,
+	EQDMA_DBE_ERR_DSC_CPLI,
+	EQDMA_DBE_ERR_DSC_CPLD,
+	EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM,
+	EQDMA_DBE_ERR_TIMER_FIFO_RAM,
+	EQDMA_DBE_ERR_QID_FIFO_RAM,
+	EQDMA_DBE_ERR_WRB_COAL_DATA_RAM,
+	EQDMA_DBE_ERR_INT_CTXT_RAM,
+	EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM,
+	EQDMA_DBE_ERR_PFCH_CTXT_RAM,
+	EQDMA_DBE_ERR_WRB_CTXT_RAM,
+	EQDMA_DBE_ERR_PFCH_LL_RAM,
+	EQDMA_DBE_ERR_PEND_FIFO_RAM,
+	EQDMA_DBE_ERR_RC_RRQ_ODD_RAM,
+	EQDMA_DBE_ERR_ALL,
+
+	EQDMA_ERRS_ALL
+};
+
+struct eqdma_hw_err_info {
+	enum eqdma_error_idx idx;
+	const char *err_name;
+	uint32_t mask_reg_addr;
+	uint32_t stat_reg_addr;
+	uint32_t leaf_err_mask;
+	uint32_t global_err_mask;
+};
+
+
+int eqdma_init_ctxt_memory(void *dev_hndl);
+
+int eqdma_get_version(void *dev_hndl, uint8_t is_vf,
+		struct qdma_hw_version_info *version_info);
+
+int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
+			struct qdma_descq_sw_ctxt *ctxt,
+			enum qdma_hw_access_type access_type);
+
+int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
+				struct qdma_descq_hw_ctxt *ctxt,
+				enum qdma_hw_access_type access_type);
+
+int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h,
+		uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt,
+		enum qdma_hw_access_type access_type);
+
+int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid,
+			struct qdma_descq_prefetch_ctxt *ctxt,
+			enum qdma_hw_access_type access_type);
+
+int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid,
+			struct qdma_descq_cmpt_ctxt *ctxt,
+			enum qdma_hw_access_type access_type);
+
+int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index,
+			struct qdma_indirect_intr_ctxt *ctxt,
+			enum qdma_hw_access_type access_type);
+
+int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf,
+		char *buf, uint32_t buflen);
+
+int eqdma_dump_intr_context(void *dev_hndl,
+		struct qdma_indirect_intr_ctxt *intr_ctx,
+		int ring_index,
+		char *buf, uint32_t buflen);
+
+int eqdma_dump_queue_context(void *dev_hndl,
+		uint8_t st,
+		enum qdma_dev_q_type q_type,
+		struct qdma_descq_context *ctxt_data,
+		char *buf, uint32_t buflen);
+
+uint32_t eqdma_reg_dump_buf_len(void);
+
+int eqdma_context_buf_len(uint8_t st,
+		enum qdma_dev_q_type q_type, uint32_t *buflen);
+
+int eqdma_hw_error_process(void *dev_hndl);
+const char *eqdma_hw_get_error_name(enum qdma_error_idx err_idx);
+
+int eqdma_read_dump_queue_context(void *dev_hndl,
+		uint16_t qid_hw,
+		uint8_t st,
+		enum qdma_dev_q_type q_type,
+		char *buf, uint32_t buflen);
+
+int eqdma_get_device_attributes(void *dev_hndl,
+		struct qdma_dev_attributes *dev_info);
+
+int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf,
+		uint8_t func_id, uint8_t *user_bar);
+
+int eqdma_dump_config_reg_list(void *dev_hndl,
+		uint32_t num_regs,
+		struct qdma_reg_data *reg_list,
+		char *buf, uint32_t buflen);
+
+int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf,
+		uint16_t reg_rd_slot,
+		uint16_t *total_regs,
+		struct qdma_reg_data *reg_list);
+
+int eqdma_set_default_global_csr(void *dev_hndl);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EQDMA_ACCESS_H_ */

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef QDMA_ACCESS_ERRORS_H_
@@ -73,8 +45,9 @@ enum qdma_access_error_codes {
 	QDMA_ERR_MBOX_INV_TMR_TH,
 	QDMA_ERR_MBOX_INV_MSG,
 	QDMA_ERR_MBOX_SEND_BUSY,
-	QDMA_ERR_MOBX_NO_MSG_IN,
-	QDMA_ERR_MBOX_ALL_ZERO_MSG,			/* 24 */
+	QDMA_ERR_MBOX_NO_MSG_IN,
+	QDMA_ERR_MBOX_REG_READ_FAILED,
+	QDMA_ERR_MBOX_ALL_ZERO_MSG,			/* 25 */
 };
 
 #endif /* QDMA_ACCESS_H_ */

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef QDMA_ACCESS_EXPORT_H_
@@ -95,6 +67,31 @@ struct qdma_dev_attributes {
 /** qdma_dev_attributes structure size */
 #define QDMA_DEV_ATTR_STRUCT_SIZE	(sizeof(struct qdma_dev_attributes))
 
+/** global_csr_conf structure size */
+#define QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE	(sizeof(struct global_csr_conf))
+
+/**
+ * enum qdma_dev_type - To hold qdma device type
+ */
+enum qdma_dev_type {
+	QDMA_DEV_PF,
+	QDMA_DEV_VF
+};
+
+/**
+ * enum qdma_dev_q_type: Q type
+ */
+enum qdma_dev_q_type {
+	/** @QDMA_DEV_Q_TYPE_H2C: H2C Q */
+	QDMA_DEV_Q_TYPE_H2C,
+	/** @QDMA_DEV_Q_TYPE_C2H: C2H Q */
+	QDMA_DEV_Q_TYPE_C2H,
+	/** @QDMA_DEV_Q_TYPE_CMPT: CMPT Q */
+	QDMA_DEV_Q_TYPE_CMPT,
+	/** @QDMA_DEV_Q_TYPE_MAX: Total Q types */
+	QDMA_DEV_Q_TYPE_MAX
+};
+
 /**
  * @enum qdma_desc_size - QDMA queue descriptor size
  */
@@ -176,19 +173,12 @@ enum qdma_wrb_interval {
 };
 
 enum qdma_rtl_version {
-	/** @QDMA_RTL_1 - RTL 1  */
+	/** @QDMA_RTL_BASE - RTL Base  */
 	QDMA_RTL_BASE,
-	/** @QDMA_RTL_2 - RTL 2  */
-	QDMA_RTL_PATCH
-};
-
-enum qdma_versal_ip_type {
-	/** @QDMA_VERSAL_HARD_IP - Hard IP  */
-	QDMA_VERSAL_HARD_IP,
-	/** @QDMA_VERSAL_SOFT_IP - Soft IP  */
-	QDMA_VERSAL_SOFT_IP,
-	/** @QDMA_VERSAL_NONE - Not versal device  */
-	QDMA_VERSAL_NONE
+	/** @QDMA_RTL_PATCH - RTL Patch  */
+	QDMA_RTL_PATCH,
+	/** @QDMA_RTL_NONE - Not a valid RTL version */
+	QDMA_RTL_NONE,
 };
 
 enum qdma_vivado_release_id {
@@ -198,17 +188,31 @@ enum qdma_vivado_release_id {
 	QDMA_VIVADO_2019_1,
 	/** @QDMA_VIVADO_2019_2 - Vivado version 2019.2  */
 	QDMA_VIVADO_2019_2,
+	/** @QDMA_VIVADO_2020_1 - Vivado version 2020.1  */
+	QDMA_VIVADO_2020_1,
 	/** @QDMA_VIVADO_NONE - Not a valid Vivado version*/
 	QDMA_VIVADO_NONE
 };
 
+enum qdma_ip_type {
+	/** @QDMA_VERSAL_HARD_IP - Hard IP  */
+	QDMA_VERSAL_HARD_IP,
+	/** @QDMA_VERSAL_SOFT_IP - Soft IP  */
+	QDMA_VERSAL_SOFT_IP,
+	/** @QDMA_SOFT_IP - Hard IP  */
+	QDMA_SOFT_IP,
+	/** @EQDMA_SOFT_IP - Soft IP  */
+	EQDMA_SOFT_IP,
+	/** @QDMA_VERSAL_NONE - Not versal device  */
+	QDMA_NONE_IP
+};
+
+
 enum qdma_device_type {
 	/** @QDMA_DEVICE_SOFT - UltraScale+ IP's  */
 	QDMA_DEVICE_SOFT,
 	/** @QDMA_DEVICE_VERSAL -VERSAL IP  */
 	QDMA_DEVICE_VERSAL,
-	/** @QDMA_DEVICE_VERSAL_CPM5 - VERSAL CPM5  */
-	QDMA_DEVICE_VERSAL_CPM5,
 	/** @QDMA_DEVICE_NONE - Not a valid device  */
 	QDMA_DEVICE_NONE
 };

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef QDMA_VERSION_H_
 #define QDMA_VERSION_H_
 
 
-#define QDMA_VERSION_MAJOR	2019
-#define QDMA_VERSION_MINOR	2
-#define QDMA_VERSION_PATCH	76
+#define QDMA_VERSION_MAJOR	2020
+#define QDMA_VERSION_MINOR	1
+#define QDMA_VERSION_PATCH	0
 
 #define QDMA_VERSION_STR	\
 	__stringify(QDMA_VERSION_MAJOR) "." \

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #include "qdma_list.h"

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef QDMA_LIST_H_

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef QDMA_MBOX_PROTOCOL_H_
@@ -41,7 +13,7 @@
  */
 
 #include "qdma_platform_env.h"
-#include "qdma_access.h"
+#include "qdma_access_common.h"
 #include "qdma_resource_mgmt.h"
 
 #define QDMA_MBOX_VF_ONLINE			(1)
@@ -49,6 +21,7 @@
 #define QDMA_MBOX_VF_RESET			(2)
 #define QDMA_MBOX_PF_RESET_DONE		(3)
 #define QDMA_MBOX_PF_BYE			(4)
+#define QDMA_MBOX_VF_RESET_BYE            (5)
 
 /** mailbox register max */
 #define MBOX_MSG_REG_MAX		32
@@ -221,6 +194,17 @@ int qdma_mbox_compose_vf_reset_message(uint32_t *raw_data, uint8_t src_funcid,
 				uint8_t dest_funcid);
 
 /*****************************************************************************/
+/**
+ * qdma_mbox_compose_vf_reset_offline(): compose VF BYE for PF initiated RESET
+ *
+ * @func_id: own function id
+ * @raw_data: output raw message to be sent
+ *
+ * Return:	0  : success and < 0: failure
+ *****************************************************************************/
+int qdma_mbox_compose_vf_reset_offline(uint16_t func_id,
+				uint32_t *raw_data);
+/*****************************************************************************/
 /**
  * qdma_mbox_compose_pf_reset_done_message(): compose PF reset done message
  *
@@ -409,6 +393,19 @@ int qdma_mbox_compose_vf_qctxt_clear(uint16_t func_id,
 int qdma_mbox_compose_csr_read(uint16_t func_id,
 			       uint32_t *raw_data);
 
+/*****************************************************************************/
+/**
+ * qdma_mbox_compose_reg_read(): compose message to read the register values
+ *
+ * @func_id:   destination function id
+ * @group_num:  group number for the registers to read
+ * @raw_data: output raw message to be sent
+ *
+ * Return:	0  : success and < 0: failure
+ *****************************************************************************/
+int qdma_mbox_compose_reg_read(uint16_t func_id, uint16_t group_num,
+			       uint32_t *raw_data);
+
 /*****************************************************************************/
 /**
  * qdma_mbox_compose_vf_intr_ctxt_write(): compose interrupt ring context
@@ -520,11 +517,13 @@ uint8_t qdma_mbox_vf_parent_func_id_get(uint32_t *rcv_data);
  *
  * @rcv_data: mbox message recieved
  * @dev_cap: device capability information
+ * @dma_device_index: DMA Identifier to be read using the mbox.
  *
  * Return:	response status with dev info received to the sent message
  *****************************************************************************/
 int qdma_mbox_vf_dev_info_get(uint32_t *rcv_data,
-				struct qdma_dev_attributes *dev_cap);
+		struct qdma_dev_attributes *dev_cap,
+		uint32_t *dma_device_index);
 
 /*****************************************************************************/
 /**
@@ -549,6 +548,19 @@ int qdma_mbox_vf_qinfo_get(uint32_t *rcv_data, int *qbase, uint16_t *qmax);
  *****************************************************************************/
 int qdma_mbox_vf_csr_get(uint32_t *rcv_data, struct qdma_csr_info *csr);
 
+/*****************************************************************************/
+/**
+ * qdma_mbox_vf_reg_list_get(): get reg info from received message
+ *
+ * @rcv_data: mbox message recieved
+ * @num_regs: number of register read
+ * @reg_list: pointer to the register info
+ *
+ * Return:	response status received to the sent message
+ *****************************************************************************/
+int qdma_mbox_vf_reg_list_get(uint32_t *rcv_data,
+		uint16_t *num_regs, struct qdma_reg_data *reg_list);
+
 /*****************************************************************************/
 /**
  * qdma_mbox_vf_context_get(): get queue context info from received message

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef LIBQDMA_QDMA_PLATFORM_H_
 #define LIBQDMA_QDMA_PLATFORM_H_
 
-#include "qdma_access.h"
-#include "qdma_access_export.h"
+#include "qdma_access_common.h"
 #include "qdma_platform_env.h"
 
 #ifdef __cplusplus
@@ -69,6 +40,14 @@ void *qdma_calloc(uint32_t num_blocks, uint32_t size);
  *****************************************************************************/
 void qdma_memfree(void *memptr);
 
+/*****************************************************************************/
+/**
+ * qdma_resource_lock_init() - Init lock to access resource management APIs
+ *
+ * @return	None
+ *****************************************************************************/
+int qdma_resource_lock_init(void);
+
 /*****************************************************************************/
 /**
  * qdma_resource_lock_take() - take lock to access resource management APIs

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of the copyright holder nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef __QDMA_REG_DUMP_H__
 #define __QDMA_REG_DUMP_H__
 
 #include "qdma_platform_env.h"
-#include "qdma_access.h"
+#include "qdma_access_common.h"
 
 #define DEBUGFS_DEV_INFO_SZ		(300)
 
-#define DEBUGFS_INTR_CNTX_SZ	(600)
+#define DEBUGFS_INTR_CNTX_SZ	(2048 * 2)
 #define DBGFS_ERR_BUFLEN		(64)
 #define DEBGFS_LINE_SZ			(81)
 #define DEBGFS_GEN_NAME_SZ		(40)
 #define REG_DUMP_SIZE_PER_LINE	(256)
-#define CTXT_ENTRY_NAME_SZ        64
 
-#define MAX_QDMA_CFG_REGS		(154)
-#define MAX_QDMA_SW_CTX_ENTRIES		(26)
-#define MAX_QDMA_HW_CTX_ENTRIES		(6)
-#define MAX_QDMA_CREDIT_CTX_ENTRIES	(1)
-#define MAX_QDMA_CMPT_CTX_ENTRIES	(23)
-#define MAX_QDMA_PFTCH_CTX_ENTRIES	(8)
+#define MAX_QDMA_CFG_REGS			(200)
 
 #define QDMA_MM_EN_SHIFT          0
 #define QDMA_CMPT_EN_SHIFT        1
@@ -80,29 +46,11 @@ struct xreg_info {
 	uint8_t shift;
 	uint8_t len;
 	uint8_t mode;
-};
-
-struct qctx_entry {
-	char name[CTXT_ENTRY_NAME_SZ];
-	uint32_t value;
+	uint8_t read_type;
 };
 
 extern struct xreg_info qdma_config_regs[MAX_QDMA_CFG_REGS];
 extern struct xreg_info qdma_cpm_config_regs[MAX_QDMA_CFG_REGS];
-extern struct qctx_entry sw_ctxt_entries[MAX_QDMA_SW_CTX_ENTRIES];
-extern struct qctx_entry hw_ctxt_entries[MAX_QDMA_HW_CTX_ENTRIES];
-extern struct qctx_entry credit_ctxt_entries[MAX_QDMA_CREDIT_CTX_ENTRIES];
-extern struct qctx_entry cmpt_ctxt_entries[MAX_QDMA_CMPT_CTX_ENTRIES];
-extern struct qctx_entry c2h_pftch_ctxt_entries[MAX_QDMA_PFTCH_CTX_ENTRIES];
 
-extern unsigned int qdma_reg_dump_buf_len(void);
-extern unsigned int qdma_context_buf_len(
-				char pfetch_valid, char cmpt_valid);
-extern void qdma_acc_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt);
-extern void qdma_acc_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt);
-extern void qdma_acc_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt);
-extern void qdma_acc_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt);
-extern void qdma_acc_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt
-					*pfetch_ctxt);
 
 #endif

QDMA/linux-kernel/libqdma/qdma_access/qdma_reg.h → QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h

 /*
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * The full GNU General Public License is included in this distribution in
- * the file called "COPYING".
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  */
 
-#ifndef QDMA_REG_H__
-#define QDMA_REG_H__
+#ifndef QDMA_SOFT_REG_H__
+#define QDMA_SOFT_REG_H__
 
 #ifdef __cplusplus
 extern "C" {
@@ -113,9 +101,15 @@ static inline uint32_t get_trailing_zeros(uint64_t value)
 #define FIELD_GET(mask, reg)    ((reg & mask) >> FIELD_SHIFT(mask))
 
 /* polling a register */
-#define	QDMA_REG_POLL_DFLT_INTERVAL_US	100		/* 100us per poll */
+#define	QDMA_REG_POLL_DFLT_INTERVAL_US	10		    /* 10us per poll */
 #define	QDMA_REG_POLL_DFLT_TIMEOUT_US	(500*1000)	/* 500ms */
 
+
+#define QDMA_H2C_THROT_DATA_THRESH       0x4000
+#define QDMA_THROT_EN_DATA               1
+#define QDMA_THROT_EN_REQ                0
+#define QDMA_H2C_THROT_REQ_THRESH        0x60
+
 /*
  * Q Context programming (indirect)
  */
@@ -158,12 +152,6 @@ enum ind_ctxt_cmd_sel {
 #define QDMA_OFFSET_IND_CTXT_CMD                            0x844
 #define     QDMA_IND_CTXT_CMD_BUSY_MASK                     0x1
 
-
-/* ------------------------ indirect register context fields -----------*/
-
-#define QDMA_INDRIECT_PROG_OP_TIMEOUT_US                    (500*1000)
-#define QDMA_IND_CTXT_DATA_NUM_REGS                         8
-
 /** QDMA_IND_REG_SEL_FMAP */
 #define QDMA_FMAP_CTXT_W1_QID_MAX_MASK                      GENMASK(11, 0)
 #define QDMA_FMAP_CTXT_W0_QID_MASK                          GENMASK(10, 0)
@@ -462,6 +450,10 @@ enum ind_ctxt_cmd_sel {
 #define     QDMA_GLBL2_MM_CMPT_EN_MASK                      BIT(2)
 #define     QDMA_GLBL2_FLR_PRESENT_MASK                     BIT(1)
 #define     QDMA_GLBL2_MAILBOX_EN_MASK                      BIT(0)
+#define     QDMA_GLBL2_DEVICE_ID_MASK                       GENMASK(31, 28)
+#define     QDMA_GLBL2_VIVADO_RELEASE_MASK                  GENMASK(27, 24)
+#define     QDMA_GLBL2_VERSAL_IP_MASK                       GENMASK(23, 20)
+#define     QDMA_GLBL2_RTL_VERSION_MASK                     GENMASK(19, 16)
 #define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ0                      0x1B8
 #define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ1                      0x1BC
 #define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR0                     0x1C0
@@ -481,10 +473,11 @@ enum ind_ctxt_cmd_sel {
 /* VF qdma version */
 #define QDMA_OFFSET_VF_VERSION                              0x1014
 #define QDMA_OFFSET_PF_VERSION                              0x2414
-#define     QDMA_GLBL2_DEVICE_TYPE                       GENMASK(15, 12)
-#define     QDMA_GLBL2_VIVADO_RELEASE_MASK               GENMASK(11, 8)
-#define     QDMA_GLBL2_VERSAL_IP_STATE                  GENMASK(7, 4)
-#define     QDMA_GLBL2_RTL_VERSION_MASK                  GENMASK(3, 0)
+#define     QDMA_GLBL2_VF_UNIQUE_ID_MASK                    GENMASK(31, 16)
+#define     QDMA_GLBL2_VF_DEVICE_ID_MASK                    GENMASK(15, 12)
+#define     QDMA_GLBL2_VF_VIVADO_RELEASE_MASK               GENMASK(11, 8)
+#define     QDMA_GLBL2_VF_VERSAL_IP_MASK                    GENMASK(7, 4)
+#define     QDMA_GLBL2_VF_RTL_VERSION_MASK                  GENMASK(3, 0)
 
 
 /* ------------------------- QDMA_TRQ_SEL_QUEUE_PF (0x18000) ----------------*/
@@ -655,8 +648,11 @@ enum ind_ctxt_cmd_sel {
 #define     QDMA_DBE_ERR_H2C_PEND_FIFO_MASK                 BIT(31)
 #define     QDMA_DBE_ERR_ALL_MASK                           0xFFFFFF11
 
+#define QDMA_OFFSET_MBOX_BASE_VF                            0x1000
+#define QDMA_OFFSET_MBOX_BASE_PF                            0x2400
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* ifndef QDMA_REG_H__ */
+#endif /* ifndef QDMA_SOFT_REG_H__ */

QDMA/DPDK/drivers/net/qdma/qdma_log.h

 /*-
  * BSD LICENSE
  *
- * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions