2022.1.1 patch: VF 4K queue support for CPM5 provided RTL support is available

2022.1.1 patch: VF 4K queue support for CPM5 provided RTL support is available

QDMA/DPDK/RELEASE

-RELEASE: 2022.1
-===============
+RELEASE: 2022.1.1
+=================
 
 This release is based on DPDK v20.11 and contains QDMA poll mode driver and
 QDMA test application.
@@ -97,11 +97,16 @@ CPM5
 	- Debug register dump for ST and MM Errors
 	- Dual Instance support
 
+2022.1.1 Patch Updates
+----------------------
+- Added VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added.
+
 KNOWN ISSUE:
 ============
 - CPM5 Only
-	- Sufficient host memory is required to accommodate 4K queues. Tested only upto 2048 queues with our test environment though driver supports 4K queues.
+	- Sufficient host memory is required to accommodate 4K queues. Tested only upto 2048 queues for PFs with our test environment though driver supports 4K queues.
 	- Tandem Boot support not available completely
+	- VF 4K queue support is not fully verified due to pdi issues
 
 - All Designs
 	- Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c

@@ -1462,6 +1462,15 @@ static struct eqdma_cpm5_hw_err_info
 		GLBL_ERR_STAT_ERR_H2C_MM_0_MASK,
 		&eqdma_cpm5_mm_h2c0_err_process
 	},
+	{
+		EQDMA_CPM5_MM_H2C0_RD_HDR_ADR_ERR,
+		"MM H2C0 Read cmpt hdr address mismatch Error",
+		EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR,
+		EQDMA_CPM5_H2C_MM_STATUS_ADDR,
+		H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK,
+		GLBL_ERR_STAT_ERR_H2C_MM_0_MASK,
+		&eqdma_cpm5_mm_h2c0_err_process
+	},
 	{
 		EQDMA_CPM5_MM_H2C0_RD_FLR_ERR,
 		"MM H2C0 Read flr Error",

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h

@@ -233,11 +233,16 @@ struct eqdma_cpm5_hw_err_info {
 	void (*eqdma_cpm5_hw_err_process)(void *dev_hndl);
 };
 
+#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED
+#define EQDMA_CPM5_OFFSET_VF_VERSION          0x21014
+#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF        0x21000
+#else
 #define EQDMA_CPM5_OFFSET_VF_VERSION           0x5014
-#define EQDMA_CPM5_OFFSET_VF_USER_BAR         0x5018
+#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF         0x5000
+#endif
 
 #define EQDMA_CPM5_OFFSET_MBOX_BASE_PF         0x42400
-#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF         0x5000
+#define EQDMA_CPM5_OFFSET_VF_USER_BAR          0x5018
 
 #define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK         GENMASK_ULL(63, 38)
 #define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK         GENMASK_ULL(37, 6)

QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c

@@ -1458,6 +1458,15 @@ static struct eqdma_hw_err_info eqdma_err_info[EQDMA_ERRS_ALL] = {
 		GLBL_ERR_STAT_ERR_H2C_MM_0_MASK,
 		&eqdma_mm_h2c0_err_process
 	},
+	{
+		EQDMA_MM_H2C0_RD_HDR_ADR_ERR,
+		"MM H2C0 Read cmpt hdr address mismatch Error",
+		EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR,
+		EQDMA_H2C_MM_STATUS_ADDR,
+		H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK,
+		GLBL_ERR_STAT_ERR_H2C_MM_0_MASK,
+		&eqdma_mm_h2c0_err_process
+	},
 	{
 		EQDMA_MM_H2C0_RD_FLR_ERR,
 		"MM H2C0 Read flr Error",

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c

@@ -34,9 +34,9 @@
 #include "qdma_platform.h"
 #include "qdma_soft_reg.h"
 #include "qdma_soft_access.h"
-#include "qdma_cpm4_access.h"
+#include "qdma_cpm4_access/qdma_cpm4_access.h"
 #include "eqdma_soft_access.h"
-#include "eqdma_cpm5_access.h"
+#include "eqdma_cpm5_access/eqdma_cpm5_access.h"
 #include "qdma_reg_dump.h"
 
 #ifdef ENABLE_WPP_TRACING
@@ -52,7 +52,8 @@
  */
 enum qdma_ip {
 	QDMA_OR_VERSAL_IP,
-	EQDMA_IP
+	EQDMA_IP,
+	EQDMA_CPM5_IP
 };
 
 
@@ -575,8 +576,14 @@ static int qdma_is_config_bar(void *dev_hndl, uint8_t is_vf, enum qdma_ip *ip)
 		if (FIELD_GET(QDMA_GLBL2_VF_UNIQUE_ID_MASK, reg_val)
 				!= QDMA_MAGIC_NUMBER) {
 			/* Its either QDMA or Versal */
+
+#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED
+			*ip = EQDMA_CPM5_IP;
+			reg_addr = EQDMA_CPM5_OFFSET_VF_VERSION;
+#else
 			*ip = EQDMA_IP;
 			reg_addr = EQDMA_OFFSET_VF_VERSION;
+#endif
 			reg_val = qdma_reg_read(dev_hndl, reg_addr);
 		} else {
 			*ip = QDMA_OR_VERSAL_IP;
@@ -1282,8 +1289,11 @@ int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf,
 
 	if (ip == EQDMA_IP)
 		hw_access->qdma_get_version = &eqdma_get_version;
+	else if (ip == EQDMA_CPM5_IP)
+		hw_access->qdma_get_version = &eqdma_cpm5_get_version;
 	else
 		hw_access->qdma_get_version = &qdma_get_version;
+
 	hw_access->qdma_init_ctxt_memory = &qdma_init_ctxt_memory;
 	hw_access->qdma_fmap_conf = &qdma_fmap_conf;
 	hw_access->qdma_sw_ctx_conf = &qdma_sw_ctx_conf;

QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h

@@ -36,7 +36,7 @@
 
 #define QDMA_VERSION_MAJOR	2022
 #define QDMA_VERSION_MINOR	1
-#define QDMA_VERSION_PATCH	0
+#define QDMA_VERSION_PATCH	2
 
 #define QDMA_VERSION_STR	\
 	__stringify(QDMA_VERSION_MAJOR) "." \

QDMA/DPDK/drivers/net/qdma/version.h

@@ -38,7 +38,7 @@
 
 #define QDMA_PMD_MAJOR		2022
 #define QDMA_PMD_MINOR		1
-#define QDMA_PMD_PATCHLEVEL	0
+#define QDMA_PMD_PATCHLEVEL	1
 
 #define QDMA_PMD_VERSION      \
 	qdma_stringify(QDMA_PMD_MAJOR) "." \