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Michael Black
OpenXG UE
Commits
439ee072
Commit
439ee072
authored
Nov 16, 2016
by
Elena_Lukashova
Browse files
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Plain Diff
Fixing DCI overwritinng during retransmissions.
Modifying some printouts into the file.
parent
6c4d2cbd
Changes
3
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
137 additions
and
62 deletions
+137
-62
openair1/PHY/LTE_TRANSPORT/dci_tools.c
openair1/PHY/LTE_TRANSPORT/dci_tools.c
+3
-1
openair1/PHY/LTE_TRANSPORT/dlsch_demodulation.c
openair1/PHY/LTE_TRANSPORT/dlsch_demodulation.c
+3
-0
openair1/SIMULATION/LTE_PHY/dlsim.c
openair1/SIMULATION/LTE_PHY/dlsim.c
+131
-61
No files found.
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @
439ee072
...
@@ -1510,7 +1510,9 @@ int generate_eNB_dlsch_params_from_dci(int frame,
...
@@ -1510,7 +1510,9 @@ int generate_eNB_dlsch_params_from_dci(int frame,
if
((
rv2
==
1
)
&&
(
mcs2
==
0
))
{
if
((
rv2
==
1
)
&&
(
mcs2
==
0
))
{
TB1_active
=
0
;
TB1_active
=
0
;
}
}
#ifdef DEBUG_HARQ
printf
(
"RV0 = %d, RV1 = %d. MCS0 = %d, MCS1=%d
\n
"
,
rv1
,
rv2
,
mcs1
,
mcs2
);
#endif
if
(
TB0_active
&&
TB1_active
&&
tbswap
==
0
)
{
if
(
TB0_active
&&
TB1_active
&&
tbswap
==
0
)
{
dlsch0
=
dlsch
[
0
];
dlsch0
=
dlsch
[
0
];
dlsch1
=
dlsch
[
1
];
dlsch1
=
dlsch
[
1
];
...
...
openair1/PHY/LTE_TRANSPORT/dlsch_demodulation.c
View file @
439ee072
...
@@ -149,6 +149,9 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
...
@@ -149,6 +149,9 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
codeword_TB1
=
dlsch_ue
[
1
]
->
harq_processes
[
harq_pid
]
->
codeword
;
codeword_TB1
=
dlsch_ue
[
1
]
->
harq_processes
[
harq_pid
]
->
codeword
;
dlsch0_harq
=
dlsch_ue
[
codeword_TB0
]
->
harq_processes
[
harq_pid
];
dlsch0_harq
=
dlsch_ue
[
codeword_TB0
]
->
harq_processes
[
harq_pid
];
dlsch1_harq
=
dlsch_ue
[
codeword_TB1
]
->
harq_processes
[
harq_pid
];
dlsch1_harq
=
dlsch_ue
[
codeword_TB1
]
->
harq_processes
[
harq_pid
];
#ifdef DEBUG_HARQ
printf
(
"I am assuming both CW active
\n
"
);
#endif
}
}
else
if
((
dlsch_ue
[
0
]
->
harq_processes
[
harq_pid
]
->
status
==
ACTIVE
)
&&
else
if
((
dlsch_ue
[
0
]
->
harq_processes
[
harq_pid
]
->
status
==
ACTIVE
)
&&
(
dlsch_ue
[
1
]
->
harq_processes
[
harq_pid
]
->
status
!=
ACTIVE
)
)
{
(
dlsch_ue
[
1
]
->
harq_processes
[
harq_pid
]
->
status
!=
ACTIVE
)
)
{
...
...
openair1/SIMULATION/LTE_PHY/dlsim.c
View file @
439ee072
...
@@ -266,7 +266,9 @@ int main(int argc, char **argv)
...
@@ -266,7 +266,9 @@ int main(int argc, char **argv)
double
thr_cw0_tm4
=
0
.
0
;
double
thr_cw0_tm4
=
0
.
0
;
double
thr_cw0_tm4_nonconst
=
0
.
0
;
double
thr_cw0_tm4_nonconst
=
0
.
0
;
double
thr_cw0
[
4
]
=
{
0
,
0
,
0
,
0
},
thr_cw1
[
4
]
=
{
0
,
0
,
0
,
0
},
thr_cw0_tot
=
0
.
0
,
thr_cw1_tot
=
0
.
0
;
double
thr_cw0
[
4
]
=
{
0
,
0
,
0
,
0
},
thr_cw1
[
4
]
=
{
0
,
0
,
0
,
0
},
thr_cw0_tot
=
0
.
0
,
thr_cw1_tot
=
0
.
0
;
double
tbs0_init
=
0
.
0
,
tbs1_init
=
0
.
0
,
rate0_init
=
0
.
0
,
rate1_init
=
0
.
0
;
unsigned
int
tbs0_init
=
0
,
tbs1_init
=
0
;
double
rate0_init
=
0
.
0
,
rate1_init
=
0
.
0
;
int
mcs0_init
=
0
,
mcs1_init
=
0
,
mod_order0_init
=
0
,
mod_order1_init
=
0
;
char
channel_model_input
[
17
]
=
"I"
;
char
channel_model_input
[
17
]
=
"I"
;
int
TB0_active
=
1
;
int
TB0_active
=
1
;
...
@@ -2195,6 +2197,9 @@ int main(int argc, char **argv)
...
@@ -2195,6 +2197,9 @@ int main(int argc, char **argv)
case
4
:
case
4
:
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
case
6
:
case
6
:
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2202,6 +2207,9 @@ int main(int argc, char **argv)
...
@@ -2202,6 +2207,9 @@ int main(int argc, char **argv)
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_1_5MHz_2A_TDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_1_5MHz_2A_TDD_t
));
break
;
break
;
case
25
:
case
25
:
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2209,6 +2217,9 @@ int main(int argc, char **argv)
...
@@ -2209,6 +2217,9 @@ int main(int argc, char **argv)
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_5MHz_2A_TDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_5MHz_2A_TDD_t
));
break
;
break
;
case
50
:
case
50
:
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2216,6 +2227,9 @@ int main(int argc, char **argv)
...
@@ -2216,6 +2227,9 @@ int main(int argc, char **argv)
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_10MHz_2A_TDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_10MHz_2A_TDD_t
));
break
;
break
;
case
100
:
case
100
:
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2295,27 +2309,39 @@ int main(int argc, char **argv)
...
@@ -2295,27 +2309,39 @@ int main(int argc, char **argv)
case
4
:
case
4
:
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
case
6
:
case
6
:
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_1_5MHz_2A_FDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_1_5MHz_2A_FDD_t
));
break
;
break
;
case
25
:
case
25
:
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_5MHz_2A_FDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_5MHz_2A_FDD_t
));
break
;
break
;
case
50
:
case
50
:
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
0
;
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_10MHz_2A_FDD_t
));
memcpy
(
&
dci_alloc
[
0
].
dci_pdu
[
0
],
&
DLSCH_alloc_pdu_1
[
0
],
sizeof
(
DCI2_10MHz_2A_FDD_t
));
break
;
break
;
case
100
:
case
100
:
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
0
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2431,13 +2457,16 @@ int main(int argc, char **argv)
...
@@ -2431,13 +2457,16 @@ int main(int argc, char **argv)
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
case
6
:
case
6
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
k
])
->
tpmi
=
2
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
k
])
->
tpmi
=
0
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
k
])
->
tpmi
=
4
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2447,6 +2476,9 @@ int main(int argc, char **argv)
...
@@ -2447,6 +2476,9 @@ int main(int argc, char **argv)
break
;
break
;
case
25
:
case
25
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_5MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2479,13 +2511,16 @@ int main(int argc, char **argv)
...
@@ -2479,13 +2511,16 @@ int main(int argc, char **argv)
break
;
break
;
case
50
:
case
50
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
0
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
4
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2495,13 +2530,16 @@ int main(int argc, char **argv)
...
@@ -2495,13 +2530,16 @@ int main(int argc, char **argv)
break
;
break
;
case
100
:
case
100
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
0
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
4
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2615,13 +2653,16 @@ int main(int argc, char **argv)
...
@@ -2615,13 +2653,16 @@ int main(int argc, char **argv)
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
switch
(
PHY_vars_eNB
->
lte_frame_parms
.
N_RB_DL
)
{
case
6
:
case
6
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
4
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_1_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2631,6 +2672,9 @@ int main(int argc, char **argv)
...
@@ -2631,6 +2672,9 @@ int main(int argc, char **argv)
break
;
break
;
case
25
:
case
25
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_5MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2662,13 +2706,16 @@ int main(int argc, char **argv)
...
@@ -2662,13 +2706,16 @@ int main(int argc, char **argv)
break
;
break
;
case
50
:
case
50
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
4
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_10MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2678,13 +2725,16 @@ int main(int argc, char **argv)
...
@@ -2678,13 +2725,16 @@ int main(int argc, char **argv)
break
;
break
;
case
100
:
case
100
:
if
(
TB0_active
==
1
)
{
if
(
TB0_active
==
1
)
{
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
mcs1
;
((
DCI2_20MHz_2A_TDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs2
=
mcs2
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
2
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi1
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
round
&
3
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv2
=
round
&
3
;
}
}
else
{
// deactivate TB0
else
{
// deactivate TB0
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
0
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
tpmi
=
4
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
mcs1
=
0
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
rv1
=
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
((
DCI2_20MHz_2A_FDD_t
*
)
&
DLSCH_alloc_pdu_1
[
0
])
->
ndi2
=
trials
&
1
;
...
@@ -2832,6 +2882,10 @@ int main(int argc, char **argv)
...
@@ -2832,6 +2882,10 @@ int main(int argc, char **argv)
rate1_init
=
rate
[
1
];
rate1_init
=
rate
[
1
];
tbs0_init
=
tbs
[
0
];
tbs0_init
=
tbs
[
0
];
tbs1_init
=
tbs
[
1
];
tbs1_init
=
tbs
[
1
];
mod_order0_init
=
get_Qm
(
PHY_vars_eNB
->
dlsch_eNB
[
0
][
0
]
->
harq_processes
[
0
]
->
mcs
);
mod_order1_init
=
get_Qm
(
PHY_vars_eNB
->
dlsch_eNB
[
0
][
1
]
->
harq_processes
[
0
]
->
mcs
);
mcs0_init
=
PHY_vars_eNB
->
dlsch_eNB
[
0
][
0
]
->
harq_processes
[
0
]
->
mcs
;
mcs1_init
=
PHY_vars_eNB
->
dlsch_eNB
[
0
][
1
]
->
harq_processes
[
0
]
->
mcs
;
}
}
generate_pilots
(
PHY_vars_eNB
,
generate_pilots
(
PHY_vars_eNB
,
...
@@ -3559,7 +3613,7 @@ int main(int argc, char **argv)
...
@@ -3559,7 +3613,7 @@ int main(int argc, char **argv)
if
(
ret
[
TB
]
<=
PHY_vars_UE
->
dlsch_ue
[
0
][
TB
]
->
max_turbo_iterations
)
{
//if CW0 is decoded, approach CW1
if
(
ret
[
TB
]
<=
PHY_vars_UE
->
dlsch_ue
[
0
][
0
]
->
max_turbo_iterations
)
{
//if CW0 is decoded, approach CW1
#ifdef DEBUG_HARQ
#ifdef DEBUG_HARQ
printf
(
"[DLSIM] TB%d is decoded
\n
"
,
TB
);
printf
(
"[DLSIM] TB%d is decoded
\n
"
,
TB
);
#endif
#endif
...
@@ -3976,7 +4030,7 @@ int main(int argc, char **argv)
...
@@ -3976,7 +4030,7 @@ int main(int argc, char **argv)
(
rx_type
==
rx_SIC_dual_stream
)
&&
(
TB0_active
==
1
))
{
(
rx_type
==
rx_SIC_dual_stream
)
&&
(
TB0_active
==
1
))
{
errs
[
1
][
round
]
++
;
errs
[
1
][
round
]
++
;
#ifdef DEBUG_HARQ
#ifdef DEBUG_HARQ
printf
(
"[DLSIM]
HERE OR NOT
TB%d is not decoded outside SIC loop, errs[TB%d][round %d] = %d
\n
"
,
1
,
1
,
round
,
errs
[
1
][
round
]);
printf
(
"[DLSIM] TB%d is not decoded outside SIC loop, errs[TB%d][round %d] = %d
\n
"
,
1
,
1
,
round
,
errs
[
1
][
round
]);
#endif
#endif
}
}
...
@@ -4192,9 +4246,10 @@ int main(int argc, char **argv)
...
@@ -4192,9 +4246,10 @@ int main(int argc, char **argv)
}
//trials
}
//trials
#ifdef DEBUG_HARQ
printf
(
"
\n
both failed round 0 = %d, both failed round 1 = %d, both failed round 2 = %d, both failed round 3 = %d
\n
"
,
resend_both
[
0
],
resend_both
[
1
],
resend_both
[
2
],
resend_both
[
3
]);
printf
(
"
\n
both failed round 0 = %d, both failed round 1 = %d, both failed round 2 = %d, both failed round 3 = %d
\n
"
,
resend_both
[
0
],
resend_both
[
1
],
resend_both
[
2
],
resend_both
[
3
]);
printf
(
" one failed round 0 = %d, one failed round 1 = %d, one failed round 2 = %d, one failed round 3 = %d
\n
"
,
resend_one
[
0
],
resend_one
[
1
],
resend_one
[
2
],
resend_one
[
3
]);
printf
(
" one failed round 0 = %d, one failed round 1 = %d, one failed round 2 = %d, one failed round 3 = %d
\n
"
,
resend_one
[
0
],
resend_one
[
1
],
resend_one
[
2
],
resend_one
[
3
]);
#endif
// round_trials[0]: number of code word : goodput the protocol
// round_trials[0]: number of code word : goodput the protocol
double
table_tx
[
time_vector_tx
.
size
];
double
table_tx
[
time_vector_tx
.
size
];
totable
(
table_tx
,
&
time_vector_tx
);
totable
(
table_tx
,
&
time_vector_tx
);
...
@@ -4366,7 +4421,7 @@ int main(int argc, char **argv)
...
@@ -4366,7 +4421,7 @@ int main(int argc, char **argv)
SNR
,
SNR
,
(
double
)
tx_lev_dB
+
10
*
log10
(
PHY_vars_UE
->
lte_frame_parms
.
ofdm_symbol_size
/
(
NB_RB
*
12
)),
(
double
)
tx_lev_dB
+
10
*
log10
(
PHY_vars_UE
->
lte_frame_parms
.
ofdm_symbol_size
/
(
NB_RB
*
12
)),
sigma2_dB
);
sigma2_dB
);
if
((
transmission_mode
!=
3
)
&&
(
transmission_mode
!=
4
)){
printf
(
"Errors (%d(%d)/%d %d(%d)/%d %d(%d)/%d %d(%d)/%d), Pe = (%e(%e),%e(%e),%e(%e),%e(%e)),"
printf
(
"Errors (%d(%d)/%d %d(%d)/%d %d(%d)/%d %d(%d)/%d), Pe = (%e(%e),%e(%e),%e(%e),%e(%e)),"
"dci_errors %d/%d, Pe = %e => effective rate %f (%2.1f%%,%f, %f), normalized delay %f (%f), "
"dci_errors %d/%d, Pe = %e => effective rate %f (%2.1f%%,%f, %f), normalized delay %f (%f), "
"throughput stream 0 = %f , throughput stream 1 = %f, system throughput = %f , rate 0 = %f , rate 1 = %f
\n
"
,
"throughput stream 0 = %f , throughput stream 1 = %f, system throughput = %f , rate 0 = %f , rate 1 = %f
\n
"
,
...
@@ -4406,14 +4461,29 @@ int main(int argc, char **argv)
...
@@ -4406,14 +4461,29 @@ int main(int argc, char **argv)
thr_cw0_tot
+
thr_cw1_tot
,
thr_cw0_tot
+
thr_cw1_tot
,
rate
[
0
],
rate
[
0
],
rate
[
1
]);
rate
[
1
]);
}
else
{
printf
(
"Errors (%d(%d)/%d %d(%d)/%d %d(%d)/%d %d(%d)/%d),"
"dci_errors %d/%d, thr TB0 = %f , thr TB1 = %f, overall thr = %f , rate 0 = %f , rate 1 = %f
\n
"
,
errs
[
0
][
0
],
errs
[
1
][
0
],
round_trials
[
0
][
0
],
errs
[
0
][
1
],
errs
[
1
][
1
],
round_trials
[
0
][
0
],
errs
[
0
][
2
],
errs
[
1
][
2
],
round_trials
[
0
][
0
],
errs
[
0
][
3
],
errs
[
1
][
3
],
round_trials
[
0
][
0
],
dci_errors
,
round_trials
[
0
][
0
],
thr_cw0_tot
,
thr_cw1_tot
,
thr_cw0_tot
+
thr_cw1_tot
,
rate0_init
,
rate1_init
);
}
if
(
print_perf
==
1
)
{
if
(
print_perf
==
1
)
{
printf
(
"eNB TX function statistics (per 1ms subframe)
\n\n
"
);
printf
(
"eNB TX function statistics (per 1ms subframe)
\n\n
"
);
...
@@ -4535,7 +4605,7 @@ int main(int argc, char **argv)
...
@@ -4535,7 +4605,7 @@ int main(int argc, char **argv)
dci_errors
);
dci_errors
);
}
}
else
{
else
{
fprintf
(
bler_fd
,
"%f;%d;%d;%d;%d;%f;%f;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%
f;%f;%f;%d
\n
"
,
fprintf
(
bler_fd
,
"%f;%d;%d;%d;%d;%f;%f;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%d;%
d;%d;%d;%d;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f
\n
"
,
SNR
,
SNR
,
mcs1
,
mcs1
,
mcs2
,
mcs2
,
...
@@ -4571,7 +4641,7 @@ int main(int argc, char **argv)
...
@@ -4571,7 +4641,7 @@ int main(int argc, char **argv)
thr_cw0
[
3
],
thr_cw0
[
3
],
thr_cw1
[
3
],
thr_cw1
[
3
],
thr_cw0
[
3
]
+
thr_cw1
[
3
],
thr_cw0
[
3
]
+
thr_cw1
[
3
],
thr_cw0
[
0
]
+
thr_cw0
[
1
]
+
thr_cw0
[
2
]
+
thr_cw0
[
4
]
+
thr_cw1
[
0
]
+
thr_cw1
[
1
]
+
thr_cw1
[
2
]
+
thr_cw1
[
3
]);
thr_cw0
[
0
]
+
thr_cw0
[
1
]
+
thr_cw0
[
2
]
+
thr_cw0
[
3
]
+
thr_cw1
[
0
]
+
thr_cw1
[
1
]
+
thr_cw1
[
2
]
+
thr_cw1
[
3
]);
}
}
...
...
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