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OpenXG UE
Commit 56aef229 authored by Sakthivel Velumani's avatar Sakthivel Velumani
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updated dci_pdu_rel15_t 

moved nr_dci_size out of scheduler_phytest
parent aa47e78e
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Showing with 191 additions and 184 deletions
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @ 56aef229
...@@ -596,8 +596,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -596,8 +596,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
// Format identifier // Format identifier
dci_pdu->format_indicator.nbits=1; size = 1;
size = dci_pdu->format_indicator.nbits;
// Carrier indicator // Carrier indicator
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
dci_pdu->carrier_indicator.nbits=3; dci_pdu->carrier_indicator.nbits=3;
...@@ -651,32 +650,23 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -651,32 +650,23 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
size += dci_pdu->zp_csi_rs_trigger.nbits; size += dci_pdu->zp_csi_rs_trigger.nbits;
// TB1- MCS 5, NDI 1, RV 2 // TB1- MCS 5, NDI 1, RV 2
dci_pdu->mcs[0].nbits = 5; size += 8;
dci_pdu->ndi[0].nbits = 1;
dci_pdu->rv[0].nbits = 2;
size += (dci_pdu->mcs[0].nbits + dci_pdu->ndi[0].nbits + dci_pdu->rv[0].nbits);
// TB2 // TB2
long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
if ((maxCWperDCI != NULL) && (maxCWperDCI == 2)) { if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) {
dci_pdu->mcs[1].nbits = 5; size += 8;
dci_pdu->ndi[1].nbits = 1;
dci_pdu->rv[1].nbits = 2;
size += (dci_pdu->mcs[1].nbits + dci_pdu->ndi[1].nbits + dci_pdu->rv[1].nbits);
} }
// HARQ PID // HARQ PID
dci_pdu->harq_pid.nbits = 4; size += 4;
size += dci_pdu->harq_pid.nbits;
// DAI // DAI
if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells
dci_pdu->dai.nbits = 4; dci_pdu->dai[0].nbits = 4;
size += dci_pdu->dai.nbits; size += dci_pdu->dai[0].nbits;
} }
// TPC PUCCH // TPC PUCCH
dci_pdu->tpc.nbits = 2; size += 2;
size += dci_pdu->tpc.nbits;
// PUCCH resource indicator // PUCCH resource indicator
dci_pdu->pucch_resource_indicator.nbits = 3; size += 3;
size += dci_pdu->pucch_resource_indicator.nbits;
// PDSCH to HARQ timing indicator // PDSCH to HARQ timing indicator
uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I)); dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
...@@ -710,8 +700,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -710,8 +700,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
size += dci_pdu->cbgfi.nbits; size += dci_pdu->cbgfi.nbits;
} }
// DMRS sequence init // DMRS sequence init
dci_pdu->dmrs_sequence_initialization.nbits = 1; size += 1;
size += dci_pdu->dmrs_sequence_initialization.nbits;
break; break;
case NR_DL_DCI_FORMAT_2_0: case NR_DL_DCI_FORMAT_2_0:
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ 56aef229
...@@ -343,17 +343,17 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -343,17 +343,17 @@ int configure_fapi_dl_pdu(int Mod_idP,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1; dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1;
dci_pdu_rel15[0].mcs[0].val = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
dci_pdu_rel15[0].tb_scaling.val = 1; dci_pdu_rel15[0].tb_scaling = 1;
dci_pdu_rel15[0].ra_preamble_index.val = 25; dci_pdu_rel15[0].ra_preamble_index = 25;
dci_pdu_rel15[0].format_indicator.val = 1; dci_pdu_rel15[0].format_indicator = 1;
dci_pdu_rel15[0].ndi[0].val = 1; dci_pdu_rel15[0].ndi = 1;
dci_pdu_rel15[0].rv[0].val = 0; dci_pdu_rel15[0].rv = 0;
dci_pdu_rel15[0].harq_pid.val = 0; dci_pdu_rel15[0].harq_pid = 0;
dci_pdu_rel15[0].dai.val = 2; dci_pdu_rel15[0].dai[0].val = 2;
dci_pdu_rel15[0].tpc.val = 2; dci_pdu_rel15[0].tpc = 2;
dci_pdu_rel15[0].pucch_resource_indicator.val = 7; dci_pdu_rel15[0].pucch_resource_indicator = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7; dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
...@@ -363,10 +363,10 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -363,10 +363,10 @@ int configure_fapi_dl_pdu(int Mod_idP,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
dci_pdu_rel15[0].time_domain_assignment.val, dci_pdu_rel15[0].time_domain_assignment.val,
dci_pdu_rel15[0].vrb_to_prb_mapping.val, dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs[0].val, dci_pdu_rel15[0].mcs,
dci_pdu_rel15[0].tb_scaling.val, dci_pdu_rel15[0].tb_scaling,
dci_pdu_rel15[0].ndi[0].val, dci_pdu_rel15[0].ndi,
dci_pdu_rel15[0].rv[0].val); dci_pdu_rel15[0].rv);
nr_configure_pdcch(pdcch_pdu_rel15, nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific 1, // ue-specific
...@@ -386,8 +386,7 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -386,8 +386,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
dci_formats[0] = NR_DL_DCI_FORMAT_1_0; dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
rnti_types[0] = NR_RNTI_C; rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
...@@ -425,23 +424,23 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr ...@@ -425,23 +424,23 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
dci_pdu_rel15->frequency_hopping_flag.val = 0; dci_pdu_rel15->frequency_hopping_flag.val = 0;
dci_pdu_rel15->mcs[0].val = 9; dci_pdu_rel15->mcs = 9;
dci_pdu_rel15->format_indicator.val = 0; dci_pdu_rel15->format_indicator = 0;
dci_pdu_rel15->ndi[0].val = 1; dci_pdu_rel15->ndi = 1;
dci_pdu_rel15->rv[0].val = 0; dci_pdu_rel15->rv = 0;
dci_pdu_rel15->harq_pid.val = 0; dci_pdu_rel15->harq_pid = 0;
dci_pdu_rel15->tpc.val = 2; dci_pdu_rel15->tpc = 2;
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->frequency_domain_assignment.val,
dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.val,
dci_pdu_rel15->frequency_hopping_flag.val, dci_pdu_rel15->frequency_hopping_flag.val,
dci_pdu_rel15->mcs[0].val, dci_pdu_rel15->mcs,
dci_pdu_rel15->tpc.val, dci_pdu_rel15->tpc,
dci_pdu_rel15->ndi[0].val, dci_pdu_rel15->ndi,
dci_pdu_rel15->rv[0].val); dci_pdu_rel15->rv);
dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0;
rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C;
...@@ -832,8 +831,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -832,8 +831,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
} }
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 56aef229
...@@ -544,7 +544,27 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -544,7 +544,27 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
} }
} }
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu_rel15,
nr_dci_format_t format) {
switch(format) {
case NR_DL_DCI_FORMAT_1_1:
//carrier indicator
//bwp indicator
//vrb to prb mapping
//bundling size indicator
//rate matching indicator
//ZP CSI-RS trigger
//dai
//antenna ports
//srs resource set
break;
}
}
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats, int *dci_formats,
int *rnti_types int *rnti_types
...@@ -557,9 +577,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -557,9 +577,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) { for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d];
AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize);
pdcch_pdu_rel15->PayloadSizeBits[d] = dci_size;
AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d]);
pos = 0; pos = 0;
/// Payload generation /// Payload generation
...@@ -583,20 +605,20 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -583,20 +605,20 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
// MCS // MCS
pos+=5; pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
LOG_D(MAC,"mcs[0] %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,dci_size-pos,*dci_pdu); LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
// TB scaling // TB scaling
pos+=2; pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling.val&0x3)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos);
LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling.val,dci_size-pos,*dci_pdu); LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
break; break;
case NR_RNTI_C: case NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
pos++; pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos);
LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator.val,1,N_RB,dci_size-pos,*dci_pdu); LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu);
// Freq domain assignment (275rb >> fsize = 16) // Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
...@@ -615,7 +637,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -615,7 +637,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
{ {
// ra_preamble_index 6 bits // ra_preamble_index 6 bits
pos+=6; pos+=6;
*dci_pdu |= ((dci_pdu_rel15->ra_preamble_index.val&0x3f)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos));
// UL/SUL indicator 1 bit // UL/SUL indicator 1 bit
pos++; pos++;
...@@ -623,11 +645,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -623,11 +645,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// SS/PBCH index 6 bits // SS/PBCH index 6 bits
pos+=6; pos+=6;
*dci_pdu |= ((dci_pdu_rel15->ss_pbch_index.val&0x3f)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos));
// prach_mask_index 4 bits // prach_mask_index 4 bits
pos+=4; pos+=4;
*dci_pdu |= ((dci_pdu_rel15->prach_mask_index.val&0xf)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos));
} //end if } //end if
...@@ -646,38 +668,38 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -646,38 +668,38 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
pos+=5; pos+=5;
*dci_pdu |= (dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,5,dci_size-pos,*dci_pdu); LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu);
// New data indicator 1bit // New data indicator 1bit
pos++; pos++;
*dci_pdu |= (dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos);
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi[0].val,1,dci_size-pos,*dci_pdu); LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; pos+=2;
*dci_pdu |= (dci_pdu_rel15->rv[0].val&0x3)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv[0].val,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; pos+=4;
*dci_pdu |= ((dci_pdu_rel15->harq_pid.val&0xf)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos));
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid.val,4,dci_size-pos,*dci_pdu); LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
// Downlink assignment index 2bit // Downlink assignment index 2bit
pos+=2; pos+=2;
*dci_pdu |= ((dci_pdu_rel15->dai.val&3)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos));
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai.val,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; pos+=2;
*dci_pdu |= ((dci_pdu_rel15->tpc.val&3)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos));
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc.val,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator.val&0x7)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos));
LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator.val,3,dci_size-pos,*dci_pdu); LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu);
// PDSCH-to-HARQ_feedback timing indicator 3bit // PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3; pos+=3;
...@@ -691,10 +713,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -691,10 +713,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Short Messages Indicator – 2 bits // Short Messages Indicator – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++);
// Short Messages – 8 bits // Short Messages – 8 bits
for (int i=0; i<8; i++) for (int i=0; i<8; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages.val>>(7-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
...@@ -706,11 +728,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -706,11 +728,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// TB scaling 2 bit // TB scaling 2 bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++);
break; break;
...@@ -727,16 +749,16 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -727,16 +749,16 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++);
break; break;
case NR_RNTI_TC: case NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
...@@ -748,23 +770,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -748,23 +770,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++);
// Downlink assignment index – 2 bits // Downlink assignment index – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUCCH – 2 bits // TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++);
// LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n",
...@@ -784,7 +806,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -784,7 +806,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
{ {
case NR_RNTI_C: case NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
...@@ -796,23 +818,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -796,23 +818,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor /* commented for now (RK): need to get this from BWP descriptor
...@@ -824,7 +846,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -824,7 +846,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
case NFAPI_NR_RNTI_TC: case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); *dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
...@@ -836,23 +858,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -836,23 +858,23 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* /*
...@@ -867,8 +889,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -867,8 +889,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
// Indicating a DL DCI format 1bit // Indicating a DL DCI format 1bit
pos=dci_pdu_rel15->format_indicator.nbits; pos=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&((1<<dci_pdu_rel15->format_indicator.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos);
// Carrier indicator // Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits; pos+=dci_pdu_rel15->carrier_indicator.nbits;
...@@ -904,45 +926,45 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -904,45 +926,45 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
//TB1 //TB1
// MCS 5bit // MCS 5bit
pos+=dci_pdu_rel15->mcs[0].nbits; pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&((1<<dci_pdu_rel15->mcs[0].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
// New data indicator 1bit // New data indicator 1bit
pos+=dci_pdu_rel15->ndi[0].nbits; pos+=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&((1<<dci_pdu_rel15->ndi[0].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos);
// Redundancy version 2bit // Redundancy version 2bit
pos+=dci_pdu_rel15->rv[0].nbits; pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[0].val&((1<<dci_pdu_rel15->rv[0].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
//TB2 //TB2
// MCS 5bit // MCS 5bit
pos+=dci_pdu_rel15->mcs[1].nbits; pos+=dci_pdu_rel15->mcs2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[1].val&((1<<dci_pdu_rel15->mcs[1].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<<dci_pdu_rel15->mcs2.nbits)-1))<<(dci_size-pos);
// New data indicator 1bit // New data indicator 1bit
pos+=dci_pdu_rel15->ndi[1].nbits; pos+=dci_pdu_rel15->ndi2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[1].val&((1<<dci_pdu_rel15->ndi[1].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<<dci_pdu_rel15->ndi2.nbits)-1))<<(dci_size-pos);
// Redundancy version 2bit // Redundancy version 2bit
pos+=dci_pdu_rel15->rv[1].nbits; pos+=dci_pdu_rel15->rv2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[1].val&((1<<dci_pdu_rel15->rv[1].nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<<dci_pdu_rel15->rv2.nbits)-1))<<(dci_size-pos);
// HARQ process number 4bit // HARQ process number 4bit
pos+=dci_pdu_rel15->harq_pid.nbits; pos+=4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid.val&((1<<dci_pdu_rel15->harq_pid.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
// Downlink assignment index // Downlink assignment index
pos+=dci_pdu_rel15->dai.nbits; pos+=dci_pdu_rel15->dai[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai.val&((1<<dci_pdu_rel15->dai.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<<dci_pdu_rel15->dai[0].nbits)-1))<<(dci_size-pos);
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=dci_pdu_rel15->tpc.nbits; pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc.val&((1<<dci_pdu_rel15->tpc.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos);
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=dci_pdu_rel15->pucch_resource_indicator.nbits; pos+=3;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator.val&((1<<dci_pdu_rel15->pucch_resource_indicator.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos);
// PDSCH-to-HARQ_feedback timing indicator // PDSCH-to-HARQ_feedback timing indicator
pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
...@@ -969,8 +991,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, ...@@ -969,8 +991,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos);
// DMRS sequence init // DMRS sequence init
pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; pos+=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<<dci_pdu_rel15->dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos);
} }
} }
} }
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ 56aef229
...@@ -130,7 +130,8 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -130,7 +130,8 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
NR_ServingCellConfigCommon_t *scc, NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp); NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats, int *dci_formats,
int *rnti_types); int *rnti_types);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 56aef229
...@@ -260,62 +260,59 @@ typedef struct { ...@@ -260,62 +260,59 @@ typedef struct {
typedef struct { typedef struct {
dci_field_t format_indicator; //1 bit uint8_t format_indicator; //1 bit
dci_field_t frequency_domain_assignment; //up to 16 bits uint8_t ra_preamble_index; //6 bits
dci_field_t time_domain_assignment; // 4 bits uint8_t ss_pbch_index; //6 bits
dci_field_t frequency_hopping_flag; //1 bit uint8_t prach_mask_index; //4 bits
uint8_t mcs; //5 bits
dci_field_t ra_preamble_index; //6 bits uint8_t ndi; //1 bit
dci_field_t ss_pbch_index; //6 bits uint8_t rv; //2 bits
dci_field_t prach_mask_index; //4 bits uint8_t harq_pid; //4 bits
uint8_t tpc; //2 bits
dci_field_t vrb_to_prb_mapping; //0 or 1 bit uint8_t short_messages_indicator; //2 bits
dci_field_t mcs[2]; //5 bits uint8_t short_messages; //8 bits
dci_field_t ndi[2]; //1 bit uint8_t tb_scaling; //2 bits
dci_field_t rv[2]; //2 bits uint8_t pucch_resource_indicator; //3 bits
dci_field_t harq_pid; //4 bits uint8_t dmrs_sequence_initialization; //1 bit
dci_field_t dai; //0, 2 or 4 bits uint8_t system_info_indicator; //1 bit
dci_field_t dai1; //1 or 2 bits
dci_field_t dai2; //0 or 2 bits uint8_t slot_format_indicator_count;
dci_field_t tpc; //2 bits uint8_t *slot_format_indicators;
dci_field_t pucch_resource_indicator; //3 bits
dci_field_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit each
dci_field_t short_messages_indicator; //2 bits
dci_field_t short_messages; //8 bits
dci_field_t tb_scaling; //2 bits
dci_field_t carrier_indicator; //0 or 3 bits
dci_field_t bwp_indicator; //0, 1 or 2 bits
dci_field_t prb_bundling_size_indicator; //0 or 1 bits
dci_field_t rate_matching_indicator; //0, 1 or 2 bits
dci_field_t zp_csi_rs_trigger; //0, 1 or 2 bits
dci_field_t transmission_configuration_indication; //0 or 3 bits
dci_field_t srs_request; //2 bits
dci_field_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
dci_field_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
dci_field_t dmrs_sequence_initialization; //0 or 1 bit
dci_field_t srs_resource_indicator;
dci_field_t precoding_information;
dci_field_t csi_request;
dci_field_t ptrs_dmrs_association;
dci_field_t beta_offset_indicator; //0 or 2 bits
dci_field_t slot_format_indicator_count;
dci_field_t *slot_format_indicators;
dci_field_t pre_emption_indication_count;
dci_field_t *pre_emption_indications; //14 bit
dci_field_t block_number_count;
dci_field_t *block_numbers;
dci_field_t ul_sul_indicator; //0 or 1 bit
dci_field_t antenna_ports;
uint8_t block_number_count;
uint8_t *block_numbers;
uint8_t padding;
dci_field_t mcs2; //variable
dci_field_t ndi2; //variable
dci_field_t rv2; //variable
dci_field_t frequency_domain_assignment; //variable
dci_field_t time_domain_assignment; //variable
dci_field_t frequency_hopping_flag; //variable
dci_field_t vrb_to_prb_mapping; //variable
dci_field_t dai[2]; //variable
dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable
dci_field_t carrier_indicator; //variable
dci_field_t bwp_indicator; //variable
dci_field_t prb_bundling_size_indicator; //variable
dci_field_t rate_matching_indicator; //variable
dci_field_t zp_csi_rs_trigger; //variable
dci_field_t transmission_configuration_indication; //variable
dci_field_t srs_request; //variable
dci_field_t cbgti; //variable
dci_field_t cbgfi; //variable
dci_field_t srs_resource_indicator; //variable
dci_field_t precoding_information; //variable
dci_field_t csi_request; //variable
dci_field_t ptrs_dmrs_association; //variable
dci_field_t beta_offset_indicator; //variable
dci_field_t cloded_loop_indicator; //variable
dci_field_t ul_sul_indicator; //variable
dci_field_t antenna_ports; //variable
dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
dci_field_t padding;
} dci_pdu_rel15_t; } dci_pdu_rel15_t;
......
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