Commit 5f872a32 authored by shahab SHARIATBAGHERI's avatar shahab SHARIATBAGHERI

DL Fixed Bug get TBS

parent 22ca90a5
...@@ -284,7 +284,7 @@ void _assign_rbs_required (module_id_t Mod_id, ...@@ -284,7 +284,7 @@ void _assign_rbs_required (module_id_t Mod_id,
nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id]; nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id];
if (nb_rbs_required[CC_id][UE_id] > nb_rbs_allowed_slice[CC_id][slice_id]) { if (nb_rbs_required[CC_id][UE_id] > nb_rbs_allowed_slice[CC_id][slice_id]) {
TBS = mac_xface->get_TBS_DL(flexran_get_ue_wcqi(Mod_id, UE_id), nb_rbs_allowed_slice[CC_id][slice_id]); TBS = mac_xface->get_TBS_DL(cqi_to_mcs[flexran_get_ue_wcqi(Mod_id, UE_id)], nb_rbs_allowed_slice[CC_id][slice_id]);
nb_rbs_required[CC_id][UE_id] = nb_rbs_allowed_slice[CC_id][slice_id]; nb_rbs_required[CC_id][UE_id] = nb_rbs_allowed_slice[CC_id][slice_id];
break; break;
} }
...@@ -495,7 +495,7 @@ void _dlsch_scheduler_pre_processor (module_id_t Mod_id, ...@@ -495,7 +495,7 @@ void _dlsch_scheduler_pre_processor (module_id_t Mod_id,
} }
} }
// Store the DLSCH buffer for each logical channel /* Store the DLSCH buffer for each logical channel for each UE */
_store_dlsch_buffer (Mod_id,slice_id,frameP,subframeP); _store_dlsch_buffer (Mod_id,slice_id,frameP,subframeP);
// Calculate the number of RBs required by each UE on the basis of logical channel's buffer // Calculate the number of RBs required by each UE on the basis of logical channel's buffer
...@@ -1044,6 +1044,7 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1044,6 +1044,7 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
if (eNB_UE_stats==NULL) { if (eNB_UE_stats==NULL) {
LOG_D(MAC,"[eNB] Cannot find eNB_UE_stats\n"); LOG_D(MAC,"[eNB] Cannot find eNB_UE_stats\n");
// mac_xface->macphy_exit("[MAC][eNB] Cannot find eNB_UE_stats\n"); // mac_xface->macphy_exit("[MAC][eNB] Cannot find eNB_UE_stats\n");
continue; continue;
...@@ -1078,6 +1079,7 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1078,6 +1079,7 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
if ((ue_sched_ctl->pre_nb_available_rbs[CC_id] == 0) || // no RBs allocated if ((ue_sched_ctl->pre_nb_available_rbs[CC_id] == 0) || // no RBs allocated
CCE_allocation_infeasible(mod_id, CC_id, 0, subframe, aggregation, rnti)) { CCE_allocation_infeasible(mod_id, CC_id, 0, subframe, aggregation, rnti)) {
LOG_D(MAC,"[eNB %d] Frame %d : no RB allocated for UE %d on CC_id %d: continue \n", LOG_D(MAC,"[eNB %d] Frame %d : no RB allocated for UE %d on CC_id %d: continue \n",
mod_id, frame, UE_id, CC_id); mod_id, frame, UE_id, CC_id);
//if(mac_xface->get_transmission_mode(module_idP,rnti)==5) //if(mac_xface->get_transmission_mode(module_idP,rnti)==5)
...@@ -1107,23 +1109,25 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1107,23 +1109,25 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
dl_data[num_ues_added]->has_serv_cell_index = 1; dl_data[num_ues_added]->has_serv_cell_index = 1;
dl_data[num_ues_added]->serv_cell_index = CC_id; dl_data[num_ues_added]->serv_cell_index = CC_id;
nb_available_rb = ue_sched_ctl->pre_nb_available_rbs[CC_id];
flexran_get_harq(mod_id, CC_id, UE_id, frame, subframe, &harq_pid, &round, openair_harq_DL); flexran_get_harq(mod_id, CC_id, UE_id, frame, subframe, &harq_pid, &round, openair_harq_DL);
sdu_length_total=0; sdu_length_total=0;
mcs = cqi_to_mcs[flexran_get_ue_wcqi(mod_id, UE_id)]; mcs = cqi_to_mcs[flexran_get_ue_wcqi(mod_id, UE_id)];
// LOG_I(FLEXRAN_AGENT, "The MCS is %d\n", mcs); // LOG_I(FLEXRAN_AGENT, "The MCS is %d\n", mcs);
mcs = cmin(mcs,flexran_slice_maxmcs(slice_id)); mcs = cmin(mcs,flexran_slice_maxmcs(slice_id));
#ifdef EXMIMO // #ifdef EXMIMO
if (mac_xface->get_transmission_mode(mod_id, CC_id, rnti) == 5) { // if (mac_xface->get_transmission_mode(mod_id, CC_id, rnti) == 5) {
mcs = cqi_to_mcs[flexran_get_ue_wcqi(mod_id, UE_id)]; // mcs = cqi_to_mcs[flexran_get_ue_wcqi(mod_id, UE_id)];
mcs = cmin(mcs,16); // mcs = cmin(mcs,16);
} // }
#endif // #endif
/*Get pre available resource blocks based on buffers*/
nb_available_rb = ue_sched_ctl->pre_nb_available_rbs[CC_id];
// initializing the rb allocation indicator for each UE // initializing the rb allocation indicator for each UE
for(j = 0; j < flexran_get_N_RBG(mod_id, CC_id); j++) { for(j = 0; j < flexran_get_N_RBG(mod_id, CC_id); j++) {
UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = 0; UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = 0;
rballoc_sub[j] = 0; rballoc_sub[j] = 0;
} }
...@@ -1211,7 +1215,9 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1211,7 +1215,9 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
ue_has_transmission = 0; ue_has_transmission = 0;
} }
//End of retransmission //End of retransmission
} else { /* This is a potentially new SDU opportunity */ }
else { /* This is a potentially new SDU opportunity */
rlc_status.bytes_in_buffer = 0; rlc_status.bytes_in_buffer = 0;
// Now check RLC information to compute number of required RBs // Now check RLC information to compute number of required RBs
// get maximum TBS size for RLC request // get maximum TBS size for RLC request
...@@ -1265,10 +1271,13 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1265,10 +1271,13 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
//Fill in as much as possible //Fill in as much as possible
data_to_request = cmin(dci_tbs - ta_len - header_len - sdu_length_total, rlc_status.bytes_in_buffer); data_to_request = cmin(dci_tbs - ta_len - header_len - sdu_length_total, rlc_status.bytes_in_buffer);
LOG_D(FLEXRAN_AGENT, "Will request %d bytes from channel %d\n", data_to_request, j); LOG_D(FLEXRAN_AGENT, "Will request %d bytes from channel %d\n", data_to_request, j);
if (data_to_request < 128) { //The header will be one byte less if (data_to_request < 128) { //The header will be one byte less
header_len--; header_len--;
header_len_last = 2; header_len_last = 2;
} else { }
else {
header_len_last = 3; header_len_last = 3;
} }
/* if (j == 1 || j == 2) { /* if (j == 1 || j == 2) {
...@@ -1364,7 +1373,8 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1364,7 +1373,8 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
for(j = 0; j < flexran_get_N_RBG(mod_id, CC_id); j++) { // for indicating the rballoc for each sub-band for(j = 0; j < flexran_get_N_RBG(mod_id, CC_id); j++) { // for indicating the rballoc for each sub-band
UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j]; UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = ue_sched_ctl->rballoc_sub_UE[CC_id][j];
} }
} else { }
else {
nb_rb_temp = nb_rb; nb_rb_temp = nb_rb;
j = 0; j = 0;
LOG_D(MAC, "[TEST]Will only partially fill the bitmap\n"); LOG_D(MAC, "[TEST]Will only partially fill the bitmap\n");
...@@ -1412,12 +1422,12 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1412,12 +1422,12 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid] = nb_rb; UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid] = nb_rb;
if (flexran_get_duplex_mode(mod_id, CC_id) == PROTOCOL__FLEX_DUPLEX_MODE__FLDM_TDD) { // if (flexran_get_duplex_mode(mod_id, CC_id) == PROTOCOL__FLEX_DUPLEX_MODE__FLDM_TDD) {
UE_list->UE_template[CC_id][UE_id].DAI++; // UE_list->UE_template[CC_id][UE_id].DAI++;
// printf("DAI update: subframeP %d: UE %d, DAI %d\n",subframeP,UE_id,UE_list->UE_template[CC_id][UE_id].DAI); // // printf("DAI update: subframeP %d: UE %d, DAI %d\n",subframeP,UE_id,UE_list->UE_template[CC_id][UE_id].DAI);
//#warning only for 5MHz channel //#warning only for 5MHz channel
update_ul_dci(mod_id, CC_id, rnti, UE_list->UE_template[CC_id][UE_id].DAI); // update_ul_dci(mod_id, CC_id, rnti, UE_list->UE_template[CC_id][UE_id].DAI);
} // }
// do PUCCH power control // do PUCCH power control
// this is the normalized RX power // this is the normalized RX power
...@@ -1653,11 +1663,11 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id, ...@@ -1653,11 +1663,11 @@ flexran_schedule_ue_dl_spec_common(mid_t mod_id,
} }
} }
if (flexran_get_duplex_mode(mod_id, CC_id) == PROTOCOL__FLEX_DUPLEX_MODE__FLDM_TDD) { // if (flexran_get_duplex_mode(mod_id, CC_id) == PROTOCOL__FLEX_DUPLEX_MODE__FLDM_TDD) {
/* TODO */ /* TODO */
//set_ul_DAI(mod_id, UE_id, CC_id, frame, subframe, frame_parms); //set_ul_DAI(mod_id, UE_id, CC_id, frame, subframe, frame_parms);
} // }
} // UE_id loop } // UE_id loop
} // CC_id loop } // CC_id loop
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment