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Michael Black
OpenXG UE
Commits
c407120c
Commit
c407120c
authored
Sep 28, 2020
by
Robert Schmidt
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Consider retransmissions in the preprocessor
parent
d2394d8a
Changes
1
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1 changed file
with
66 additions
and
32 deletions
+66
-32
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+66
-32
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
c407120c
...
@@ -513,13 +513,46 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
...
@@ -513,13 +513,46 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
module_id
,
UE_id
,
frame
,
slot
,
num_slots_per_tdd
,
&
sched_ctrl
->
pucch_sched_idx
);
module_id
,
UE_id
,
frame
,
slot
,
num_slots_per_tdd
,
&
sched_ctrl
->
pucch_sched_idx
);
AssertFatal
(
sched_ctrl
->
pucch_sched_idx
>=
0
,
"no uplink slot for PUCCH found!
\n
"
);
AssertFatal
(
sched_ctrl
->
pucch_sched_idx
>=
0
,
"no uplink slot for PUCCH found!
\n
"
);
uint8_t
*
vrb_map
=
RC
.
nrmac
[
module_id
]
->
common_channels
[
CC_id
].
vrb_map
;
const
int
current_harq_pid
=
sched_ctrl
->
current_harq_pid
;
NR_UE_harq_t
*
harq
=
&
sched_ctrl
->
harq_processes
[
current_harq_pid
];
NR_UE_ret_info_t
*
retInfo
=
&
sched_ctrl
->
retInfo
[
current_harq_pid
];
const
uint16_t
bwpSize
=
NRRIV2BW
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
int
rbStart
=
NRRIV2PRBOFFSET
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
if
(
harq
->
round
!=
0
)
{
/* retransmission */
sched_ctrl
->
time_domain_allocation
=
retInfo
->
time_domain_allocation
;
/* ensure that there is a free place for RB allocation */
int
rbSize
=
0
;
while
(
rbSize
<
retInfo
->
rbSize
)
{
rbStart
+=
rbSize
;
/* last iteration rbSize was not enough, skip it */
rbSize
=
0
;
while
(
rbStart
<
bwpSize
&&
vrb_map
[
rbStart
])
rbStart
++
;
if
(
rbStart
>=
bwpSize
)
{
LOG_E
(
MAC
,
"cannot allocate retransmission for UE %d/RNTI %04x: no resources
\n
"
,
UE_id
,
rnti
);
return
;
}
while
(
rbStart
+
rbSize
<
bwpSize
&&
!
vrb_map
[
rbStart
+
rbSize
]
&&
rbSize
<
retInfo
->
rbSize
)
rbSize
++
;
}
sched_ctrl
->
rbSize
=
retInfo
->
rbSize
;
sched_ctrl
->
rbStart
=
rbStart
;
/* MCS etc: just reuse from previous scheduling opportunity */
sched_ctrl
->
mcsTableIdx
=
retInfo
->
mcsTableIdx
;
sched_ctrl
->
mcs
=
retInfo
->
mcs
;
sched_ctrl
->
numDmrsCdmGrpsNoData
=
retInfo
->
numDmrsCdmGrpsNoData
;
}
else
{
// Time-domain allocation
// Time-domain allocation
sched_ctrl
->
time_domain_allocation
=
2
;
sched_ctrl
->
time_domain_allocation
=
2
;
// Freq-demain allocation
// Freq-demain allocation
uint8_t
*
vrb_map
=
RC
.
nrmac
[
module_id
]
->
common_channels
[
CC_id
].
vrb_map
;
const
uint16_t
bwpSize
=
NRRIV2BW
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
int
rbStart
=
NRRIV2PRBOFFSET
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
while
(
rbStart
<
bwpSize
&&
vrb_map
[
rbStart
])
rbStart
++
;
while
(
rbStart
<
bwpSize
&&
vrb_map
[
rbStart
])
rbStart
++
;
int
rbSize
=
1
;
int
rbSize
=
1
;
while
(
rbStart
+
rbSize
<
bwpSize
&&
!
vrb_map
[
rbStart
+
rbSize
])
rbSize
++
;
while
(
rbStart
+
rbSize
<
bwpSize
&&
!
vrb_map
[
rbStart
+
rbSize
])
rbSize
++
;
...
@@ -527,10 +560,6 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
...
@@ -527,10 +560,6 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
sched_ctrl
->
rbSize
=
rbSize
;
sched_ctrl
->
rbSize
=
rbSize
;
sched_ctrl
->
rbStart
=
rbStart
;
sched_ctrl
->
rbStart
=
rbStart
;
/* mark the corresponding RBs as used */
for
(
int
rb
=
0
;
rb
<
sched_ctrl
->
rbSize
;
rb
++
)
vrb_map
[
rb
+
sched_ctrl
->
rbStart
]
=
1
;
// modulation scheme
// modulation scheme
sched_ctrl
->
mcsTableIdx
=
0
;
sched_ctrl
->
mcsTableIdx
=
0
;
sched_ctrl
->
mcs
=
9
;
sched_ctrl
->
mcs
=
9
;
...
@@ -552,6 +581,11 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
...
@@ -552,6 +581,11 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
1
/* nrOfLayers */
)
1
/* nrOfLayers */
)
>>
3
;
>>
3
;
AssertFatal
(
TBS
!=
0
,
"TBS is zero but requested %d RBs!
\n
"
,
sched_ctrl
->
rbSize
);
AssertFatal
(
TBS
!=
0
,
"TBS is zero but requested %d RBs!
\n
"
,
sched_ctrl
->
rbSize
);
}
/* mark the corresponding RBs as used */
for
(
int
rb
=
0
;
rb
<
sched_ctrl
->
rbSize
;
rb
++
)
vrb_map
[
rb
+
sched_ctrl
->
rbStart
]
=
1
;
}
}
void
nr_schedule_ue_spec
(
module_id_t
module_id
,
void
nr_schedule_ue_spec
(
module_id_t
module_id
,
...
...
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