Commit efbd43fc authored by Raymond Knopp's avatar Raymond Knopp

Merge branch 'NR_RRCConfiguration' of...

Merge branch 'NR_RRCConfiguration' of https://gitlab.eurecom.fr/oai/openairinterface5g into NR_RRCConfiguration
parents 858c3328 4418f534
......@@ -751,6 +751,18 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
flags = 3; // end of burst
}
if (fp->freq_range==nr_FR2) {
// the beam index is written in bits 8-10 of the flags
// bit 11 enables the gpio programming
int beam=0;
if (slot==0 || slot==40) beam=0&8;
if (slot==10 || slot==50) beam=1&8;
if (slot==20 || slot==60) beam=2&8;
if (slot==30 || slot==70) beam=3&8;
flags |= beam<<8;
}
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_WRITE_FLAGS, flags );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot );
......
......@@ -276,14 +276,17 @@ static int trx_usrp_start(openair0_device *device) {
// setup GPIO for TDD, GPIO(4) = ATR_RX
//set data direction register (DDR) to output
s->usrp->set_gpio_attr("FP0", "DDR", 0x7f, 0x7f);
//set control register to ATR
s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0x7f);
s->usrp->set_gpio_attr("FP0", "DDR", 0xfff, 0xfff);
//set lower 7 bits to be controlled automatically by ATR (the rest 5 bits are controlled manually)
s->usrp->set_gpio_attr("FP0", "CTRL", 0x7f,0xfff);
//set pins 4 (RX_TX_Switch) and 6 (Shutdown PA) to 1 when the radio is only receiving (ATR_RX)
s->usrp->set_gpio_attr("FP0", "ATR_RX", (1<<4)|(1<<6), 0x7f);
// set pin 5 (Shutdown LNA) to 1 when the radio is transmitting and receiveing (ATR_XX)
// (we use full duplex here, because our RX is on all the time - this might need to change later)
s->usrp->set_gpio_attr("FP0", "ATR_XX", (1<<5), 0x7f);
// set the output pins to 0
s->usrp->set_gpio_attr("FP0", "OUT", 7<<7, 0xf80);
// init recv and send streaming
uhd::stream_cmd_t cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
LOG_I(HW,"Time in secs now: %llu \n", s->usrp->get_time_now().to_ticks(s->sample_rate));
......@@ -404,10 +407,19 @@ static int trx_usrp_write_recplay(openair0_device *device, openair0_timestamp ti
@param antenna_id index of the antenna if the device has multiple antennas
@param flags flags must be set to TRUE if timestamp parameter needs to be applied
*/
static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp, void **buff, int nsamps, int cc, int flags) {
static int trx_usrp_write(openair0_device *device,
openair0_timestamp timestamp,
void **buff,
int nsamps,
int cc,
int flags) {
int ret=0;
usrp_state_t *s = (usrp_state_t *)device->priv;
int nsamps2; // aligned to upper 32 or 16 byte boundary
int flags_lsb = flags&0xff;
int flags_msb = (flags>>8)&0xff;
#if defined(__x86_64) || defined(__i386__)
#ifdef __AVX2__
nsamps2 = (nsamps+7)>>3;
......@@ -441,27 +453,28 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
boolean_t first_packet_state=false,last_packet_state=false;
if (flags == 2) { // start of burst
if (flags_lsb == 2) { // start of burst
// s->tx_md.start_of_burst = true;
// s->tx_md.end_of_burst = false;
first_packet_state = true;
last_packet_state = false;
} else if (flags == 3) { // end of burst
} else if (flags_lsb == 3) { // end of burst
//s->tx_md.start_of_burst = false;
//s->tx_md.end_of_burst = true;
first_packet_state = false;
last_packet_state = true;
} else if (flags == 4) { // start and end
} else if (flags_lsb == 4) { // start and end
// s->tx_md.start_of_burst = true;
// s->tx_md.end_of_burst = true;
first_packet_state = true;
last_packet_state = true;
} else if (flags==1) { // middle of burst
} else if (flags_lsb==1) { // middle of burst
// s->tx_md.start_of_burst = false;
// s->tx_md.end_of_burst = false;
first_packet_state = false;
last_packet_state = false;
} else if (flags==10) { // fail safe mode
}
else if (flags_lsb==10) { // fail safe mode
// s->tx_md.has_time_spec = false;
// s->tx_md.start_of_burst = false;
// s->tx_md.end_of_burst = true;
......@@ -469,12 +482,22 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
last_packet_state = true;
}
s->tx_md.has_time_spec = true;
s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state;
s->tx_md.end_of_burst = last_packet_state;
s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate);
s->tx_count++;
// bit 3 enables gpio (for backward compatibility)
if (flags_msb&8) {
// push GPIO bits 7-9 from flags_msb
int gpio789=(flags_msb&7)<<7;
s->usrp->set_command_time(s->tx_md.time_spec);
s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380);
s->usrp->clear_command_time();
}
if (cc>1) {
std::vector<void *> buff_ptrs;
......@@ -482,7 +505,11 @@ static int trx_usrp_write(openair0_device *device, openair0_timestamp timestamp,
buff_ptrs.push_back(&(((int16_t *)buff_tx[i])[0]));
ret = (int)s->tx_stream->send(buff_ptrs, nsamps, s->tx_md);
} else ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md);
}
else {
ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md);
}
if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
return ret;
......
......@@ -148,7 +148,7 @@ gNBs =
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 3;
ssb_PositionsInBurst_Bitmap = 1;
ssb_PositionsInBurst_Bitmap = 0x100000001L;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
......@@ -170,8 +170,8 @@ gNBs =
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 30;
dl_UL_TransmissionPeriodicity = 5;
nrofDownlinkSlots = 10;
nrofDownlinkSymbols = 0;
nrofUplinkSlots = 10;
nrofUplinkSymbols = 0;
......@@ -237,8 +237,8 @@ RUs = (
max_pdschReferenceSignalPower = -27;
max_rxgain = 114;
eNB_instances = [0];
sdr_addrs = "type=x300";
if_freq = 3000000000;
sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2";
if_freq = 5300000000;
}
);
......
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