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Michael Black
OpenXG-RAN
Commits
17a1a554
Commit
17a1a554
authored
Jun 02, 2020
by
Francesco Mani
Browse files
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Plain Diff
separation of dl and ul clear fapi information
parent
cf5bc231
Changes
4
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4 changed files
with
30 additions
and
15 deletions
+30
-15
openair1/SIMULATION/NR_PHY/dlsim.c
openair1/SIMULATION/NR_PHY/dlsim.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+19
-9
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+9
-4
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
+1
-1
No files found.
openair1/SIMULATION/NR_PHY/dlsim.c
View file @
17a1a554
...
@@ -745,7 +745,7 @@ int main(int argc, char **argv)
...
@@ -745,7 +745,7 @@ int main(int argc, char **argv)
while
((
round
<
num_rounds
)
&&
(
UE_harq_process
->
harq_ack
.
ack
==
0
))
{
while
((
round
<
num_rounds
)
&&
(
UE_harq_process
->
harq_ack
.
ack
==
0
))
{
memset
(
RC
.
nrmac
[
0
]
->
cce_list
[
1
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
memset
(
RC
.
nrmac
[
0
]
->
cce_list
[
1
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
memset
(
RC
.
nrmac
[
0
]
->
cce_list
[
1
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
memset
(
RC
.
nrmac
[
0
]
->
cce_list
[
1
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
clear_nr_nfapi_information
(
RC
.
nrmac
[
0
],
0
,
frame
,
slot
);
clear_nr_nfapi_information
_dl
(
RC
.
nrmac
[
0
],
0
,
frame
,
slot
);
UE_list
->
UE_sched_ctrl
[
0
].
harq_processes
[
0
].
ndi
=
!
(
trial
&
1
);
UE_list
->
UE_sched_ctrl
[
0
].
harq_processes
[
0
].
ndi
=
!
(
trial
&
1
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
17a1a554
...
@@ -62,13 +62,12 @@
...
@@ -62,13 +62,12 @@
const
uint8_t
nr_slots_per_frame
[
5
]
=
{
10
,
20
,
40
,
80
,
160
};
const
uint8_t
nr_slots_per_frame
[
5
]
=
{
10
,
20
,
40
,
80
,
160
};
uint16_t
nr_pdcch_order_table
[
6
]
=
{
31
,
31
,
511
,
2047
,
2047
,
8191
};
uint16_t
nr_pdcch_order_table
[
6
]
=
{
31
,
31
,
511
,
2047
,
2047
,
8191
};
void
clear_nr_nfapi_information
(
gNB_MAC_INST
*
gNB
,
void
clear_nr_nfapi_information
_dl
(
gNB_MAC_INST
*
gNB
,
int
CC_idP
,
int
CC_idP
,
frame_t
frameP
,
frame_t
frameP
,
sub_frame_t
slotP
){
sub_frame_t
slotP
){
nfapi_nr_dl_tti_request_t
*
DL_req
=
&
gNB
->
DL_req
[
0
];
nfapi_nr_dl_tti_request_t
*
DL_req
=
&
gNB
->
DL_req
[
0
];
nfapi_nr_ul_tti_request_t
*
UL_tti_req
=
&
gNB
->
UL_tti_req
[
0
];
nfapi_nr_ul_dci_request_t
*
UL_dci_req
=
&
gNB
->
UL_dci_req
[
0
];
nfapi_nr_ul_dci_request_t
*
UL_dci_req
=
&
gNB
->
UL_dci_req
[
0
];
nfapi_nr_tx_data_request_t
*
TX_req
=
&
gNB
->
TX_req
[
0
];
nfapi_nr_tx_data_request_t
*
TX_req
=
&
gNB
->
TX_req
[
0
];
...
@@ -86,17 +85,28 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
...
@@ -86,17 +85,28 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
UL_dci_req
[
CC_idP
].
Slot
=
slotP
;
UL_dci_req
[
CC_idP
].
Slot
=
slotP
;
UL_dci_req
[
CC_idP
].
numPdus
=
0
;
UL_dci_req
[
CC_idP
].
numPdus
=
0
;
TX_req
[
CC_idP
].
Number_of_PDUs
=
0
;
}
}
void
clear_nr_nfapi_information_ul
(
gNB_MAC_INST
*
gNB
,
int
CC_idP
,
frame_t
frameP
,
sub_frame_t
slotP
){
nfapi_nr_ul_tti_request_t
*
UL_tti_req
=
&
gNB
->
UL_tti_req
[
0
];
if
(
nfapi_mode
==
0
||
nfapi_mode
==
1
)
{
// monolithic or PNF
UL_tti_req
[
CC_idP
].
SFN
=
frameP
;
UL_tti_req
[
CC_idP
].
SFN
=
frameP
;
UL_tti_req
[
CC_idP
].
Slot
=
slotP
;
UL_tti_req
[
CC_idP
].
Slot
=
slotP
;
UL_tti_req
[
CC_idP
].
n_pdus
=
0
;
UL_tti_req
[
CC_idP
].
n_pdus
=
0
;
UL_tti_req
[
CC_idP
].
n_ulsch
=
0
;
UL_tti_req
[
CC_idP
].
n_ulsch
=
0
;
UL_tti_req
[
CC_idP
].
n_ulcch
=
0
;
UL_tti_req
[
CC_idP
].
n_ulcch
=
0
;
UL_tti_req
[
CC_idP
].
n_group
=
0
;
UL_tti_req
[
CC_idP
].
n_group
=
0
;
TX_req
[
CC_idP
].
Number_of_PDUs
=
0
;
}
}
}
}
/*
/*
void check_nr_ul_failure(module_id_t module_idP,
void check_nr_ul_failure(module_id_t module_idP,
int CC_id,
int CC_id,
...
@@ -419,7 +429,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
...
@@ -419,7 +429,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
memset
(
cc
[
CC_id
].
vrb_map
,
0
,
100
);
memset
(
cc
[
CC_id
].
vrb_map
,
0
,
100
);
memset
(
cc
[
CC_id
].
vrb_map_UL
,
0
,
100
);
memset
(
cc
[
CC_id
].
vrb_map_UL
,
0
,
100
);
clear_nr_nfapi_information
(
RC
.
nrmac
[
module_idP
],
CC_id
,
frame_txP
,
slot_txP
);
clear_nr_nfapi_information
_dl
(
RC
.
nrmac
[
module_idP
],
CC_id
,
frame_txP
,
slot_txP
);
}
}
// refresh UE list based on UEs dropped by PHY in previous subframe
// refresh UE list based on UEs dropped by PHY in previous subframe
...
...
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
17a1a554
...
@@ -56,10 +56,15 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
...
@@ -56,10 +56,15 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
NR_CellGroupConfig_t
*
secondaryCellGroup
NR_CellGroupConfig_t
*
secondaryCellGroup
);
);
void
clear_nr_nfapi_information
(
gNB_MAC_INST
*
gNB
,
void
clear_nr_nfapi_information_dl
(
gNB_MAC_INST
*
gNB
,
int
CC_idP
,
int
CC_idP
,
frame_t
frameP
,
frame_t
frameP
,
sub_frame_t
subframeP
);
sub_frame_t
subframeP
);
void
clear_nr_nfapi_information_ul
(
gNB_MAC_INST
*
gNB
,
int
CC_idP
,
frame_t
frameP
,
sub_frame_t
subframeP
);
void
gNB_dlsch_ulsch_scheduler
(
module_id_t
module_idP
,
void
gNB_dlsch_ulsch_scheduler
(
module_id_t
module_idP
,
frame_t
frame_txP
,
sub_frame_t
slot_txP
,
frame_t
frame_txP
,
sub_frame_t
slot_txP
,
...
...
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
View file @
17a1a554
...
@@ -225,7 +225,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
...
@@ -225,7 +225,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
}
}
// clear DL/UL info for new scheduling round
// clear DL/UL info for new scheduling round
clear_nr_nfapi_information
(
mac
,
CC_id
,
UL_info
->
frame
,
UL_info
->
slot
);
clear_nr_nfapi_information
_ul
(
mac
,
CC_id
,
UL_info
->
frame
,
UL_info
->
slot
);
handle_nr_rach
(
UL_info
);
handle_nr_rach
(
UL_info
);
handle_nr_uci
(
UL_info
,
&
mac
->
UE_list
.
UE_sched_ctrl
[
0
]);
handle_nr_uci
(
UL_info
,
&
mac
->
UE_list
.
UE_sched_ctrl
[
0
]);
// clear HI prior to handling ULSCH
// clear HI prior to handling ULSCH
...
...
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