Type 0 pdcch coreset and ss params update

nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h

@@ -121,6 +121,7 @@ typedef struct {
   nfapi_uint16_tlv_t  ssb_periodicity;
   nfapi_uint16_tlv_t  ss_pbch_block_power;
   nfapi_uint16_tlv_t  n_ssb_crb;
+  nfapi_uint16_tlv_t  rmsi_pdcch_config;
 } nfapi_nr_sch_config_t;
 
 #define NFAPI_NR_SCH_CONFIG_PHYSICAL_CELL_ID_TAG 0x501E

openair1/PHY/NR_TRANSPORT/nr_dci.h

@@ -56,10 +56,10 @@ typedef enum {
 } nr_pdcch_ss_type_e;
 
 typedef enum {
-  nr_pdcch_mux_pattern_type_1=0,
-  nr_pdcch_mux_pattern_type_2,
-  nr_pdcch_mux_pattern_type_3
-} nr_pdcch_mux_pattern_type_e;
+  nr_ssb_and_cset_mux_pattern_type_1=0,
+  nr_ssb_and_cset_mux_pattern_type_2,
+  nr_ssb_and_cset_mux_pattern_type_3
+} nr_ssb_and_cset_mux_pattern_type_e;
 
 typedef struct {
   uint8_t param_O;
@@ -73,7 +73,7 @@ typedef struct {
   uint8_t n_rb;
   uint8_t n_symb;
   uint8_t rb_offset;
-  nr_pdcch_mux_pattern_type_e mux_pattern;
+  nr_ssb_and_cset_mux_pattern_type_e mux_pattern;
 } nr_pdcch_coreset_params_t;
 
 typedef struct {

openair1/PHY/defs_nr_common.h

@@ -70,6 +70,13 @@ typedef enum {
   NR_MU_4,
 } nr_numerology_index_e;
 
+typedef enum {
+  kHz15=0,
+  kHz30,
+  kHz60,
+  kHz120,
+  kHz240
+} nr_scs_e;
 
 typedef enum{
   nr_ssb_type_A = 0,

openair1/SCHED_NR/phy_procedures_nr_common.c

@@ -33,17 +33,22 @@
 #include "sched_nr.h"
 
 
-/// LUT for the number of symbols in the coreset indexed by SSB index
-uint8_t nr_coreset_nsymb_pdcch_type_0[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2};
-/// LUT for the number of RBs in the coreset indexed by SSB index
-uint8_t nr_coreset_rb_offset_pdcch_type_0[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
-/// LUT for monitoring occasions param O indexed by SSB index
+/// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config)
+uint8_t nr_coreset_nsymb_pdcch_type_0_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
+uint8_t nr_coreset_nsymb_pdcch_type_0_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
+/// LUT for the number of RBs in the coreset indexed by coreset index
+uint8_t nr_coreset_rb_offset_pdcch_type_0_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
+uint8_t nr_coreset_rb_offset_pdcch_type_0_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
+/// LUT for monitoring occasions param O indexed by ss index (4 MSB rmsi_pdcch_config)
 uint8_t nr_ss_param_O_type_0_mux1_FR1[16] = {0,0,2,2,5,5,7,7,0,5,0,0,2,2,5,5};
-/// LUT for number of SS sets per slot indexed by SSB index
+uint8_t nr_ss_param_O_type_0_mux1_FR2[14] = {0,0,2.5,2.5,5,5,0,2.5,5,7.5,7.5,7.5,0,5};
+/// LUT for number of SS sets per slot indexed by ss index
 uint8_t nr_ss_sets_per_slot_type_0_FR1[16] = {1,2,1,2,1,2,1,2,1,1,1,1,1,1,1,1};
-/// LUT for monitoring occasions param M indexed by SSB index
+uint8_t nr_ss_sets_per_slot_type_0_FR2[14] = {1,2,1,2,1,2,2,2,2,1,2,2,1,1};
+/// LUT for monitoring occasions param M indexed by ss index
 uint8_t nr_ss_param_M_type_0_mux1_FR1[16] = {1,0.5,1,0.5,1,0.5,1,0.5,2,2,1,1,1,1,1,1};
-/// LUT for SS first symbol index indexed by SSB index
+uint8_t nr_ss_param_M_type_0_mux1_FR2[14] = {1,0.5,1,0.5,1,0.5,0.5,0.5,0.5,1,0.5,0.5,2,2};
+/// LUT for SS first symbol index indexed by ss index
 uint8_t nr_ss_first_symb_idx_type_0_mux1_FR1[8] = {0,0,1,2,1,2,1,2};
 
 
@@ -55,40 +60,101 @@ nr_subframe_t nr_subframe_select(nfapi_nr_config_request_t *cfg,unsigned char su
 }
 
 
-void nr_get_coreset_and_ss_params(nr_pdcch_vars_t *pdcch_vars,
-                          uint8_t mu,
-                          uint8_t ssb_idx)
+void nr_get_type0_coreset_and_ss_params(nr_pdcch_vars_t *pdcch_vars,
+                          nr_scs_e scs_common,
+                          nr_scs_e pdcch_scs,
+                          nr_frequency_range_e freq_range,
+                          uint8_t rmsi_pdcch_config,
+                          uint16_t N_RB)
 {
   nr_pdcch_coreset_params_t *coreset_params = &pdcch_vars->coreset_params;
   nr_pdcch_ss_params_t *ss_params = &pdcch_vars->ss_params;
+  uint8_t ss_idx = rmsi_pdcch_config&0xf;
+  uint8_t cset_idx = (rmsi_pdcch_config>>4)&0xf;
+
+  /// Coreset params
+  switch(scs_common) {
+
+    case kHz15:
+      break;
 
-  // the switch case below assumes that only the cases where the SSB and the PDCCH have the same SCS are supported along with type 1 PDCCH/ mux pattern 1 and FR1
-  switch(mu) {
+    case kHz30:
 
-    case NR_MU_0:
+      if (N_RB < 106) { // Minimum 40Mhz bandwidth not satisfied
+        switch(pdcch_scs) {
+          case kHz15:
             break;
 
-    case NR_MU_1:
-      coreset_params->mux_pattern = nr_pdcch_mux_pattern_type_1;
-      coreset_params->n_rb = (ssb_idx < 10)? 24 : 48;
-      coreset_params->n_symb = nr_coreset_nsymb_pdcch_type_0[ssb_idx];
-      coreset_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0[ssb_idx];
-      ss_params->ss_type = nr_pdcch_css_type_1;
-      ss_params->param_O = nr_ss_param_O_type_0_mux1_FR1[ssb_idx];
-      ss_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ssb_idx];
-      ss_params->param_M = nr_ss_param_M_type_0_mux1_FR1[ssb_idx];
-      ss_params->first_symbol_idx = (ssb_idx < 8)? ( (ssb_idx&1)? coreset_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ssb_idx - 8];
+          case kHz30:
+            coreset_params->mux_pattern = nr_ssb_and_cset_mux_pattern_type_1;
+            coreset_params->n_rb = (cset_idx < 10)? 24 : 48;
+            coreset_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
+            coreset_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
             break;
 
-    case NR_MU_2:
+          default:
+            AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+        }
+      }
+
+      else {
+        AssertFatal(ss_idx<10 ,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+        switch(pdcch_scs) {
+          case kHz15:
             break;
 
-    case NR_MU_3:
+          case kHz30:
+            coreset_params->mux_pattern = nr_ssb_and_cset_mux_pattern_type_1;
+            coreset_params->n_rb = (cset_idx < 4)? 24 : 48;
+            coreset_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
+            coreset_params->rb_offset =  nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
             break;
 
           default:
-    AssertFatal(1==0,"Invalid PDCCH numerology index %d\n", mu);
+            AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
+        }
+      }
+
+    case kHz60:
+      break;
+
+    case kHz120:
+      break;
 
+  default:
+    AssertFatal(1==0,"Invalid common subcarrier spacing %d\n", scs_common);
+
+  }
+
+  /// Search space params
+  switch(coreset_params->mux_pattern) {
+
+    case nr_ssb_and_cset_mux_pattern_type_1:
+      if (freq_range == nr_FR1) {
+        ss_params->param_O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
+        ss_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
+        ss_params->param_M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
+        ss_params->first_symbol_idx = (ss_idx < 8)? ( (ss_idx&1)? coreset_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
+      }
+
+      else {
+        AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx);
+        ss_params->param_O = nr_ss_param_O_type_0_mux1_FR2[ss_idx];
+        ss_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx];
+        ss_params->param_M = nr_ss_param_M_type_0_mux1_FR2[ss_idx];
+        ss_params->first_symbol_idx = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0;
+      }
+
+      break;
+
+    case nr_ssb_and_cset_mux_pattern_type_2:
+      break;
+
+    case nr_ssb_and_cset_mux_pattern_type_3:
+      break;
+
+    default:
+      AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", coreset_params->mux_pattern);
   }
 }
 
@@ -99,7 +165,7 @@ void nr_get_pdcch_type_0_monitoring_period(nr_pdcch_vars_t *pdcch_vars,
 {
   uint8_t O = pdcch_vars->ss_params.param_O, M = pdcch_vars->ss_params.param_M;
 
-  if (pdcch_vars->coreset_params.mux_pattern == nr_pdcch_mux_pattern_type_1) {
+  if (pdcch_vars->coreset_params.mux_pattern == nr_ssb_and_cset_mux_pattern_type_1) {
     pdcch_vars->nb_slots = 2;
     pdcch_vars->sfn_mod2 = ((uint8_t)(floor( (O*pow(2, mu) + floor(ssb_idx*M)) / nb_slots_per_frame )) & 1)? 1 : 0;
     pdcch_vars->first_slot = (uint8_t)(O*pow(2, mu) + floor(ssb_idx*M)) % nb_slots_per_frame;

openair1/SCHED_NR/sched_nr.h

@@ -42,9 +42,12 @@ void nr_feptx_ofdm(RU_t *ru);
 void nr_feptx_ofdm_2thread(RU_t *ru);
 void nr_feptx0(RU_t *ru,int slot);
 
-void nr_get_coreset_and_ss_params(nr_pdcch_vars_t *pdcch_params,
-                                  uint8_t mu,
-                                  uint8_t ssb_idx);
+void nr_get_type0_coreset_and_ss_params(nr_pdcch_vars_t *pdcch_vars,
+                          nr_scs_e scs_common,
+                          nr_scs_e pdcch_scs,
+                          nr_frequency_range_e freq_range,
+                          uint8_t rmsi_pdcch_config,
+                          uint16_t N_RB);
 void nr_get_pdcch_type_0_monitoring_period(nr_pdcch_vars_t *pdcch_vars,
                                            uint8_t mu,
                                            uint8_t nb_slots_per_frame,