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Michael Black
OpenXG-RAN
Commits
4e1b874a
Commit
4e1b874a
authored
Oct 21, 2019
by
Francesco Mani
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fix on table definition in dlschsim
parent
668de031
Changes
1
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openair1/SIMULATION/NR_PHY/dlschsim.c
openair1/SIMULATION/NR_PHY/dlschsim.c
+2
-2
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openair1/SIMULATION/NR_PHY/dlschsim.c
View file @
4e1b874a
...
@@ -110,7 +110,7 @@ int main(int argc, char **argv)
...
@@ -110,7 +110,7 @@ int main(int argc, char **argv)
uint16_t
nb_symb_sch
=
12
;
uint16_t
nb_symb_sch
=
12
;
uint16_t
nb_rb
=
50
;
uint16_t
nb_rb
=
50
;
uint8_t
Imcs
=
9
;
uint8_t
Imcs
=
9
;
uint8_t
mcs_table
=
1
;
uint8_t
mcs_table
=
0
;
cpuf
=
get_cpu_freq_GHz
();
cpuf
=
get_cpu_freq_GHz
();
...
@@ -442,7 +442,7 @@ int main(int argc, char **argv)
...
@@ -442,7 +442,7 @@ int main(int argc, char **argv)
mod_order
=
nr_get_Qm_dl
(
Imcs
,
mcs_table
);
mod_order
=
nr_get_Qm_dl
(
Imcs
,
mcs_table
);
rate
=
nr_get_code_rate_dl
(
Imcs
,
mcs_table
);
rate
=
nr_get_code_rate_dl
(
Imcs
,
mcs_table
);
available_bits
=
nr_get_G
(
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
,
length_dmrs
,
mod_order
,
1
);
available_bits
=
nr_get_G
(
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
,
length_dmrs
,
mod_order
,
1
);
scale
=
((
mcs_table
==
2
)
&&
((
Imcs
==
20
)
||
(
Imcs
==
26
)))
?
11
:
10
;
scale
=
((
mcs_table
==
1
)
&&
((
Imcs
==
20
)
||
(
Imcs
==
26
)))
?
11
:
10
;
TBS
=
nr_compute_tbs
(
mod_order
,
rate
,
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
*
length_dmrs
,
0
,
Nl
);
TBS
=
nr_compute_tbs
(
mod_order
,
rate
,
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
*
length_dmrs
,
0
,
Nl
);
printf
(
"available bits %u TBS %u mod_order %d
\n
"
,
available_bits
,
TBS
,
mod_order
);
printf
(
"available bits %u TBS %u mod_order %d
\n
"
,
available_bits
,
TBS
,
mod_order
);
//dlsch->harq_ids[subframe]= 0;
//dlsch->harq_ids[subframe]= 0;
...
...
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