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Commit c96c98e1 authored by hardy's avatar hardy
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remove thread-pool for gnb + oai ue test update

parent 1e689715
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ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.usrpn310.conf
View file @ c96c98e1
Active_gNBs = ( "gNB-OAI"); Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying # Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none"; Asn1_verbosity = "none";
gNBs = gNBs =
( (
{ {
////////// Identification parameters: ////////// Identification parameters:
gNB_ID = 0xe00; gNB_CU_ID = 0xe00;
gNB_name = "gNB-OAI";
# cell_type = "CELL_MACRO_GNB";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1; gNB_name = "gNB-OAI";
plmn_list = ({ min_rxtxtime_pdsch = 6;
mcc = 208;
mnc = 99; // Tracking area code, 0x0000 and 0xfffe are reserved values
mnc_length = 2; tracking_area_code = 1;
snssaiList = (
{ plmn_list = ({
sst = 1; mcc = 208;
sd = 0x1; // 0 false, else true mnc = 97;
}, mnc_length = 2;
{ snssaiList = (
sst = 1; {
sd = 0x112233; // 0 false, else true sst = 1;
} sd = 0x010203; // 0 false, else true
); },
{
}); sst = 1;
sd = 0x112233; // 0 false, else true
nr_cellid = 12345678L; }
);
////////// Physical parameters: });
ssb_SubcarrierOffset = 0; nr_cellid = 12345678L
pdsch_AntennaPorts = 1;
pusch_AntennaPorts = 1; # tr_s_preference = "local_mac"
min_rxtxtime_pdsch = 6;
ul_prbblacklist = "51,52,53,54" ////////// Physical parameters:
pdcch_ConfigSIB1 = ( ssb_SubcarrierOffset = 0;
{ pdsch_AntennaPorts = 1;
controlResourceSetZero = 12; pusch_AntennaPorts = 1;
searchSpaceZero = 0; #pusch_TargetSNRx10 = 200;
} #pucch_TargetSNRx10 = 200;
); ul_prbblacklist = "51,52,53,54"
servingCellConfigCommon = ( pdcch_ConfigSIB1 = (
{ {
#spCellConfigCommon controlResourceSetZero = 11;
searchSpaceZero = 0;
physCellId = 0; }
);
# downlinkConfigCommon
#frequencyInfoDL servingCellConfigCommon = (
# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) {
absoluteFrequencySSB = 641280; #spCellConfigCommon
dl_frequencyBand = 78;
# this is 3600 MHz physCellId = 0;
dl_absoluteFrequencyPointA = 640008;
#scs-SpecificCarrierList # downlinkConfigCommon
dl_offstToCarrier = 0; #frequencyInfoDL
# subcarrierSpacing # this is 3301.68 MHz + 22*12*30e-3 MHz = 3309.6
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 #absoluteFrequencySSB = 620640;
dl_subcarrierSpacing = 1; # this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
dl_carrierBandwidth = 106; absoluteFrequencySSB = 621312;
#initialDownlinkBWP # this is 3503.28 MHz + 22*12*30e-3 MHz = 3511.2
#genericParameters #absoluteFrequencySSB = 634080;
# this is RBstart=27,L=48 (275*(L-1))+RBstart # this is 3600.48 MHz
initialDLBWPlocationAndBandwidth = 12952; # 6366 12925 12956 28875 12952 #absoluteFrequencySSB = 640032;
# subcarrierSpacing #dl_frequencyBand = 78;
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 # this is 3301.68 MHz
initialDLBWPsubcarrierSpacing = 1; #dl_absoluteFrequencyPointA = 620112;
#pdcch-ConfigCommon # this is 3300.60 MHz
initialDLBWPcontrolResourceSetZero = 12; dl_absoluteFrequencyPointA = 620040;
initialDLBWPsearchSpaceZero = 0; # this is 3502.56 MHz
#pdsch-ConfigCommon #dl_absoluteFrequencyPointA = 633552;
#pdschTimeDomainAllocationList (up to 16 entries) # this is 3600.48 MHz
initialDLBWPk0_0 = 0; #for DL slot #dl_absoluteFrequencyPointA = 640032;
initialDLBWPmappingType_0 = 0; #0=typeA,1=typeB #scs-SpecificCarrierList
initialDLBWPstartSymbolAndLength_0 = 40; #this is SS=1,L=13 dl_offstToCarrier = 0;
# subcarrierSpacing
initialDLBWPk0_1 = 0; #for mixed slot # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPmappingType_1 = 0; dl_subcarrierSpacing = 1;
initialDLBWPstartSymbolAndLength_1 = 57; #this is SS=1,L=5 dl_carrierBandwidth = 106;
#initialDownlinkBWP
#uplinkConfigCommon #genericParameters
#frequencyInfoUL # this is RBstart=0,L=106 (275*(L-1))+RBstart
ul_frequencyBand = 78; initialDLBWPlocationAndBandwidth = 28875;
#scs-SpecificCarrierList # subcarrierSpacing
ul_offstToCarrier = 0; # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
# subcarrierSpacing initialDLBWPsubcarrierSpacing = 1;
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 #pdcch-ConfigCommon
ul_subcarrierSpacing = 1; initialDLBWPcontrolResourceSetZero = 11;
ul_carrierBandwidth = 106; initialDLBWPsearchSpaceZero = 0;
pMax = 20; #pdsch-ConfigCommon
#initialUplinkBWP #pdschTimeDomainAllocationList (up to 16 entries)
#genericParameters initialDLBWPk0_0 = 0;
initialULBWPlocationAndBandwidth = 12952; #initialULBWPmappingType
# subcarrierSpacing #0=typeA,1=typeB
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 initialDLBWPmappingType_0 = 0;
initialULBWPsubcarrierSpacing = 1; #this is SS=1,L=13
#rach-ConfigCommon initialDLBWPstartSymbolAndLength_0 = 40;
#rach-ConfigGeneric
prach_ConfigurationIndex = 98; initialDLBWPk0_1 = 0;
#prach_msg1_FDM initialDLBWPmappingType_1 = 0;
#0 = one, 1=two, 2=four, 3=eight #this is SS=1,L=5
prach_msg1_FDM = 0; initialDLBWPstartSymbolAndLength_1 = 57;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13; #uplinkConfigCommon
preambleReceivedTargetPower = -96; #frequencyInfoUL
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) ul_frequencyBand = 78;
preambleTransMax = 6; #scs-SpecificCarrierList
#powerRampingStep ul_offstToCarrier = 0;
# 0=dB0,1=dB2,2=dB4,3=dB6 # subcarrierSpacing
powerRampingStep = 1; # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
#ra_ReponseWindow ul_subcarrierSpacing = 1;
#1,2,4,8,10,20,40,80 ul_carrierBandwidth = 106;
ra_ResponseWindow = 4; pMax = 20;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR #initialUplinkBWP
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen #genericParameters
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; initialULBWPlocationAndBandwidth = 28875;
#oneHalf (0..15) 4,8,12,16,...60,64 # subcarrierSpacing
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
#ra_ContentionResolutionTimer initialULBWPsubcarrierSpacing = 1;
#(0..7) 8,16,24,32,40,48,56,64 #rach-ConfigCommon
ra_ContentionResolutionTimer = 7; #rach-ConfigGeneric
rsrp_ThresholdSSB = 19; prach_ConfigurationIndex = 98;
#prach-RootSequenceIndex_PR #prach_msg1_FDM
#1 = 839, 2 = 139 #0 = one, 1=two, 2=four, 3=eight
prach_RootSequenceIndex_PR = 2; prach_msg1_FDM = 0;
prach_RootSequenceIndex = 1; prach_msg1_FrequencyStart = 0;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex zeroCorrelationZoneConfig = 12;
# preambleReceivedTargetPower = -104;
msg1_SubcarrierSpacing = 1, #preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
# restrictedSetConfig preambleTransMax = 6;
# 0=unrestricted, 1=restricted type A, 2=restricted type B #powerRampingStep
restrictedSetConfig = 0, # 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
# pusch-ConfigCommon (up to 16 elements) #ra_ReponseWindow
initialULBWPk2_0 = 6; # used for UL slot #1,2,4,8,10,20,40,80
initialULBWPmappingType_0 = 1 ra_ResponseWindow = 4;
initialULBWPstartSymbolAndLength_0 = 41; # this is SS=0 L=13 #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
initialULBWPk2_1 = 6; # used for mixed slot ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
initialULBWPmappingType_1 = 1; #oneHalf (0..15) 4,8,12,16,...60,64
initialULBWPstartSymbolAndLength_1 = 38; # this is SS=10 L=3 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
initialULBWPk2_2 = 7; # used for Msg.3 during RA #(0..7) 8,16,24,32,40,48,56,64
initialULBWPmappingType_2 = 1; ra_ContentionResolutionTimer = 7;
initialULBWPstartSymbolAndLength_2 = 52; # this is SS=10 L=4 rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
msg3_DeltaPreamble = 1; #1 = 839, 2 = 139
p0_NominalWithGrant =-90; prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# pucch-ConfigCommon setup : # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
# pucchGroupHopping #
# 0 = neither, 1= group hopping, 2=sequence hopping msg1_SubcarrierSpacing = 1,
pucchGroupHopping = 0; # restrictedSetConfig
hoppingId = 40; # 0=unrestricted, 1=restricted type A, 2=restricted type B
p0_nominal = -90; restrictedSetConfig = 0,
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long # pusch-ConfigCommon (up to 16 elements)
ssb_PositionsInBurst_PR = 2; initialULBWPk2_0 = 6;
ssb_PositionsInBurst_Bitmap = 1; initialULBWPmappingType_0 = 1
# this is SS=2 L=13
# ssb_periodicityServingCell initialULBWPstartSymbolAndLength_0 = 41;
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2; initialULBWPk2_1 = 6;
initialULBWPmappingType_1 = 1;
# dmrs_TypeA_position # this is SS=0 L=4
# 0 = pos2, 1 = pos3 initialULBWPstartSymbolAndLength_1 = 52;
dmrs_TypeA_Position = 0;
initialULBWPk2_2 = 7;
# subcarrierSpacing initialULBWPmappingType_2 = 1;
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 # this is SS=10 L=4
subcarrierSpacing = 1; initialULBWPstartSymbolAndLength_2 = 52;
msg3_DeltaPreamble = 1;
#tdd-UL-DL-ConfigurationCommon p0_NominalWithGrant =-90;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 # pucch-ConfigCommon setup :
referenceSubcarrierSpacing = 1; # pucchGroupHopping
# pattern1 # 0 = neither, 1= group hopping, 2=sequence hopping
# dl_UL_TransmissionPeriodicity pucchGroupHopping = 0;
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 hoppingId = 40;
dl_UL_TransmissionPeriodicity = 6; p0_nominal = -90;
nrofDownlinkSlots = 7; # ssb_PositionsInBurs_BitmapPR
nrofDownlinkSymbols = 6; # 1=short, 2=medium, 3=long
nrofUplinkSlots = 2; ssb_PositionsInBurst_PR = 2;
nrofUplinkSymbols = 4; ssb_PositionsInBurst_Bitmap = 1;
ssPBCH_BlockPower = -25; # ssb_periodicityServingCell
} # 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
);
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
# ------- SCTP definitions dmrs_TypeA_Position = 0;
SCTP :
{ # subcarrierSpacing
# Number of streams to use in input/output # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
SCTP_INSTREAMS = 2; subcarrierSpacing = 1;
SCTP_OUTSTREAMS = 2;
};
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
////////// AMF parameters: # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
amf_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; referenceSubcarrierSpacing = 1;
ipv6 = "192:168:30::17"; # pattern1
active = "yes"; # dl_UL_TransmissionPeriodicity
preference = "ipv4"; # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
} dl_UL_TransmissionPeriodicity = 6;
); nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
NETWORK_INTERFACES : nrofUplinkSymbols = 4;
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "eth0"; ssPBCH_BlockPower = -25;
GNB_IPV4_ADDRESS_FOR_NG_AMF = "CI_GNB_IP_ADDR"; }
GNB_INTERFACE_NAME_FOR_NGU = "eth0";
GNB_IPV4_ADDRESS_FOR_NGU = "CI_GNB_IP_ADDR"; );
GNB_PORT_FOR_NGU = 2152; # Spec 2152
};
# ------- SCTP definitions
} SCTP :
); {
# Number of streams to use in input/output
MACRLCs = ( SCTP_INSTREAMS = 2;
{ SCTP_OUTSTREAMS = 2;
num_cc = 1; };
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC"; ////////// AMF parameters:
pusch_TargetSNRx10 = 200; amf_ip_address = ( { ipv4 = "CI_MME_IP_ADDR";
pucch_TargetSNRx10 = 150; ipv6 = "192:168:30::17";
} active = "yes";
); preference = "ipv4";
}
L1s = ( );
{
num_cc = 1; NETWORK_INTERFACES :
tr_n_preference = "local_mac"; {
pusch_proc_threads = 8;
prach_dtx_threshold = 120; GNB_INTERFACE_NAME_FOR_NG_AMF = "em1";
pucch0_dtx_threshold = 150; GNB_IPV4_ADDRESS_FOR_NG_AMF = "CI_GNB_IP_ADDR";
} GNB_INTERFACE_NAME_FOR_NGU = "em1";
); GNB_IPV4_ADDRESS_FOR_NGU = "CI_GNB_IP_ADDR";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
RUs = ( };
{
local_rf = "yes" }
nb_tx = 1 );
nb_rx = 1
att_tx = 0 MACRLCs = (
att_rx = 0; {
bands = [78]; num_cc = 1;
max_pdschReferenceSignalPower = -27; tr_s_preference = "local_L1";
max_rxgain = 75; tr_n_preference = "local_RRC";
eNB_instances = [0]; pusch_TargetSNRx10 = 200;
#beamforming 1x4 matrix: pucch_TargetSNRx10 = 200;
bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000]; ulsch_max_frame_inactivity = 1;
#clock_src = "external"; }
sdr_addrs = "mgmt_addr=192.168.18.240,addr=192.168.10.2,second_addr=192.168.20.2,clock_source=internal,time_source=internal" );
}
); L1s = (
{
THREAD_STRUCT = ( num_cc = 1;
{ tr_n_preference = "local_mac";
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" pusch_proc_threads = 2;
parallel_config = "PARALLEL_SINGLE_THREAD"; prach_dtx_threshold = 120;
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" # pucch0_dtx_threshold = 150;
worker_config = "WORKER_ENABLE"; }
} );
);
RUs = (
rfsimulator : {
{ local_rf = "yes"
serveraddr = "server"; nb_tx = 1
serverport = "4043"; nb_rx = 1
options = (); #("saviq"); or/and "chanmod" att_tx = 0
modelname = "AWGN"; att_rx = 0;
IQfile = "/tmp/rfsimulator.iqs"; bands = [78];
}; max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
security = { eNB_instances = [0];
# preferred ciphering algorithms ##beamforming 1x2 matrix: 1 layer x 2 antennas
# the first one of the list that an UE supports in chosen bf_weights = [0x00007fff, 0x0000];
# valid values: nea0, nea1, nea2, nea3 ##beamforming 1x4 matrix: 1 layer x 4 antennas
ciphering_algorithms = ( "nea0" ); #bf_weights = [0x00007fff, 0x0000,0x0000, 0x0000];
## beamforming 2x2 matrix:
# preferred integrity algorithms # bf_weights = [0x00007fff, 0x00000000, 0x00000000, 0x00007fff];
# the first one of the list that an UE supports in chosen ## beamforming 4x4 matrix:
# valid values: nia0, nia1, nia2, nia3 #bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000, 0x00000000, 0x00007fff, 0x0000, 0x0000, 0x0000, 0x0000, 0x00007fff, 0x0000, 0x0000, 0x0000, 0x0000, 0x00007fff];
integrity_algorithms = ( "nia2", "nia0" ); sf_extension = 0
sdr_addrs = "mgmt_addr=192.168.18.240,addr=192.168.10.2,second_addr=192.168.20.2,clock_source=internal,time_source=internal"
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter }
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity' );
drb_ciphering = "yes";
drb_integrity = "no"; THREAD_STRUCT = (
}; {
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
log_config : parallel_config = "PARALLEL_SINGLE_THREAD";
{ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
global_log_level ="info"; worker_config = "WORKER_ENABLE";
global_log_verbosity ="medium"; }
hw_log_level ="info"; );
hw_log_verbosity ="medium";
phy_log_level ="info"; security = {
phy_log_verbosity ="medium"; # preferred ciphering algorithms
mac_log_level ="info"; # the first one of the list that an UE supports in chosen
mac_log_verbosity ="high"; # valid values: nea0, nea1, nea2, nea3
rlc_log_level ="info"; ciphering_algorithms = ( "nea0" );
rlc_log_verbosity ="medium";
pdcp_log_level ="info"; # preferred integrity algorithms
pdcp_log_verbosity ="medium"; # the first one of the list that an UE supports in chosen
rrc_log_level ="info"; # valid values: nia0, nia1, nia2, nia3
rrc_log_verbosity ="medium"; integrity_algorithms = ( "nia2", "nia0" );
ngap_log_level ="debug";
ngap_log_verbosity ="medium"; # setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
}; # what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
global_log_verbosity ="medium";
hw_log_level ="info";
hw_log_verbosity ="medium";
phy_log_level ="info";
phy_log_verbosity ="medium";
mac_log_level ="info";
mac_log_verbosity ="high";
rlc_log_level ="info";
rlc_log_verbosity ="medium";
pdcp_log_level ="info";
pdcp_log_verbosity ="medium";
rrc_log_level ="info";
rrc_log_verbosity ="medium";
f1ap_log_level ="debug";
f1ap_log_verbosity ="medium";
};
ci-scripts/xml_files/fr1_nsa_2x2_quectel.xml
View file @ c96c98e1
...@@ -74,7 +74,7 @@ ...@@ -74,7 +74,7 @@
<testCase id="040000"> <testCase id="040000">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB</desc> <desc>Initialize gNB</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.nsa_2x2.106PRB.usrpn310.conf -q --usrp-tx-thread-config 1 --thread-pool 0,2,4,6</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.nsa_2x2.106PRB.usrpn310.conf -q --usrp-tx-thread-config 1</Initialize_eNB_args>
<eNB_instance>1</eNB_instance> <eNB_instance>1</eNB_instance>
<eNB_serverId>1</eNB_serverId> <eNB_serverId>1</eNB_serverId>
<air_interface>nr</air_interface> <air_interface>nr</air_interface>
......
ci-scripts/xml_files/fr1_nsa_2x2_quectel_attach_detach.xml
View file @ c96c98e1
...@@ -94,7 +94,7 @@ ...@@ -94,7 +94,7 @@
<testCase id="041000"> <testCase id="041000">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB</desc> <desc>Initialize gNB</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.nsa_2x2.106PRB.usrpn310.conf -q --usrp-tx-thread-config 1 --thread-pool 0,2,4,6</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.nsa_2x2.106PRB.usrpn310.conf -q --usrp-tx-thread-config 1</Initialize_eNB_args>
<eNB_instance>1</eNB_instance> <eNB_instance>1</eNB_instance>
<eNB_serverId>1</eNB_serverId> <eNB_serverId>1</eNB_serverId>
<air_interface>nr</air_interface> <air_interface>nr</air_interface>
......
ci-scripts/xml_files/fr1_sa_oaiue_b200.xml
View file @ c96c98e1
...@@ -54,7 +54,7 @@ ...@@ -54,7 +54,7 @@
<testCase id="040000"> <testCase id="040000">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB</desc> <desc>Initialize gNB</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.2x2.usrpn310.conf --sa -q --usrp-tx-thread-config 1 --thread-pool 0,2,4,6</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.usrpn310.conf --sa -q --usrp-tx-thread-config 1</Initialize_eNB_args>
<eNB_instance>0</eNB_instance> <eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId> <eNB_serverId>0</eNB_serverId>
<air_interface>nr</air_interface> <air_interface>nr</air_interface>
......
ci-scripts/xml_files/fr1_sa_quectel.xml
View file @ c96c98e1
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
<testCase id="040000"> <testCase id="040000">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB</desc> <desc>Initialize gNB</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.2x2.usrpn310.conf --sa -q --usrp-tx-thread-config 1 --thread-pool 0,2,4,6</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.2x2.usrpn310.conf --sa -q --usrp-tx-thread-config 1</Initialize_eNB_args>
<eNB_instance>0</eNB_instance> <eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId> <eNB_serverId>0</eNB_serverId>
<air_interface>nr</air_interface> <air_interface>nr</air_interface>
......
ci-scripts/xml_files/fr1_sa_quectel_stages.xml
View file @ c96c98e1
...@@ -65,7 +65,7 @@ ...@@ -65,7 +65,7 @@
<testCase id="040000"> <testCase id="040000">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB</desc> <desc>Initialize gNB</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.2x2.usrpn310.conf --sa -q --usrp-tx-thread-config 1 --thread-pool 0,2,4,6</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.sa.fr1.106PRB.2x2.usrpn310.conf --sa -q --usrp-tx-thread-config 1</Initialize_eNB_args>
<eNB_instance>0</eNB_instance> <eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId> <eNB_serverId>0</eNB_serverId>
<air_interface>nr</air_interface> <air_interface>nr</air_interface>
......
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