Commit 71a5ae24 authored by Thomas Schlichter's avatar Thomas Schlichter

NR_UE: further cleanup of DMRS configuration

parent 20f88953
...@@ -186,23 +186,6 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ...@@ -186,23 +186,6 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
/////////////////////////PUSCH DMRS init///////////////////////// /////////////////////////PUSCH DMRS init/////////////////////////
/////////// ///////////
// default values until overwritten by RRCConnectionReconfiguration
for (i=0; i<MAX_NR_OF_UL_ALLOCATIONS; i++) {
ue->pusch_config.pusch_TimeDomainResourceAllocation[i] = (PUSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PUSCH_TimeDomainResourceAllocation_t));
ue->pusch_config.pusch_TimeDomainResourceAllocation[i]->mappingType = typeB;
}
for (i=0;i<MAX_NR_OF_DL_ALLOCATIONS;i++){
ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[i] = (PDSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PDSCH_TimeDomainResourceAllocation_t));
ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[i]->mappingType = typeA;
}
//------------- config DMRS parameters--------------//
ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition = pdsch_dmrs_pos0;
//-------------------------------------------------//
ue->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); ue->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***));
pusch_dmrs = ue->nr_gold_pusch_dmrs; pusch_dmrs = ue->nr_gold_pusch_dmrs;
n_scid = 0; // This quantity is indicated by higher layer parameter dmrs-SeqInitialization n_scid = 0; // This quantity is indicated by higher layer parameter dmrs-SeqInitialization
......
...@@ -701,11 +701,11 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -701,11 +701,11 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
int8_t delta = get_delta(p, config_type); int8_t delta = get_delta(p, config_type);
// checking if re-initialization of scrambling IDs is needed // checking if re-initialization of scrambling IDs is needed
if ((ue->dmrs_DownlinkConfig.scramblingID0 != ue->scramblingID[0]) || (ue->dmrs_DownlinkConfig.scramblingID1 != ue->scramblingID[1])){ /*if ((XXX.scramblingID0 != ue->scramblingID[0]) || (XXX.scramblingID1 != ue->scramblingID[1])){
ue->scramblingID[0]=ue->dmrs_DownlinkConfig.scramblingID0; ue->scramblingID[0] = XXX.scramblingID0;
ue->scramblingID[1]=ue->dmrs_DownlinkConfig.scramblingID1; ue->scramblingID[1] = XXX.scramblingID1;
nr_gold_pdsch(ue,ue->scramblingID); nr_gold_pdsch(ue,ue->scramblingID);
} }*/
nr_pdsch_dmrs_rx(ue, Ns, ue->nr_gold_pdsch[gNB_id][Ns][symbol][0], &pilot[0], 1000+p, 0, nb_rb_pdsch+rb_offset, config_type); nr_pdsch_dmrs_rx(ue, Ns, ue->nr_gold_pdsch[gNB_id][Ns][symbol][0], &pilot[0], 1000+p, 0, nb_rb_pdsch+rb_offset, config_type);
......
...@@ -968,17 +968,14 @@ typedef struct { ...@@ -968,17 +968,14 @@ typedef struct {
CellGroupConfig_t cell_group_config; CellGroupConfig_t cell_group_config;
PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig; PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig;
PDSCH_Config_t PDSCH_Config;
PUCCH_ConfigCommon_nr_t pucch_config_common_nr[NUMBER_OF_CONNECTED_gNB_MAX]; PUCCH_ConfigCommon_nr_t pucch_config_common_nr[NUMBER_OF_CONNECTED_gNB_MAX];
PUCCH_Config_t pucch_config_dedicated_nr[NUMBER_OF_CONNECTED_gNB_MAX]; PUCCH_Config_t pucch_config_dedicated_nr[NUMBER_OF_CONNECTED_gNB_MAX];
PUSCH_Config_t pusch_config;
SRS_NR srs; SRS_NR srs;
crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig; crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig;
supplementaryUplink_t supplementaryUplink; supplementaryUplink_t supplementaryUplink;
dmrs_DownlinkConfig_t dmrs_DownlinkConfig;
csi_MeasConfig_t csi_MeasConfig; csi_MeasConfig_t csi_MeasConfig;
PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig; PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig;
......
...@@ -401,62 +401,6 @@ typedef struct{ ...@@ -401,62 +401,6 @@ typedef struct{
int startSymbolAndLength; int startSymbolAndLength;
}PDSCH_TimeDomainResourceAllocation_t; }PDSCH_TimeDomainResourceAllocation_t;
typedef struct {
/*
* resourceAllocation
*/
dl_resourceAllocation_t dl_resourceAllocation;
/*
* corresponds to I, where I the number of entries in the higher layer parameter pdsch-AllocationList
*/
uint8_t n_pdsh_alloc_list;
/*
* rateMatchPatternToAddModList
*/
rateMatchPattern_t rateMatchPatternToAddModList[MAX_NR_RATE_MATCH_PATTERNS];
/*
* rateMatchPatternToReleaseList
*/
uint8_t rateMatchPatternToReleaseList[MAX_NR_RATE_MATCH_PATTERNS];
/*
* n_rateMatchPatterns indicates the number of rateMatchPatterns defined currently
*/
uint8_t n_rateMatchPatterns;
/*
* zp-CSI-RS-ResourceToAddModList
*/
zp_CSI_RS_Resource_t zp_CSI_RS_Resource[MAX_NR_ZP_CSI_RS_RESOURCES];
/*
* zp-CSI-RS-ResourceToReleaseList
*/
uint8_t zp_CSI_RS_ResourceId[MAX_NR_ZP_CSI_RS_RESOURCES];
/*
* n_zp-CSI-RS-Resource
*/
uint8_t n_zp_CSI_RS_ResourceId;
/*
* rgb_Size
*/
dl_rgb_Size_t dl_rgbSize;
/*
* prb-BundlingType
*/
prb_bundleType_t prbBundleType;
/*
* pdsch-HARQ-ACK-Codebook: this is part of the IE PhysicalCellGroupConfig which is used to configure cell-group specific L1 parameters (TS 38.331)
*/
pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook;
////////////////////////////////////////////////////////////////////////////////################################
/*
Maximum number of code words that a single DCI may schedule. This changes the number of MCS/RV/NDI bits in the DCI message from 1 to 2.
*/
maxNrofCodeWordsScheduledByDCI_t maxNrofCodeWordsScheduledByDCI;
PDSCH_TimeDomainResourceAllocation_t *pdsch_TimeDomainResourceAllocation[MAX_NR_OF_DL_ALLOCATIONS];
} PDSCH_Config_t;
/*********************************************************************** /***********************************************************************
* *
...@@ -507,6 +451,7 @@ typedef enum { ...@@ -507,6 +451,7 @@ typedef enum {
typedef enum { typedef enum {
pdsch_dmrs_pos0 = 0, pdsch_dmrs_pos0 = 0,
pdsch_dmrs_pos1 = 1, pdsch_dmrs_pos1 = 1,
pdsch_dmrs_pos2 = 2,
pdsch_dmrs_pos3 = 3, pdsch_dmrs_pos3 = 3,
} pdsch_dmrs_AdditionalPosition_t; } pdsch_dmrs_AdditionalPosition_t;
typedef enum { typedef enum {
...@@ -534,11 +479,6 @@ typedef struct { ...@@ -534,11 +479,6 @@ typedef struct {
uint16_t n_rb0; uint16_t n_rb0;
uint16_t n_rb1; uint16_t n_rb1;
} ptrs_frequency_density_t; } ptrs_frequency_density_t;
typedef struct { // The IE DMRS-DownlinkConfig is used to configure downlink demodulation reference signals for PDSCH
pdsch_dmrs_AdditionalPosition_t pdsch_dmrs_AdditionalPosition;
uint16_t scramblingID0;
uint16_t scramblingID1;
} dmrs_DownlinkConfig_t;
typedef struct { typedef struct {
/* /*
* Serving cell ID of a PSCell. The PCell of the Master Cell Group uses ID = 0 * Serving cell ID of a PSCell. The PCell of the Master Cell Group uses ID = 0
...@@ -603,53 +543,6 @@ typedef struct { ...@@ -603,53 +543,6 @@ typedef struct {
betaOffset_type_t betaOffset_type; betaOffset_type_t betaOffset_type;
betaOffset_t betaOffset; betaOffset_t betaOffset;
} uci_onPusch_t; } uci_onPusch_t;
typedef struct {
/*
* txConfig
*/
txConfig_t txConfig;
/*
* frequencyHopping
*/
frequencyHopping_t frequencyHopping;
/*
* frequencyHoppingOffsetLists
*/
uint16_t frequencyHoppingOffsetLists[4];
// n_frequencyHoppingOffsetLists contains the number of offsets listed. We can list up to 4 offsets
uint8_t n_frequencyHoppingOffsetLists;
/*
* resourceAllocation
*/
ul_resourceAllocation_t ul_resourceAllocation;
/*
* rgb_Size
*/
ul_rgb_Size_t ul_rgbSize;
/*
* corresponds to I, where I the number of entries in the higher layer parameter pusch-AllocationList
*/
uint8_t n_push_alloc_list;
/*
* transformPrecoder
*/
transformPrecoder_t transformPrecoder;
/*
* codebookSubset
*/
codebookSubset_t codebookSubset;
/*
* maxRank
*/
uint8_t maxRank;
/*
* uci_onPusch
*/
uci_onPusch_t uci_onPusch;
////////////////////////////////////////////////////////////////////////////////################################
PUSCH_PowerControl_t pusch_PowerControl;
PUSCH_TimeDomainResourceAllocation_t *pusch_TimeDomainResourceAllocation[MAX_NR_OF_UL_ALLOCATIONS];
} PUSCH_Config_t;
/*********************************************************************** /***********************************************************************
* *
......
...@@ -1155,7 +1155,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -1155,7 +1155,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
} }
} }
if (ue->mac_enabled == 1) { if (ue->mac_enabled == 1) { // TODO: move this from PHY to MAC layer!
/* Time Alignment procedure /* Time Alignment procedure
// - UE processing capability 1 // - UE processing capability 1
...@@ -1176,11 +1176,34 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -1176,11 +1176,34 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
const int Ta_max = 3846; // Max value of 12 bits TA Command const int Ta_max = 3846; // Max value of 12 bits TA Command
const double N_TA_max = Ta_max * bw_scaling * tc_factor; const double N_TA_max = Ta_max * bw_scaling * tc_factor;
NR_UE_MAC_INST_t *mac = get_mac_inst(0);
NR_BWP_Id_t ul_bwp_id = mac->UL_BWP_Id;
NR_PUSCH_Config_t *pusch_Config = mac->ULbwp[ul_bwp_id-1]->bwp_Dedicated->pusch_Config->choice.setup;
NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = pusch_Config->pusch_TimeDomainAllocationList->choice.setup;
long mapping_type_ul = pusch_TimeDomainAllocationList->list.array[0]->mappingType;
NR_BWP_Id_t dl_bwp_id = mac->DL_BWP_Id;
NR_PDSCH_Config_t *pdsch_Config = mac->DLbwp[dl_bwp_id-1]->bwp_Dedicated->pdsch_Config->choice.setup;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = pdsch_Config->pdsch_TimeDomainAllocationList->choice.setup;
long mapping_type_dl = pdsch_TimeDomainAllocationList->list.array[0]->mappingType;
NR_DMRS_DownlinkConfig_t *NR_DMRS_dlconfig;
if (mapping_type_dl == NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA)
NR_DMRS_dlconfig = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
else
NR_DMRS_dlconfig = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB->choice.setup;
pdsch_dmrs_AdditionalPosition_t add_pos_dl = pdsch_dmrs_pos2;
if (NR_DMRS_dlconfig->dmrs_AdditionalPosition)
add_pos_dl = *NR_DMRS_dlconfig->dmrs_AdditionalPosition;
/* PDSCH decoding time N_1 for processing capability 1 */ /* PDSCH decoding time N_1 for processing capability 1 */
int N_1; int N_1;
if (ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == pdsch_dmrs_pos0)
if (add_pos_dl == pdsch_dmrs_pos0)
N_1 = pdsch_N_1_capability_1[numerology][1]; N_1 = pdsch_N_1_capability_1[numerology][1];
else if (ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == pdsch_dmrs_pos1 || ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == 2) // TODO set to pdsch_dmrs_pos2 when available else if (add_pos_dl == pdsch_dmrs_pos1 || add_pos_dl == pdsch_dmrs_pos2)
N_1 = pdsch_N_1_capability_1[numerology][2]; N_1 = pdsch_N_1_capability_1[numerology][2];
else else
N_1 = pdsch_N_1_capability_1[numerology][3]; N_1 = pdsch_N_1_capability_1[numerology][3];
...@@ -1191,8 +1214,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -1191,8 +1214,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
/* d_1_1 depending on the number of PDSCH symbols allocated */ /* d_1_1 depending on the number of PDSCH symbols allocated */
const int d = 0; // TODO number of overlapping symbols of the scheduling PDCCH and the scheduled PDSCH const int d = 0; // TODO number of overlapping symbols of the scheduling PDCCH and the scheduled PDSCH
int d_1_1 = 0; int d_1_1 = 0;
mappingType_t mapping_type_dl = ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[0]->mappingType; if (mapping_type_dl == NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA)
if (mapping_type_dl == typeA)
if (nb_symb_sch + start_symbol < 7) if (nb_symb_sch + start_symbol < 7)
d_1_1 = 7 - (nb_symb_sch + start_symbol); d_1_1 = 7 - (nb_symb_sch + start_symbol);
else else
...@@ -1207,8 +1229,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -1207,8 +1229,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
/* d_2_1 */ /* d_2_1 */
int d_2_1; int d_2_1;
mappingType_t mapping_type_ul = ue->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; if (mapping_type_ul == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB && start_symbol != 0)
if (mapping_type_ul == typeB && start_symbol != 0)
d_2_1 = 0; d_2_1 = 0;
else else
d_2_1 = 1; d_2_1 = 1;
......
...@@ -158,13 +158,14 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, ...@@ -158,13 +158,14 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue,
} }
} }
int k2;
if (power_config->twoPUCCH_PC_AdjustmentStates > 1) { if (power_config->twoPUCCH_PC_AdjustmentStates > 1) {
LOG_E(PHY,"PUCCH power control adjustment states with 2 states not yet implemented : at line %d in function %s of file %s \n", LINE_FILE , __func__, __FILE__); LOG_E(PHY,"PUCCH power control adjustment states with 2 states not yet implemented : at line %d in function %s of file %s \n", LINE_FILE , __func__, __FILE__);
return (PUCCH_POWER_DEFAULT); return (PUCCH_POWER_DEFAULT);
} }
#if 0
int k2;
/* response to a detection by the UE of a DCI format 1_0 or DCI format 1_1 */ /* response to a detection by the UE of a DCI format 1_0 or DCI format 1_1 */
//int K_PUCCH = 0; //int K_PUCCH = 0;
if (O_ACK != 0) { if (O_ACK != 0) {
...@@ -201,6 +202,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, ...@@ -201,6 +202,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue,
} }
//K_PUCCH = N_SYMB_SLOT * k2; /* the product of a number of symbols per slot and the minimum of the values provided by higher layer parameter k2 */ //K_PUCCH = N_SYMB_SLOT * k2; /* the product of a number of symbols per slot and the minimum of the values provided by higher layer parameter k2 */
} }
#endif
int contributor = (10 * log10((double)(pow(2,(ue->frame_parms.numerology_index)) * nb_of_prbs))); int contributor = (10 * log10((double)(pow(2,(ue->frame_parms.numerology_index)) * nb_of_prbs)));
......
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