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Commit a64a892a authored by Mario Joa-Ng's avatar Mario Joa-Ng
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remove #if 0

parent 626e3a70
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Showing with 1 addition and 186 deletions
openair2/LAYER2/NR_MAC_UE/main_ue_nr.c
View file @ a64a892a
......@@ -54,7 +54,6 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst) {
for (int j=0;j<NB_NR_UE_MAC_INST;j++) {
nr_ue_init_mac(j);
for (int i=0;i<NR_MAX_HARQ_PROCESSES;i++) nr_ue_mac_inst[j].first_ul_tx[i]=1;
}
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ a64a892a
......@@ -197,6 +197,7 @@ void nr_ue_init_mac(module_id_t module_idP) {
mac->scheduling_info.LCID_status[i] =
LCID_EMPTY;
mac->scheduling_info.LCID_buffer_remain[i] = 0;
for (int i=0;i<NR_MAX_HARQ_PROCESSES;i++) mac->first_ul_tx[i]=1;
}
}
......@@ -2214,61 +2215,6 @@ int8_t nr_ue_get_SR(module_id_t module_idP, frame_t frameP, slot_t slot){
// no UL-SCH resources available for this tti && UE has a valid PUCCH resources for SR configuration for this tti
DevCheck(module_idP < (int) NB_UE_INST, module_idP, NB_NR_UE_MAC_INST, 0);
NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
#if 0 // todo
// int MGL=6;// measurement gap length in ms
int MGRP = 0; // measurement gap repetition period in ms
int gapOffset = -1;
int T = 0;
// determin the measurement gap
if (mac->measGapConfig != NULL) {
if (mac->measGapConfig->choice.setup.
gapOffset.present == LTE_MeasGapConfig__setup__gapOffset_PR_gp0) {
MGRP = 40;
gapOffset =
mac->measGapConfig->choice.
setup.gapOffset.choice.gp0;
} else if (mac->measGapConfig->choice.
setup.gapOffset.present ==
LTE_MeasGapConfig__setup__gapOffset_PR_gp1) {
MGRP = 80;
gapOffset =
mac->measGapConfig->choice.
setup.gapOffset.choice.gp1;
} else {
LOG_W(NR_MAC, "Measurement GAP offset is unknown\n");
}
T = MGRP / 10;
DevAssert(T != 0);
//check the measurement gap and sr prohibit timer
if ((subframe == gapOffset % 10)
&& ((frameP % T) == (floor(gapOffset / 10)))
&& (mac->
scheduling_info.sr_ProhibitTimer_Running == 0)) {
mac->scheduling_info.SR_pending = 1;
return (0);
}
}
if ((mac->physicalConfigDedicated != NULL) &&
(mac->scheduling_info.SR_pending == 1) &&
(mac->scheduling_info.SR_COUNTER <
(1 <<
(2 +
mac->
physicalConfigDedicated->schedulingRequestConfig->choice.setup.
dsr_TransMax)))) {
LOG_D(NR_MAC,
"[UE %d] Frame %d slot %d PHY asks for SR (SR_COUNTER/dsr_TransMax %d/%d), SR_pending %d\n",
module_idP, frameP, slot,
mac->scheduling_info.SR_COUNTER,
(1 <<
(2 +
mac->
physicalConfigDedicated->schedulingRequestConfig->choice.
setup.dsr_TransMax)),
mac->scheduling_info.SR_pending);
#endif
DSR_TRANSMAX_t dsr_TransMax = sr_n64; // todo
LOG_D(NR_MAC,
"[UE %d] Frame %d slot %d send SR indication (SR_COUNTER/dsr_TransMax %d/%d), SR_pending %d\n",
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ a64a892a
......@@ -1011,50 +1011,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
// Handle the SR/BSR procedures per subframe
NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
uint8_t gNB_indexP=0;
#if 0 // todo
// Get RLC status info and update Bj for all lcids that are active
int lcid; // lcid index
for (lcid = DCCH; lcid < NR_MAX_NUM_LCID; lcid++) {
if (mac->logicalChannelConfig[lcid]) {
// meausre the Bj
if ((directionP == SF_UL)
&& (mac->scheduling_info.Bj[lcid] >= 0)) {
if (mac->
logicalChannelConfig[lcid]->ul_SpecificParameters) {
bucketsizeduration =
mac->logicalChannelConfig
[lcid]->ul_SpecificParameters->prioritisedBitRate *
TTI;
bucketsizeduration_max =
get_ms_bucketsizeduration(mac->logicalChannelConfig
[lcid]->ul_SpecificParameters->bucketSizeDuration);
} else {
LOG_E(NR_MAC,
"[UE %d] lcid %d, NULL ul_SpecificParameters\n",
mod_id, lcid);
AssertFatal(1 == 0, "");
}
if (mac->scheduling_info.Bj[lcid] >
bucketsizeduration_max) {
mac->scheduling_info.Bj[lcid] =
bucketsizeduration_max;
} else {
mac->scheduling_info.Bj[lcid] =
bucketsizeduration;
}
}
/*
if (lcid == DCCH) {
LOG_D(NR_MAC,"[UE %d][SR] Frame %d slot %d Pending data for SRB1=%d for LCGID %d \n",
mod_id, txFrameP,txSlotP,mac->scheduling_info.BSR[mac->scheduling_info.LCGID[lcid]],
// mac->scheduling_info.LCGID[lcid]);
}
*/
}
}
#endif
// Call BSR procedure as described in Section 5.4.5 in 38.321
// First check ReTxBSR Timer because it is always configured
......@@ -1084,33 +1041,6 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
"[UE %d][BSR] Regular BSR Triggered Frame %d slot %d SR for PUSCH is pending\n",
mod_id, txFrameP, txSlotP);
}
#if 0
// UE has no valid phy config dedicated || no valid/released SR
if ((mac->physicalConfigDedicated == NULL)) {
// cancel all pending SRs
mac->scheduling_info.SR_pending = 0;
mac->ul_active = 0;
LOG_T(NR_MAC, "[UE %d] Release all SRs \n", mod_id);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SCHEDULER, VCD_FUNCTION_OUT);
#if UE_TIMING_TRACE
stop_meas(&mac->nr_ue_scheduler);
#endif
return (CONNECTION_OK);
}
if ((mac->
physicalConfigDedicated->schedulingRequestConfig == NULL)
|| (mac->
physicalConfigDedicated->schedulingRequestConfig->present ==
LTE_SchedulingRequestConfig_PR_release)) {
// initiate RA with CRNTI included in msg3 (no contention) as descibed in 38.321 sec 5.1.5
// cancel all pending SRs
mac->scheduling_info.SR_pending = 0;
mac->ul_active = 0;
LOG_T(NR_MAC, "[UE %d] Release all SRs \n", mod_id);
}
#endif
return UE_CONNECTION_OK;
}
......@@ -2548,23 +2478,6 @@ uint8_t nr_ue_get_sdu(module_id_t module_idP,
}
bsr_len = bsr_ce_len + bsr_header_len;
#if 0 // todo
phr_ce_len =
(mac->PHR_reporting_active ==
1) ? 1 /* sizeof(POWER_HEADROOM_CMD) */ : 0;
if ((phr_ce_len > 0)
&& ((phr_ce_len + phr_header_len + bsr_len) <= buflen)) {
phr_len = phr_ce_len + phr_header_len;
LOG_D(NR_MAC,
"[UE %d] header size info: PHR len %d (ce%d,hdr%d) buff_len %d\n",
module_idP, phr_len, phr_ce_len, phr_header_len, buflen);
} else {
phr_len = 0;
phr_header_len = 0;
phr_ce_len = 0;
}
#endif
int tot_mac_ce_len = bsr_len + phr_len;
uint8_t total_mac_pdu_header_len = tot_mac_ce_len;
......@@ -2665,25 +2578,6 @@ uint8_t nr_ue_get_sdu(module_id_t module_idP,
scheduling_info.LCGID[lcid]]
== 0)) {
num_lcg_id_with_data--;
#if 0 // Disable the following to simplify the logic
// Change BSR size to BSR SHORT if num_lcg_id_with_data becomes to 1
if (bsr_len) {
if (num_lcg_id_with_data == 1) {
bsr_ce_len = sizeof(NR_BSR_SHORT);
bsr_header_len = sizeof(NR_MAC_SUBHEADER_FIXED);
bsr_len = bsr_ce_len + bsr_header_len;
total_mac_pdu_header_len = total_mac_pdu_header_len - tot_mac_ce_len + bsr_len + phr_len;
tot_mac_ce_len = bsr_len + phr_len;
}
else if (num_lcg_id_with_data > 1) {
bsr_ce_len = num_lcg_id_with_data + 1;
bsr_header_len = sizeof(NR_MAC_SUBHEADER_SHORT);
bsr_len = bsr_ce_len + bsr_header_len;
total_mac_pdu_header_len = total_mac_pdu_header_len - tot_mac_ce_len + bsr_len + phr_len;
tot_mac_ce_len = bsr_len + phr_len;
}
}
#endif
}
}
}
......@@ -2710,30 +2604,6 @@ uint8_t nr_ue_get_sdu(module_id_t module_idP,
}
}
#if 0 // todo
// build PHR and update the timers
if (phr_ce_len == sizeof(POWER_HEADROOM_CMD)) {
if(NFAPI_MODE==NFAPI_UE_STUB_PNF) {
//Substitute with a static value for the MAC layer abstraction (phy_stub mode)
phr_p->PH = 60;
} else {
phr_p->PH = get_phr_mapping(module_idP, CC_id, eNB_index);
}
phr_p->R = 0;
LOG_D(NR_MAC,
"[UE %d] Frame %d report PHR with mapping (%d->%d) for LCID %d\n",
module_idP, frameP, get_PHR(module_idP, CC_id, eNB_index),
phr_p->PH, POWER_HEADROOM);
update_phr(module_idP, CC_id);
} else {
phr_p = NULL;
}
LOG_T(NR_MAC, "[UE %d] Frame %d: bsr s %p bsr_l %p, phr_p %p\n",
module_idP, frameP, bsr_s, bsr_l, phr_p);
#endif
// TS 38.321 Section 5.4.5
// Check BSR padding: it is done after PHR according to Logical Channel Prioritization order
// Check for max padding size, ie MAC Hdr for last RLC PDU = 1
......
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