Commit a7ab50e8 authored by Francesco Mani's avatar Francesco Mani

scheduling PRACH and filling fapi PRACH PDU

parent eda3a76e
...@@ -1028,10 +1028,12 @@ typedef struct ...@@ -1028,10 +1028,12 @@ typedef struct
{ {
uint16_t phys_cell_id; uint16_t phys_cell_id;
uint8_t num_prach_ocas; uint8_t num_prach_ocas;
// SCF PRACH PDU format field does not consider A1/B1 etc. possibilities
// We added 9 = A1/B1 10 = A2/B2 11 A3/B3
uint8_t prach_format; uint8_t prach_format;
uint8_t num_ra; uint8_t num_ra;
uint8_t prach_start_symbol; uint8_t prach_start_symbol;
uint16_t num_cs;// uint16_t num_cs;
nfapi_nr_ul_beamforming_t beamforming; nfapi_nr_ul_beamforming_t beamforming;
} nfapi_nr_prach_pdu_t; } nfapi_nr_prach_pdu_t;
......
...@@ -37,18 +37,6 @@ uint16_t nr_du[838]; ...@@ -37,18 +37,6 @@ uint16_t nr_du[838];
/************************************* /*************************************
* The following tables defined for NR * The following tables defined for NR
**************************************/ **************************************/
// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz
uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419};
uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A
uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B
// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz
uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419};
uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A
uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B
// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3}
uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69};
//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 //Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839
uint16_t prach_root_sequence_map_0_3[838] = { uint16_t prach_root_sequence_map_0_3[838] = {
......
...@@ -218,9 +218,9 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, ...@@ -218,9 +218,9 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex,
AssertFatal(zeroCorrelationZoneConfig<=15, AssertFatal(zeroCorrelationZoneConfig<=15,
"FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig );
if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; /* if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig];
if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig]; if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig];
if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig]; if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig];*/
num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC);
...@@ -235,7 +235,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, ...@@ -235,7 +235,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex,
AssertFatal(zeroCorrelationZoneConfig<=14, AssertFatal(zeroCorrelationZoneConfig<=14,
"FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig );
if (prach_fmt<3){ /* if (prach_fmt<3){
if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME
if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME
} }
...@@ -245,7 +245,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, ...@@ -245,7 +245,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex,
} }
if (prach_fmt>3){ if (prach_fmt>3){
} }*/
nr_fill_du(prach_fmt); nr_fill_du(prach_fmt);
......
...@@ -391,15 +391,15 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) ...@@ -391,15 +391,15 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) {
nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req;
int num_pusch_pdu = UL_tti_req->n_pdus; int num_pdus = UL_tti_req->n_pdus;
LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu); LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus);
gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0;
for (int i = 0; i < num_pusch_pdu; i++) { for (int i = 0; i < num_pdus; i++) {
switch (UL_tti_req->pdus_list[i].pdu_type) { switch (UL_tti_req->pdus_list[i].pdu_type) {
case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:{ case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx);
nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
...@@ -418,7 +418,13 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) ...@@ -418,7 +418,13 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid);
nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC
nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0);
} break;
case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx);
break;
case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE\n",frame_rx,slot_rx);
break;
} }
} }
} }
...@@ -32,6 +32,52 @@ ...@@ -32,6 +32,52 @@
#include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h"
// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz
uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419};
uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A
uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B
// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz
uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419};
uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A
uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B
// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3}
uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69};
uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) {
if (format0 < 3) {
switch(restricted_set_config){
case 0:
return(NCS_unrestricted_delta_f_RA_125[index]);
case 1:
return(NCS_restricted_TypeA_delta_f_RA_125[index]);
case 2:
return(NCS_restricted_TypeB_delta_f_RA_125[index]);
default:
AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config);
}
}
else {
if (format0 == 3) {
switch(restricted_set_config){
case 0:
return(NCS_unrestricted_delta_f_RA_5[index]);
case 1:
return(NCS_restricted_TypeA_delta_f_RA_5[index]);
case 2:
return(NCS_restricted_TypeB_delta_f_RA_5[index]);
default:
AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config);
}
}
else
return(NCS_unrestricted_delta_f_RA_15[index]);
}
}
// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink // Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink
// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. // the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent.
// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. // E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9.
......
...@@ -53,6 +53,8 @@ int get_nr_prach_info_from_index(uint8_t index, ...@@ -53,6 +53,8 @@ int get_nr_prach_info_from_index(uint8_t index,
uint8_t *N_t_slot, uint8_t *N_t_slot,
uint8_t *N_dur); uint8_t *N_dur);
uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config);
typedef enum { typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0, NR_DL_DCI_FORMAT_1_0 = 0,
NR_DL_DCI_FORMAT_1_1, NR_DL_DCI_FORMAT_1_1,
......
...@@ -122,13 +122,23 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm ...@@ -122,13 +122,23 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
} }
} }
lte_frame_type_t frame_type;
uint16_t band;
int32_t offset;
get_band((cfg->carrier_config.dl_frequency.value)*1000,
&band,
&offset,
&frame_type);
RC.nrmac[Mod_idP]->common_channels[0].frame_type = frame_type;
// Cell configuration // Cell configuration
cfg->cell_config.phy_cell_id.value = *scc->physCellId; cfg->cell_config.phy_cell_id.value = *scc->physCellId;
cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG; cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG;
cfg->num_tlv++; cfg->num_tlv++;
cfg->cell_config.frame_duplex_type.value = 1; cfg->cell_config.frame_duplex_type.value = frame_type;
cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG; cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG;
cfg->num_tlv++; cfg->num_tlv++;
......
...@@ -263,18 +263,122 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram ...@@ -263,18 +263,122 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram
} }
*/ */
/*
void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
// schedule PRACH for iniital BWP
if (is_initialBWP_prach_subframe(frameP,subframeP)<0) return; void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
// fill FAPI gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = gNB->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0];
uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex;
uint8_t mu,N_dur,N_t_slot,start_symbol;
uint16_t format;
if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing)
mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing;
else
mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
// prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4
if ( get_nr_prach_info_from_index(config_index,
(int)frameP,
(int)slotP,
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA,
mu,
cc->frame_type,
&format,
&start_symbol,
&N_t_slot,
&N_dur) ) {
int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM;
uint16_t format0 = format&0xff; // first column of format from table
uint16_t format1 = (format>>8)&0xff; // second column of format from table
UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP;
for (int n=0; n<(1<<fdm); n++) { // one structure per frequency domain occasion
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t);
nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu;
memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t));
UL_tti_req->n_pdus+=1;
// filling the prach fapi structure
prach_pdu->phys_cell_id = *scc->physCellId;
prach_pdu->num_prach_ocas = N_t_slot;
prach_pdu->prach_start_symbol = start_symbol;
prach_pdu->num_ra = n;
prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig,
format0,
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig);
// SCF PRACH PDU format field does not consider A1/B1 etc. possibilities
// We added 9 = A1/B1 10 = A2/B2 11 A3/B3
if (format1!=0xff) {
switch(format0) {
case 0xa1:
prach_pdu->prach_format = 9;
break;
case 0xa2:
prach_pdu->prach_format = 10;
break;
case 0xa3:
prach_pdu->prach_format = 10;
break;
default:
AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format");
}
}
else{
switch(format0) {
case 0xa1:
prach_pdu->prach_format = 0;
break;
case 0xa2:
prach_pdu->prach_format = 1;
break;
case 0xa3:
prach_pdu->prach_format = 2;
break;
case 0xb1:
prach_pdu->prach_format = 3;
break;
case 0xb2:
prach_pdu->prach_format = 4;
break;
case 0xb3:
prach_pdu->prach_format = 5;
break;
case 0xb4:
prach_pdu->prach_format = 6;
break;
case 0xc0:
prach_pdu->prach_format = 7;
break;
case 0xc2:
prach_pdu->prach_format = 8;
break;
case 0:
// long formats are handled @ PHY
break;
case 1:
// long formats are handled @ PHY
break;
case 2:
// long formats are handled @ PHY
break;
case 3:
// long formats are handled @ PHY
break;
default:
AssertFatal(1==0,"Invalid PRACH format");
}
}
}
}
} }
*/
/* /*
void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
...@@ -382,7 +486,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -382,7 +486,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// Phytest scheduling // Phytest scheduling
if (phy_test && slot_txP==1){ if (phy_test && slot_txP==1){
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL);
nr_schedule_RA(module_idP, frame_txP, slot_txP); //nr_schedule_RA(module_idP, frame_txP, slot_txP);
// resetting ta flag // resetting ta flag
gNB->ta_len = 0; gNB->ta_len = 0;
} }
...@@ -396,6 +500,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -396,6 +500,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} //is_nr_DL_slot } //is_nr_DL_slot
if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) {
schedule_nr_prach(module_idP, frame_rxP, slot_rxP);
if (phy_test && slot_rxP==8){ if (phy_test && slot_rxP==8){
nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
} }
......
...@@ -716,11 +716,11 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -716,11 +716,11 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
UL_tti_req->SFN = frameP; UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP; UL_tti_req->Slot = slotP;
UL_tti_req->n_pdus = 1; UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu;
nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t));
UL_tti_req->n_pdus+=1;
LOG_D(MAC, "Scheduling UE specific PUSCH\n"); LOG_D(MAC, "Scheduling UE specific PUSCH\n");
//UL_tti_req = &nr_mac->UL_tti_req[CC_id]; //UL_tti_req = &nr_mac->UL_tti_req[CC_id];
......
...@@ -141,6 +141,7 @@ typedef struct { ...@@ -141,6 +141,7 @@ typedef struct {
int p_gNB; int p_gNB;
int Ncp; int Ncp;
int nr_band; int nr_band;
lte_frame_type_t frame_type;
uint64_t dl_CarrierFreq; uint64_t dl_CarrierFreq;
NR_BCCH_BCH_Message_t *mib; NR_BCCH_BCH_Message_t *mib;
NR_ServingCellConfigCommon_t *ServingCellConfigCommon; NR_ServingCellConfigCommon_t *ServingCellConfigCommon;
......
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