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OpenXG-RAN
Commit d2c996f7 authored by Sakthivel Velumani's avatar Sakthivel Velumani
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Added cmd line options 

for DL and UL MCS,
  DL and UL bandwidth (in PRBs)
  DL and UL slot scheduling bitmap
parent 228be922
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Showing with 29 additions and 10 deletions
executables/nr-softmodem-common.h
View file @ d2c996f7
......@@ -68,11 +68,15 @@
#define CONFIG_HLP_SOFTS "Enable soft scope and L1 and L2 stats (Xforms)\n"
#define CONFIG_HLP_EXMCAL "Calibrate the EXMIMO borad, available files: exmimo2_2arxg.lime exmimo2_2brxg.lime \n"
#define CONFIG_HLP_ITTIL "Generate ITTI analyzser logs (similar to wireshark logs but with more details)\n"
#define CONFIG_HLP_DLMCS "Set the maximum downlink MCS\n"
#define CONFIG_HLP_DLMCS "Set the downlink MCS for PHYTEST mode\n"
#define CONFIG_HLP_STMON "Enable processing timing measurement of lte softmodem on per subframe basis \n"
#define CONFIG_HLP_PRB "Set the PRB, valid values: 6, 25, 50, 100 \n"
#define CONFIG_HLP_MSLOTS "Skip the missed slots/subframes \n"
#define CONFIG_HLP_ULMCS "Set the maximum uplink MCS\n"
#define CONFIG_HLP_ULMCS "Set the uplink MCS for PHYTEST mode\n"
#define CONFIG_HLP_DLBW "Set the downlink banwdwidth (in PRBs) for PHYTEST mode\n"
#define CONFIG_HLP_ULBW "Set the uplink banwdwidth (in PRBs) for PHYTEST mode\n"
#define CONFIG_HLP_DLBM "Bitmap for DLSCH slots (slot 0 starts at LSB)\n"
#define CONFIG_HLP_ULBM "Bitmap for ULSCH slots (slot 0 starts at LSB)\n"
#define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n"
#define CONFIG_HLP_UE "Set the lte softmodem as a UE\n"
#define CONFIG_HLP_L2MONW "Enable L2 wireshark messages on localhost \n"
......
executables/nr-softmodem.c
View file @ d2c996f7
......@@ -162,8 +162,12 @@ int otg_enabled;
//static NR_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
//static nfapi_nr_config_request_t *config[MAX_NUM_CCs];
uint32_t target_dl_mcs = 28; //maximum allowed mcs
uint32_t target_ul_mcs = 20;
uint32_t target_dl_mcs = 9;
uint32_t target_ul_mcs = 9;
uint32_t target_dl_bw = 50;
uint32_t target_ul_bw = 50;
uint64_t dlsch_slot_bitmap = (1<<1);
uint64_t ulsch_slot_bitmap = (1<<8);
uint32_t timing_advance = 0;
uint64_t num_missed_slots=0; // counter for the number of missed slots
......
executables/nr-softmodem.h
View file @ d2c996f7
......@@ -25,12 +25,22 @@
{"K" , CONFIG_HLP_ITTIL, PARAMFLAG_NOFREE, strptr:&itti_dump_file, defstrval:"/tmp/itti.dump", TYPE_STRING, 0}, \
{"m" , CONFIG_HLP_DLMCS, 0, uptr:&target_dl_mcs, defintval:0, TYPE_UINT, 0}, \
{"t" , CONFIG_HLP_ULMCS, 0, uptr:&target_ul_mcs, defintval:0, TYPE_UINT, 0}, \
{"M" , CONFIG_HLP_DLBW, 0, uptr:&target_dl_bw, defintval:0, TYPE_UINT, 0}, \
{"T" , CONFIG_HLP_ULBW, 0, uptr:&target_ul_bw, defintval:0, TYPE_UINT, 0}, \
{"D" , CONFIG_HLP_DLBM, 0, uptr:&dlsch_slot_bitmap, defintval:0, TYPE_UINT, 0}, \
{"U" , CONFIG_HLP_ULBM, 0, uptr:&ulsch_slot_bitmap, defintval:0, TYPE_UINT, 0}, \
{"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, iptr:&usrp_tx_thread, defstrval:0, TYPE_INT, 0}, \
{"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \
}
#include "threads_t.h"
extern threads_t threads;
extern uint32_t target_dl_mcs;
extern uint32_t target_ul_mcs;
extern uint32_t target_dl_bw;
extern uint32_t target_ul_bw;
extern uint64_t dlsch_slot_bitmap;
extern uint64_t ulsch_slot_bitmap;
// In nr-gnb.c
extern void init_gNB(int single_thread_flag,int wait_for_sync);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @ d2c996f7
......@@ -52,6 +52,7 @@
#include "intertask_interface.h"
#include "executables/softmodem-common.h"
#include "executables/nr-softmodem.h"
uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
......@@ -360,8 +361,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
}
const uint64_t dlsch_in_slot_bitmap = (1 << 1) | (1 << 2);
const uint64_t ulsch_in_slot_bitmap = (1 << 8);
const uint64_t dlsch_in_slot_bitmap = dlsch_slot_bitmap;
const uint64_t ulsch_in_slot_bitmap = ulsch_slot_bitmap;
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ d2c996f7
......@@ -338,7 +338,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
sched_ctrl->rbStart = rbStart;
sched_ctrl->rbSize = rbSize;
sched_ctrl->rbSize = target_dl_bw;
sched_ctrl->time_domain_allocation = 2;
if (!UE_info->secondaryCellGroup[UE_id]->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table)
sched_ctrl->mcsTableIdx = 0;
......@@ -348,7 +348,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
else
sched_ctrl->mcsTableIdx = 2;
}
sched_ctrl->mcs = 9;
sched_ctrl->mcs = target_dl_mcs;
sched_ctrl->numDmrsCdmGrpsNoData = 1;
/* mark the corresponding RBs as used */
......@@ -396,7 +396,7 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
return;
const uint16_t rbStart = 0;
const uint16_t rbSize = 50; /* due to OAI UE limitations */
const uint16_t rbSize = target_ul_bw;
uint16_t *vrb_map_UL =
&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * 275];
for (int i = rbStart; i < rbStart + rbSize; ++i) {
......@@ -456,7 +456,7 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
num_dmrs_cdm_grps_no_data,
ps);
const int mcs = 9;
const int mcs = target_ul_mcs;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
sched_pusch->mcs = mcs;
sched_pusch->rbStart = rbStart;
......
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