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OpenXG-RAN
Commit f29b5c50 authored by Sakthivel Velumani's avatar Sakthivel Velumani
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openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
View file @ f29b5c50
......@@ -234,36 +234,6 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
gNB->pdcch_pdu[pdcch_id].frame = frame;
gNB->pdcch_pdu[pdcch_id].slot = slot;
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
//uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i];
int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE);
if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){
LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id);
return;
}
dlsch = gNB->dlsch[dlsch_id][0];
int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value);
int harq_pid = slot % num_slots_tdd;
dlsch->slot_tx[slot] = 1;
dlsch->harq_ids[frame%2][slot] = harq_pid;
AssertFatal(harq_pid < 8 && harq_pid >= 0,
"illegal harq_pid %d\n",harq_pid);
dlsch->harq_mask |= (1<<harq_pid);
dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i];
// nr_fill_cce_list(gNB,0);
/*
LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]);
LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx);
*/
}
}
......
openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c
View file @ f29b5c50
......@@ -285,17 +285,27 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &pdsch_pdu->pdsch_pdu_rel15;
int dlsch_id = find_nr_dlsch(rel15->rnti,gNB,SEARCH_EXIST);
int dlsch_id = find_nr_dlsch(rel15->rnti,gNB,SEARCH_EXIST_OR_FREE);
AssertFatal( (dlsch_id>=0) && (dlsch_id<NUMBER_OF_NR_DLSCH_MAX),
"illegal or no dlsch_id found!!! rnti %04x dlsch_id %d\n",rel15->rnti,dlsch_id);
NR_gNB_DLSCH_t *dlsch = gNB->dlsch[dlsch_id][0];
NR_DL_gNB_HARQ_t **harq = dlsch->harq_processes;
int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value);
int harq_pid = slot % num_slots_tdd;
dlsch->slot_tx[slot] = 1;
dlsch->harq_ids[frame%2][slot] = harq_pid;
AssertFatal(harq_pid < 8 && harq_pid >= 0,
"illegal harq_pid %d\n",harq_pid);
dlsch->harq_mask |= (1<<harq_pid);
dlsch->rnti = rel15->rnti;
/// DLSCH struct
memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_tti_pdsch_pdu));
gNB->num_pdsch_rnti[slot]++;
AssertFatal(sdu!=NULL,"sdu is null\n");
harq[dlsch->harq_ids[frame%2][slot]]->pdu = sdu;
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @ f29b5c50
......@@ -449,7 +449,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// hardcoding dlsch to be in slot 1
if (get_softmodem_params()->phy_test) {
if (slot==0) {
*dlsch_in_slot_bitmap = 0x1FC3E; // 1 to 6 & 10 to 16
*dlsch_in_slot_bitmap = 0x1FC7E; // 1 to 6 & 10 to 16
*ulsch_in_slot_bitmap = 0xC0300; // 8,9,18,19
}
} else {
......@@ -533,6 +533,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
}
memset(RC.nrmac[module_idP]->dci_pdus,0,MAX_DCI_CORESET*sizeof(dci_mac_pdus_t));
RC.nrmac[module_idP]->dci_pdus.num_dci_pdus = 0;
// This schedules the DCI for Uplink and subsequently PUSCH
if (UE_list->fiveG_connected[UE_id]) {
int tda = 1; // time domain assignment hardcoded for now
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @ f29b5c50
......@@ -681,7 +681,7 @@ void nr_generate_Msg2(module_id_t module_idP,
dci_pdu_rel15[0].mcs,
dci_pdu_rel15[0].tb_scaling);
nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, RA_rnti, 0, ss, scc, bwp);
nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, RA_rnti, 0, ss, scc, bwp, 1);
LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x\n", frameP, slotP, RA_rnti);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ f29b5c50
......@@ -413,7 +413,8 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp){
NR_BWP_Downlink_t *bwp,
bool doCCEAlloc){
int CCEIndex = -1;
int cid = 0;
......@@ -512,6 +513,7 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
&nr_of_candidates,
ss);
if (doCCEAlloc)
CCEIndex = allocate_nr_CCEs(nr_mac,
1, // bwp_id
cid,
......@@ -520,6 +522,9 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
0, // UE-id
0); // m
else
CCEIndex=0;
if (CCEIndex<0)
return (CCEIndex);
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ f29b5c50
......@@ -217,7 +217,8 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp);
NR_BWP_Downlink_t *bwp,
bool doCCEAlloc);
void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc,
NR_CellGroupConfig_t *secondaryCellGroup,
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ f29b5c50
......@@ -337,6 +337,14 @@ typedef struct {
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
} NR_UE_list_t;
/*! \brif struct used to store DCI information for scheduling*/
typedef struct dci_mac_pdus {
int num_dci_pdus;
int dci_formats[MAX_DCI_CORESET];
int rnti_types[MAX_DCI_CORESET];
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
} dci_mac_pdus_t;
/*! \brief top level eNB MAC structure */
typedef struct gNB_MAC_INST_s {
/// Ethernet parameters for northbound midhaul interface
......@@ -401,6 +409,8 @@ typedef struct gNB_MAC_INST_s {
time_stats_t schedule_pch;
/// CCE lists
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
/// DCI information
dci_mac_pdus_t dci_pdus;
} gNB_MAC_INST;
#endif /*__LAYER2_NR_MAC_GNB_H__ */
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