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Commit e84adbb4 authored by francescomani's avatar francescomani
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msg3 retransmission at UE

parent 041ccea4
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Showing with 103 additions and 55 deletions
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ e84adbb4
...@@ -963,7 +963,8 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -963,7 +963,8 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
currentPtrDCI); currentPtrDCI);
n_rnti = rel15->rnti; n_rnti = rel15->rnti;
LOG_D(PHY, "(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d)\n", proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length); LOG_D(PHY, "(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d)\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length);
if (crc == n_rnti) { if (crc == n_rnti) {
LOG_D(PHY, "(%i.%i) Received dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx)\n", LOG_D(PHY, "(%i.%i) Received dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length,*(unsigned long long*)dci_estimation); proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length,*(unsigned long long*)dci_estimation);
...@@ -990,6 +991,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -990,6 +991,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
} }
} }
} }
pdcch_vars->nb_search_space = 0;
return(dci_ind->number_of_dcis); return(dci_ind->number_of_dcis);
} }
......
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @ e84adbb4
...@@ -69,7 +69,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ...@@ -69,7 +69,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
for (i = 0; i < dl_config->number_pdus; ++i){ for (i = 0; i < dl_config->number_pdus; ++i){
AssertFatal(dl_config->number_pdus < FAPI_NR_DL_CONFIG_LIST_NUM,"dl_config->number_pdus %d out of bounds\n",dl_config->number_pdus); AssertFatal(dl_config->number_pdus < FAPI_NR_DL_CONFIG_LIST_NUM,"dl_config->number_pdus %d out of bounds\n",dl_config->number_pdus);
AssertFatal(dl_config->dl_config_list[i].pdu_type<=FAPI_NR_DL_CONFIG_TYPES,"pdu_type %d > 2\n",dl_config->dl_config_list[i].pdu_type); AssertFatal(dl_config->dl_config_list[i].pdu_type<=FAPI_NR_DL_CONFIG_TYPES,"pdu_type %d > 2\n",dl_config->dl_config_list[i].pdu_type);
LOG_D(PHY, "In %s: received 1 DL %s PDU of %d total DL PDUs:\n", __FUNCTION__, dl_pdu_type[dl_config->dl_config_list[i].pdu_type - 1], dl_config->number_pdus); LOG_D(PHY, "In %s: frame %d slot %d received 1 DL %s PDU of %d total DL PDUs:\n",
__FUNCTION__, scheduled_response->frame, slot, dl_pdu_type[dl_config->dl_config_list[i].pdu_type - 1], dl_config->number_pdus);
if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) { if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) {
...@@ -145,7 +146,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ...@@ -145,7 +146,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
dlsch0_harq->nEpreRatioOfPDSCHToPTRS = dlsch_config_pdu->nEpreRatioOfPDSCHToPTRS; dlsch0_harq->nEpreRatioOfPDSCHToPTRS = dlsch_config_pdu->nEpreRatioOfPDSCHToPTRS;
dlsch0_harq->PTRSReOffset = dlsch_config_pdu->PTRSReOffset; dlsch0_harq->PTRSReOffset = dlsch_config_pdu->PTRSReOffset;
dlsch0_harq->pduBitmap = dlsch_config_pdu->pduBitmap; dlsch0_harq->pduBitmap = dlsch_config_pdu->pduBitmap;
LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\tpdsch_to_harq_feedback_time_ind = %d\tslot_for_feedback_ack = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs, dlsch_config_pdu->pdsch_to_harq_feedback_time_ind, dlsch0_harq->harq_ack.slot_for_feedback_ack); LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\tpdsch_to_harq_feedback_time_ind = %d\tslot_for_feedback_ack = %d\n",
dlsch0->g_pucch, dlsch0_harq->mcs, dlsch_config_pdu->pdsch_to_harq_feedback_time_ind, dlsch0_harq->harq_ack.slot_for_feedback_ack);
} }
} }
} }
......
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @ e84adbb4
...@@ -183,7 +183,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t ...@@ -183,7 +183,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->BWPStart = NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); rel15->BWPStart = NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
rel15->dci_length_options[0] = nr_dci_size(initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[0]], rel15->dci_format_options[0], NR_RNTI_TC, rel15->BWPSize, bwp_id); for (int i = 0; i < rel15->num_dci_options; i++)
rel15->dci_length_options[i] = nr_dci_size(initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_TC, rel15->BWPSize, bwp_id);
break; break;
case NR_RNTI_SP_CSI: case NR_RNTI_SP_CSI:
break; break;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ e84adbb4
...@@ -1465,6 +1465,11 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -1465,6 +1465,11 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
pos++; pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
//switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0)
return 2+nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, dci_pdu, dci_pdu_rel15);
if (dci_pdu_rel15->format_indicator == 0) if (dci_pdu_rel15->format_indicator == 0)
return 1; // discard dci, format indicator not corresponding to dci_format return 1; // discard dci, format indicator not corresponding to dci_format
...@@ -1603,40 +1608,62 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, ...@@ -1603,40 +1608,62 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
break; break;
case NR_RNTI_TC: case NR_RNTI_TC:
/* //Identifier for DCI formats
// indicating a DL DCI format 1bit pos++;
dci_pdu->= (*dci_pdu>>(dci_size-pos)format_indicator&1)<<(dci_size-pos++); dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
// Freq domain assignment max 16 bit #ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
#endif
if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format
fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
for (int i=0; i<fsize; i++) pos+=fsize;
dci_pdu->= ((*dci_pdu>>(dci_size-pos)frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
#endif
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) pos+=4;
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
#endif
// Frequency hopping flag  E1 bit // Frequency hopping flag  E1 bit
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)frequency_hopping_flag&1)<<(dci_size-pos++); pos++;
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu);
#endif
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) pos+=5;
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)mcs>>(4-i))&1)<<(dci_size-pos++); dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
#endif
// New data indicator 1bit // New data indicator 1bit
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ndi&1)<<(dci_size-pos++); pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) pos+=2;
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)rv>>(1-i))&1)<<(dci_size-pos++); dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
#endif
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) pos+=4;
*dci_pdu |= (((uint64_t)*dci_pdu>>(dci_size-pos)harq_pid>>(3-i))&1)<<(dci_size-pos++); dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits // TPC command for scheduled PUSCH  E2 bits
for (int i=0; i<2; i++) pos+=2;
dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)tpc>>(1-i))&1)<<(dci_size-pos++); dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
*/ #ifdef DEBUG_EXTRACT_DCI
// UL/SUL indicator  E1 bit LOG_I(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
/* #endif
commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
*/
break; break;
} }
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ e84adbb4
...@@ -941,12 +941,15 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in ...@@ -941,12 +941,15 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
} }
// this is for Msg2/Msg4 // this is for Msg2/Msg4
if (mac->ra.ra_state >= WAIT_RAR) { if (mac->ra.ra_state >= WAIT_RAR) {
rel15->num_dci_options = 1; rel15->num_dci_options = mac->ra.ra_state == WAIT_RAR ? 1 : 2;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
if (mac->ra.ra_state == WAIT_CONTENTION_RESOLUTION)
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0; // msg3 retransmission
config_dci_pdu(mac, rel15, dl_config, mac->ra.ra_state == WAIT_RAR ? NR_RNTI_RA : NR_RNTI_TC , -1); config_dci_pdu(mac, rel15, dl_config, mac->ra.ra_state == WAIT_RAR ? NR_RNTI_RA : NR_RNTI_TC , -1);
fill_dci_search_candidates(ss0, rel15); fill_dci_search_candidates(ss0, rel15);
dl_config->number_pdus = 1; dl_config->number_pdus = 1;
LOG_D(NR_MAC,"mac->cg %p: Calling fill_scheduled_response rnti %x, type0_pdcch, num_pdus %d\n",mac->cg,rel15->rnti,dl_config->number_pdus); LOG_D(NR_MAC,"mac->cg %p: Calling fill_scheduled_response rnti %x, type0_pdcch, num_pdus %d frame %d slot %d\n",
mac->cg,rel15->rnti,dl_config->number_pdus,rx_frame,rx_slot);
fill_scheduled_response(&scheduled_response, dl_config, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id); fill_scheduled_response(&scheduled_response, dl_config, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id);
if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL) if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL)
mac->if_module->scheduled_response(&scheduled_response); mac->if_module->scheduled_response(&scheduled_response);
...@@ -1014,7 +1017,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in ...@@ -1014,7 +1017,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
if (ulcfg_pdu->pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) { if (ulcfg_pdu->pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
uint16_t TBS_bytes = ulcfg_pdu->pusch_config_pdu.pusch_data.tb_size; uint16_t TBS_bytes = ulcfg_pdu->pusch_config_pdu.pusch_data.tb_size;
LOG_D(NR_MAC,"harq_id %d, NDI %d NDI_DCI %d, TBS_bytes %d (ra_state %d\n", LOG_D(NR_MAC,"harq_id %d, NDI %d NDI_DCI %d, TBS_bytes %d (ra_state %d)\n",
ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id, ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id,
mac->UL_ndi[ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id], mac->UL_ndi[ulcfg_pdu->pusch_config_pdu.pusch_data.harq_process_id],
ulcfg_pdu->pusch_config_pdu.pusch_data.new_data_indicator, ulcfg_pdu->pusch_config_pdu.pusch_data.new_data_indicator,
...@@ -1119,7 +1122,6 @@ int nr_ue_pusch_scheduler(NR_UE_MAC_INST_t *mac, ...@@ -1119,7 +1122,6 @@ int nr_ue_pusch_scheduler(NR_UE_MAC_INST_t *mac,
int delta = 0; int delta = 0;
NR_BWP_Uplink_t *ubwp = mac->ULbwp[0]; NR_BWP_Uplink_t *ubwp = mac->ULbwp[0];
// Get the numerology to calculate the Tx frame and slot // Get the numerology to calculate the Tx frame and slot
int mu = ubwp ? int mu = ubwp ?
ubwp->bwp_Common->genericParameters.subcarrierSpacing : ubwp->bwp_Common->genericParameters.subcarrierSpacing :
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @ e84adbb4
...@@ -859,6 +859,8 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t ...@@ -859,6 +859,8 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
// reset state to wait msg3 // reset state to wait msg3
ra->state = WAIT_Msg3; ra->state = WAIT_Msg3;
ra->Msg3_frame = sched_frame;
ra->Msg3_slot = sched_slot;
} }
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ e84adbb4
...@@ -1387,41 +1387,53 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc, ...@@ -1387,41 +1387,53 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
break; break;
case NFAPI_NR_RNTI_TC: case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a UL DCI format 1bit
*dci_pdu |= (dci_pdu_rel15->format_indicator & 1) << (dci_size - pos++); pos=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator & 1) << (dci_size - pos);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)); fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
for (int i = 0; i < fsize; i++) pos+=fsize;
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val >> (fsize - i - 1)) & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val & ((1 << fsize) - 1)) << (dci_size - pos);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i = 0; i < 4; i++) pos += 4;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val >> (3 - i)) & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val & ((1 << 4) - 1)) << (dci_size - pos);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val & 1) << (dci_size - pos++); pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val & 1) << (dci_size - pos);
// MCS 5 bit // MCS 5 bit
for (int i = 0; i < 5; i++) pos+=5;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs >> (4 - i)) & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs & 0x1f) << (dci_size - pos);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi & 1) << (dci_size - pos++); pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi & 1) << (dci_size - pos);
// Redundancy version 2bit // Redundancy version 2bit
for (int i = 0; i < 2; i++) pos+=2;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv >> (1 - i)) & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv & 0x3) << (dci_size - pos);
// HARQ process number 4bit // HARQ process number 4bit
for (int i = 0; i < 4; i++) pos+=4;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid >> (3 - i)) & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid & 0xf) << (dci_size - pos);
// TPC command for scheduled PUSCH – 2 bits
for (int i = 0; i < 2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc >> (1 - i)) & 1) << (dci_size - pos++);
// Padding bits // Padding bits
for (int a = pos; a < 32; a++) for (int a = pos; a < 32; a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding & 1) << (dci_size - pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding & 1) << (dci_size - pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* /* commented for now (RK): need to get this from BWP descriptor
commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= *dci_pdu |=
((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++); ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/ */
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_hopping_flag.val = %i\n", dci_pdu_rel15->frequency_hopping_flag.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->ndi = %i\n", dci_pdu_rel15->ndi);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->padding = %i\n", dci_pdu_rel15->padding);
break; break;
} }
break; break;
......
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