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OpenXG-RAN
Commit 2c196830 authored by Raymond Knopp's avatar Raymond Knopp
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adding -E.c files. patch file for E and new directories in 

oran_fhi_integration_patches for bronze and E XRAN targets
parent c9ec2ac8
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Showing with 981 additions and 34 deletions
radio/ETHERNET/oran/5g/app_io_fh_xran-E.c
View file @ 2c196830
......@@ -1988,6 +1988,7 @@ app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg,
p_xran_fh_cfg->nDLRBs = app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA);
p_xran_fh_cfg->nULRBs = app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA);
printf("FH init: nDLRBs %d, nULRBs %d\n", p_xran_fh_cfg->nDLRBs, p_xran_fh_cfg->nULRBs);
if(p_o_xu_cfg->DynamicSectionEna == 0){
pRbMap = p_o_xu_cfg->p_PrbMapDl;
......@@ -2092,7 +2093,12 @@ app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg,
p_o_xu_cfg->prachiqWidth = 16;
p_xran_fh_cfg->ru_conf.iqWidth_PRACH = p_o_xu_cfg->prachiqWidth;
printf("CompHdrType %s. iqWidth %d, compMeth %s, compMeth_PRACH %s, iqWidth_PRACH %d\n",
p_xran_fh_cfg->ru_conf.xranCompHdrType==1?"Static":"Dynamic",
p_xran_fh_cfg->ru_conf.iqWidth,
p_xran_fh_cfg->ru_conf.compMeth==XRAN_COMPMETHOD_NONE?"NONE":"BFP",
p_xran_fh_cfg->ru_conf.compMeth_PRACH==XRAN_COMPMETHOD_NONE?"PRACH NONE":"PRACH BFP",
p_xran_fh_cfg->ru_conf.iqWidth_PRACH);
p_xran_fh_cfg->ru_conf.fftSize = 0;
while (p_o_xu_cfg->nULFftSize >>= 1)
++p_xran_fh_cfg->ru_conf.fftSize;
......
radio/ETHERNET/oran/5g/app_io_fh_xran-E.h 0 → 100644
View file @ 2c196830
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
/**
* @brief Header file to interface implementation to ORAN FH from Application side
* @file app_iof_fh_xran.h
* @ingroup xran
* @author Intel Corporation
*
**/
#ifndef _APP_IO_FH_H_
#define _APP_IO_FH_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdio.h>
#include <unistd.h>
#include "config.h"
#include "xran_fh_o_du.h"
#include "xran_pkt_up.h"
#define MAX_PKT_BURST (448+4) /* 4x14x8 */
#define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST
#define NUM_OF_SUBFRAME_PER_FRAME (10)
#define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024
#define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024
#define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024
#define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)
extern void* app_io_xran_handle;
extern struct xran_fh_init app_io_xran_fh_init;
extern struct xran_fh_config app_io_xran_fh_config[XRAN_PORTS_NUM];
typedef struct
{
uint32_t phaseFlag :1;
uint32_t NRARFCN :22;
uint32_t SULFreShift :1;
uint32_t SULFlag :1;
uint32_t rsv :7;
} FPGAPhaseCompCfg;
typedef enum {
XRANFTHTX_OUT = 0,
XRANFTHTX_PRB_MAP_OUT,
XRANFTHTX_SEC_DESC_OUT,
XRANFTHRX_IN,
XRANFTHRX_PRB_MAP_IN,
XRANFTHTX_SEC_DESC_IN,
XRANFTHRACH_IN,
XRANSRS_IN,
XRANSRS_PRB_MAP_IN,
XRANSRS_SEC_DESC_IN,
MAX_SW_XRAN_INTERFACE_NUM
} SWXRANInterfaceTypeEnum;
struct xran_io_buf_ctrl {
/* -1-this subframe is not used in current frame format
0-this subframe can be transmitted, i.e., data is ready
1-this subframe is waiting transmission, i.e., data is not ready
10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1,
set bValid to 10.
*/
int32_t bValid ; // when UL rx, it is subframe index.
int32_t nSegToBeGen;
int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE
// -1 means that DL packet to be transmitted is not ready in BS
int32_t nSegTransferred; // number of data segments has been transmitted or received
struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool
struct xran_buffer_list sBufferList;
};
struct xran_io_shared_ctrl {
/* io struct */
struct xran_io_buf_ctrl sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrlDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
/* Cat B */
struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
/* buffers lists */
struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
/* Cat B SRS buffers */
struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
};
struct bbu_xran_io_if {
void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /**< instance per ORAN port per CC */
uint32_t nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; /**< unique buffer pool */
uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC */
uint16_t DynamicSectionEna;
uint32_t nPhaseCompFlag;
int32_t num_o_ru;
int32_t num_cc_per_port[XRAN_PORTS_NUM];
int32_t map_cell_id2port[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU port */
struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
};
struct bbu_xran_io_if* app_io_xran_if_alloc(void);
struct bbu_xran_io_if* app_io_xran_if_get(void);
void app_io_xran_if_free(void);
struct xran_io_shared_ctrl * app_io_xran_if_ctrl_get(uint32_t o_xu_id);
int32_t app_io_xran_sfidx_get(uint8_t nNrOfSlotInSf);
int32_t app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg);
int32_t app_io_xran_iq_content_init(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
int32_t app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
int32_t app_io_xran_eAxCid_conf_set(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg);
int32_t app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init, struct xran_fh_config* p_xran_fh_cfg);
int32_t app_io_xran_fh_init_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init);
int32_t app_io_xran_buffers_max_sz_set (RuntimeConfig* p_o_xu_cfg);
int32_t app_io_xran_dl_tti_call_back(void * param);
int32_t app_io_xran_ul_half_slot_call_back(void * param);
int32_t app_io_xran_ul_full_slot_call_back(void * param);
int32_t app_io_xran_ul_custom_sym_call_back(void * param, struct xran_sense_of_time* time);
void app_io_xran_if_stop(void);
#ifdef __cplusplus
}
#endif
#endif /* _APP_IO_FH_H_ */
radio/ETHERNET/oran/5g/common-E.h 0 → 100644
View file @ 2c196830
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
#ifndef _XRAN_APP_COMMON_H_
#define _XRAN_APP_COMMON_H_
#include <stdio.h>
#include <unistd.h>
#include "xran_fh_o_du.h"
#include "xran_pkt_up.h"
#include <rte_common.h>
#include <rte_mbuf.h>
#define VERSIONX "oran_e_maintenance_release_v1.0"
#define APP_O_DU 0
#define APP_O_RU 1
enum app_state
{
APP_RUNNING,
APP_STOPPED
};
enum nRChBwOptions
{
PHY_BW_5_0_MHZ = 5, PHY_BW_10_0_MHZ = 10, PHY_BW_15_0_MHZ = 15, PHY_BW_20_0_MHZ = 20, PHY_BW_25_0_MHZ = 25,
PHY_BW_30_0_MHZ = 30, PHY_BW_40_0_MHZ = 40, PHY_BW_50_0_MHZ = 50, PHY_BW_60_0_MHZ = 60, PHY_BW_70_0_MHZ = 70,
PHY_BW_80_0_MHZ = 80, PHY_BW_90_0_MHZ = 90, PHY_BW_100_0_MHZ = 100, PHY_BW_200_0_MHZ = 200, PHY_BW_400_0_MHZ = 400
};
#define N_SC_PER_PRB 12
#define N_SYM_PER_SLOT 14
#define MAX_ANT_CARRIER_SUPPORTED (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR)
#define MAX_ANT_CARRIER_SUPPORTED_CAT_B (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR)
#define SUBFRAME_DURATION_US 1000
#define SUBFRAMES_PER_SYSTEMFRAME 10
#define IQ_PLAYBACK_BUFFER_BYTES (XRAN_NUM_OF_SLOT_IN_TDD_LOOP*N_SYM_PER_SLOT*XRAN_MAX_PRBS*N_SC_PER_PRB*4L)
/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 840 samples for long sequence or 144 for short sequence. The payload length is 840*16*2/8 octets.*/
#ifdef FCN_1_2_6_EARLIER
#define PRACH_PLAYBACK_BUFFER_BYTES (144*4L)
#else
#define PRACH_PLAYBACK_BUFFER_BYTES (840*4L)
#endif
#ifdef _DEBUG
#define iAssert(p) if(!(p)){fprintf(stderr,\
"Assertion failed: %s, file %s, line %d, val %d\n",\
#p, __FILE__, __LINE__, p);exit(-1);}
#else /* _DEBUG */
#define iAssert(p)
#endif /* _DEBUG */
/**< all the buffers allocated for O-XU */
struct o_xu_buffers {
int iq_playback_buffer_size_dl;
int iq_playback_buffer_size_ul;
int iq_bfw_buffer_size_dl;
int iq_bfw_buffer_size_ul;
int iq_srs_buffer_size_ul;
int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_tx_srs_play_buffer[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int32_t tx_srs_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int32_t tx_srs_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_srs_log_buffer[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int32_t srs_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int32_t srs_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-RU) */
int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-RU) */
int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
};
extern struct o_xu_buffers* p_o_xu_buff[XRAN_PORTS_NUM];
void sys_save_buf_to_file_txt(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
uint32_t app_xran_get_scs(uint8_t nMu);
uint16_t app_xran_get_num_rbs(uint8_t ranTech, uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA);
uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq);
int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType,
uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig);
uint32_t app_xran_get_tti_interval(uint8_t nMu);
#endif /*_XRAN_APP_COMMON_H_*/
radio/ETHERNET/oran/5g/config-E.h 0 → 100644
View file @ 2c196830
This diff is collapsed.
radio/ETHERNET/oran/5g/debug-E.h 0 → 100644
View file @ 2c196830
/******************************************************************************
*
* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*******************************************************************************/
/**
* @brief
* @file
* @ingroup
* @author Intel Corporation
**/
#ifndef _SAMPLEAPP__DEBUG_H_
#define _SAMPLEAPP__DEBUG_H_
#include <stdio.h>
#include "config.h"
#define MAX_FILE_NAME_LEN (512)
#define MAX_PATH_NAME_LEN (1024)
#ifdef _DEBUG
#define log_dbg(fmt, ...) \
fprintf(stderr, \
"DEBUG: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
#else
#define log_dbg(fmt, ...)
#endif
#if defined(_DEBUG) || defined(_VERBOSE)
#define log_wrn(fmt, ...) \
fprintf( \
stderr, \
"WARNING: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
#else
#define log_dbg(fmt, ...)
#define log_wrn(fmt, ...)
#endif
#define log_err(fmt, ...) \
fprintf(stderr, \
"ERROR: %s(%d): " fmt "\n", \
__FILE__, \
__LINE__, ##__VA_ARGS__)
inline void ShowData(void* ptr, unsigned int size)
{
uint8_t *d = (uint8_t *)ptr;
unsigned int i;
for(i = 0; i < size; i++)
{
if ( !(i & 0xf) )
printf("\n");
printf("%02x ", d[i]);
}
printf("\n");
}
#endif /* _SAMPLEAPP__DEBUG_H_ */
radio/ETHERNET/oran/5g/oaioran.c
View file @ 2c196830
......@@ -33,7 +33,7 @@
#include "xran_common.h"
#include "common/utils/threadPool/thread-pool.h"
#include "oaioran.h"
#include <rte_ethdev.h>
#define USE_POLLING 1
// Declare variable useful for the send buffer function
......@@ -55,7 +55,6 @@ volatile uint32_t rx_cb_slot = 0;
#define GetFrameNum(tti,SFNatSecStart,numSubFramePerSystemFrame, numSlotPerSubFrame) ((((uint32_t)tti / ((uint32_t)numSubFramePerSystemFrame * (uint32_t)numSlotPerSubFrame)) + SFNatSecStart) & 0x3FF)
#define GetSlotNum(tti, numSlotPerSfn) ((uint32_t)tti % ((uint32_t)numSlotPerSfn))
//#define ORAN_BRONZE 1
#ifdef ORAN_BRONZE
extern struct xran_fh_config xranConf;
extern void * xranHandle;
......@@ -172,38 +171,37 @@ int read_prach_data(ru_info_t *ru, int frame, int slot)
struct xran_device_ctx *xran_ctx = xran_dev_get_ctx();
struct xran_prach_cp_config *pPrachCPConfig = &(xran_ctx->PrachCPConfig);
struct xran_ru_config *ru_conf=&(xran_ctx->fh_cfg.ru_conf);
/* If it is PRACH slot, copy prach IQ from XRAN PRACH buffer to OAI PRACH buffer */
if(is_prach_slot) {
for(sym_idx = 0; sym_idx < pPrachCPConfig->numSymbol; sym_idx++) {
for (int aa=0;aa<ru->nb_rx;aa++) {
/* mb = (struct rte_mbuf *) xran_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][0][aa].sBufferList.pBuffers[sym_idx].pCtrl;
if(mb) { */
uint16_t *dst, *src;
int16_t *dst, *src;
int idx = 0;
dst = (uint16_t * )((uint8_t *)ru->prach_buf[aa]);// + (sym_idx*576));
src = (uint16_t *) ((uint8_t *) xran_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][0][aa].sBufferList.pBuffers[sym_idx].pData);
dst = (int16_t *)((uint8_t *)ru->prach_buf[aa]);// + (sym_idx*576));
src = (int16_t *)((uint8_t *) xran_ctx->sFHPrachRxBbuIoBufCtrlDecomp[tti % XRAN_N_FE_BUF_LEN][0][aa].sBufferList.pBuffers[sym_idx].pData);
/* convert Network order to host order */
if (ru_conf->compMeth == XRAN_COMPMETHOD_NONE) {
if (ru_conf->compMeth_PRACH == XRAN_COMPMETHOD_NONE) {
if (sym_idx==0) {
for (idx = 0; idx < 576/2; idx++)
{
((int16_t*)dst)[idx] = ((int16_t)ntohs(src[idx]))>>2;
dst[idx] = ((int16_t)ntohs(src[idx]))>>2;
}
}
else {
for (idx = 0; idx < 576/2; idx++)
{
((int16_t*)dst)[idx] += ((int16_t)ntohs(src[idx]))>>2;
dst[idx] += ((int16_t)ntohs(src[idx]))>>2;
}
}
} else if (ru_conf->compMeth == XRAN_COMPMETHOD_BLKFLOAT) {
} else if (ru_conf->compMeth_PRACH == XRAN_COMPMETHOD_BLKFLOAT) {
struct xranlib_decompress_request bfp_decom_req;
struct xranlib_decompress_response bfp_decom_rsp;
int32_t local_dst[12*N_SC_PER_PRB] __attribute__((aligned(64)));
int16_t local_dst[12*2*N_SC_PER_PRB] __attribute__((aligned(64)));
int payload_len = (3* ru_conf->iqWidth + 1)*12; // 12 = closest number of PRBs to 139 REs
int payload_len = (3* ru_conf->iqWidth_PRACH + 1)*12; // 12 = closest number of PRBs to 139 REs
memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
......@@ -212,27 +210,19 @@ int read_prach_data(ru_info_t *ru, int frame, int slot)
bfp_decom_req.numRBs = 12; // closest number of PRBs to 139 REs
bfp_decom_req.len = payload_len;
bfp_decom_req.compMethod = XRAN_COMPMETHOD_BLKFLOAT;
bfp_decom_req.iqWidth = ru_conf->iqWidth;
bfp_decom_req.iqWidth = ru_conf->iqWidth_PRACH;
bfp_decom_rsp.data_out = (int16_t*)local_dst;
bfp_decom_rsp.len = 0;
xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp);
if (sym_idx == 0) memcpy((void*)dst,(void*)local_dst,576); // 576 is short PRACH 139 -> 144*4
if (sym_idx == 0) //memcpy((void*)dst,(void*)local_dst,576); // 576 is short PRACH 139 -> 144*4
for (idx = 0; idx < (576/2); idx++) dst[idx]=local_dst[idx]>>2;
else
for (idx = 0; idx < 576/2; idx++)
((int16_t*)dst)[idx] += ((int16_t)local_dst[idx]);
}
/* } else {
// TODO: Unlikely this code never gets executed
printf("%s():%d, %d.%d There is no prach ctrl data for symb %d ant %d\n", __func__, __LINE__, frame, slot, sym_idx,aa);
}*/
}
}
}
for (idx = 0; idx < (576/2); idx++) dst[idx]+=(local_dst[idx]>>2);
} // COMPMETHOD_BLKFLOAT
} //aa
}// symb_indx
} // is_prach_slot
return(0);
}
......@@ -404,7 +394,7 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
memcpy((void*)dst2,(void*)local_dst,neg_len*4);
memcpy((void*)dst1,(void*)&local_dst[neg_len],pos_len*4);
outcnt++;
if (0/*outcnt==1000*/) {
if (0 /*outcnt==1000*/) {
LOG_I(NR_PHY,"bfp_decom_rsp.len %d, payload_len %d\n",bfp_decom_rsp.len,payload_len);
for (int prb=0;prb<p_prbMapElm->nRBSize;prb++){
LOG_I(NR_PHY,"PRB%d exponent %u\n",prb,((uint8_t*)src)[25*prb]);
......@@ -435,7 +425,7 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
#endif
{
for (int o_xu_id = 0; o_xu_id < 1 /*p_usecaseConfiguration->oXuNum*/; o_xu_id++) {
LOG_I(PHY,"[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld][Total Msgs_Rcvd %ld]\n",
LOG_I(NR_PHY,"[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld][Total Msgs_Rcvd %ld]\n",
"o-du ",
o_xu_id,
x_counters[o_xu_id].rx_counter,
......@@ -446,7 +436,7 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot){
x_counters[o_xu_id].tx_bytes_per_sec*8/1000L,
x_counters[o_xu_id].Total_msgs_rcvd);
for (int rxant=0;rxant<xran_max_antenna_nr && rxant<ru->nb_rx;rxant++)
LOG_I(PHY,"[%s%d][pusch%d %7ld prach%d %7ld]\n","o_du",o_xu_id,rxant,x_counters[o_xu_id].rx_pusch_packets[rxant],rxant,x_counters[o_xu_id].rx_prach_packets[rxant]);
LOG_I(NR_PHY,"[%s%d][pusch%d %7ld prach%d %7ld]\n","o_du",o_xu_id,rxant,x_counters[o_xu_id].rx_pusch_packets[rxant],rxant,x_counters[o_xu_id].rx_prach_packets[rxant]);
if (x_counters[o_xu_id].rx_counter > old_rx_counter[o_xu_id])
old_rx_counter[o_xu_id] = x_counters[o_xu_id].rx_counter;
if (x_counters[o_xu_id].tx_counter > old_tx_counter[o_xu_id])
......
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