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lizhongxiao
OpenXG-RAN
Commits
3ef7f3d0
Commit
3ef7f3d0
authored
Oct 16, 2020
by
masayuki.harada
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Revert "Change BLER interval and TPC target range in fairRR scheduler."
This reverts commit
b16f9dae
.
parent
b16f9dae
Changes
1
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3 additions
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14 deletions
+3
-14
openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
+3
-14
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openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
View file @
3ef7f3d0
...
...
@@ -4331,18 +4331,7 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
int32_t
framex10psubframe
=
UE_template
->
pusch_bler_calc_frame
*
10
+
UE_template
->
pusch_bler_calc_subframe
;
int
pusch_bler_interval
=
50
;
double
total_bler
;
if
(
cc
->
tdd_Config
)
{
switch
(
cc
->
tdd_Config
->
subframeAssignment
)
{
case
1
:
pusch_bler_interval
=
(
5
*
pusch_bler_interval
)
>>
1
;
break
;
case
2
:
pusch_bler_interval
=
5
*
pusch_bler_interval
;
break
;
}
}
if
(
UE_info
->
UE_sched_ctrl
[
UE_id
].
pusch_rx_num
[
CC_id
]
==
0
&&
UE_info
->
UE_sched_ctrl
[
UE_id
].
pusch_rx_error_num
[
CC_id
]
==
0
)
{
total_bler
=
0
;
}
...
...
@@ -4857,10 +4846,10 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
UE_template
->
pusch_tpc_tx_frame
=
frameP
;
UE_template
->
pusch_tpc_tx_subframe
=
subframeP
;
if
(
snr
>
target_snr
+
2
)
{
if
(
snr
>
target_snr
+
4
)
{
tpc
=
0
;
//-1
tpc_accumulated
--
;
}
else
if
(
snr
<
target_snr
-
2
)
{
}
else
if
(
snr
<
target_snr
-
4
)
{
tpc
=
2
;
//+1
tpc_accumulated
++
;
}
else
{
...
...
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