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lizhongxiao
OpenXG-RAN
Commits
4661138d
Commit
4661138d
authored
Feb 07, 2017
by
Raymond Knopp
Browse files
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Plain Diff
protection in case of false DCI
parent
bb5ee76a
Changes
4
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Showing
4 changed files
with
159 additions
and
42 deletions
+159
-42
openair1/PHY/LTE_TRANSPORT/dci_tools.c
openair1/PHY/LTE_TRANSPORT/dci_tools.c
+4
-2
openair1/SCHED/phy_mac_stub.c
openair1/SCHED/phy_mac_stub.c
+147
-29
openair1/SCHED/phy_procedures_lte_ue.c
openair1/SCHED/phy_procedures_lte_ue.c
+4
-8
targets/SIMU/USER/oaisim_functions.c
targets/SIMU/USER/oaisim_functions.c
+4
-3
No files found.
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @
4661138d
...
...
@@ -3831,6 +3831,8 @@ int generate_ue_dlsch_params_from_dci(int frame,
LTE_UE_DLSCH_t
*
dlsch0
=
NULL
,
*
dlsch1
=
NULL
;
LTE_DL_UE_HARQ_t
*
dlsch0_harq
,
*
dlsch1_harq
;
if
(
!
dlsch
[
0
])
return
-
1
;
#ifdef DEBUG_DCI
LOG_D
(
PHY
,
"dci_tools.c: Filling ue dlsch params -> rnti %x, SFN/SF %d/%d, dci_format %s
\n
"
,
rnti
,
...
...
@@ -7395,8 +7397,8 @@ int generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB,
rb_alloc
=
rballoc
;
if
(
rb_alloc
>
RIV_max
)
{
LOG_E
(
PHY
,
"Format 0: rb_alloc
> RIV_max
\n
"
);
mac_xface
->
macphy_exit
(
"Format 0:
rb_alloc > RIV_max
\n
"
);
LOG_E
(
PHY
,
"Format 0: rb_alloc
(%d) > RIV_max (%d)
\n
"
,
rb_alloc
,
RIV_max
);
mac_xface
->
macphy_exit
(
"Format 0:
error
"
);
return
(
-
1
);
}
...
...
openair1/SCHED/phy_mac_stub.c
View file @
4661138d
...
...
@@ -455,6 +455,151 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
break
;
}
DCI_pdu
->
dci_alloc
[
1
].
L
=
2
;
DCI_pdu
->
dci_alloc
[
1
].
rnti
=
0x1235
;
DCI_pdu
->
dci_alloc
[
1
].
format
=
format0
;
DCI_pdu
->
dci_alloc
[
1
].
ra_flag
=
0
;
if
(
eNB
->
frame_parms
.
frame_type
==
FDD
)
{
switch
(
eNB
->
frame_parms
.
N_RB_DL
)
{
case
6
:
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
6
,
1
,
4
);
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_1_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
/* case 15:
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case
25
:
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
25
,
1
,
20
);
printf
(
"rballoc %d
\n
"
,((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
);
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_5MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
case
50
:
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
50
,
1
,
48
);
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_10MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
/* case 75:
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case
100
:
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
100
,
1
,
96
);
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_20MHz_FDD_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
}
}
else
{
switch
(
eNB
->
frame_parms
.
N_RB_DL
==
6
)
{
case
6
:
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
6
,
1
,
5
);
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
dai
=
0
;
((
DCI0_1_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
/* case 15:
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case
25
:
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
25
,
2
,
20
);
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
dai
=
0
;
((
DCI0_5MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
case
50
:
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
50
,
1
,
48
);
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
dai
=
0
;
((
DCI0_10MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
/* case 75:
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case
100
:
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
type
=
0
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
hopping
=
0
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
rballoc
=
computeRIV
(
100
,
1
,
96
);
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
mcs
=
eNB
->
target_ue_ul_mcs
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
ndi
=
proc
->
frame_tx
&
1
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
TPC
=
0
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cshift
=
0
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
dai
=
0
;
((
DCI0_20MHz_TDD_1_6_t
*
)
&
DCI_pdu
->
dci_alloc
[
1
].
dci_pdu
[
0
])
->
cqi_req
=
1
;
break
;
}
}
}
else
if
(
transmission_mode
==
4
)
{
DCI_pdu
->
Num_ue_spec_dci
=
1
;
// user 1
...
...
@@ -543,32 +688,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],&RA_alloc_pdu,sizeof(DCI1A_5MHz_TDD_1_6_t));
break;
*/
/*
case 9:
DCI_pdu->Num_ue_spec_dci = 1;
//user 1
if (eNB->frame_parms.frame_type == FDD)
DCI_pdu->dci_alloc[0].dci_length = sizeof_DCI0_5MHz_FDD_t ;
else
DCI_pdu->dci_alloc[0].dci_length = sizeof_DCI0_5MHz_TDD_1_6_t ;
DCI_pdu->dci_alloc[0].L = 2;
DCI_pdu->dci_alloc[0].rnti = 0x1235;
DCI_pdu->dci_alloc[0].format = format0;
DCI_pdu->dci_alloc[0].ra_flag = 0;
UL_alloc_pdu.type = 0;
UL_alloc_pdu.hopping = 0;
UL_alloc_pdu.rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
UL_alloc_pdu.mcs = eNB->target_ue_ul_mcs;
UL_alloc_pdu.ndi = proc->frame_tx&1;
UL_alloc_pdu.TPC = 0;
UL_alloc_pdu.cshift = 0;
UL_alloc_pdu.dai = 0;
UL_alloc_pdu.cqi_req = 1;
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t));
*/
// user 2
/*
DCI_pdu->dci_alloc[1].dci_length = sizeof_DCI0_5MHz_TDD_1_6_t ;
...
...
@@ -593,11 +714,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
UL_alloc_pdu.dai = 0;
UL_alloc_pdu.cqi_req = 1;
memcpy((void*)&DCI_pdu->dci_alloc[1].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t));
break;
*/
/*default:
break;*/
}
/*
...
...
openair1/SCHED/phy_procedures_lte_ue.c
View file @
4661138d
...
...
@@ -2971,17 +2971,14 @@ int ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint
#endif
}
}
else
if
(
(
dci_alloc_rx
[
i
].
rnti
==
ue
->
ulsch
[
eNB_id
]
->
cba_rnti
[
0
])
&&
}
/* else if( (dci_alloc_rx[i].rnti == ue->ulsch[eNB_id]->cba_rnti[0]) &&
(dci_alloc_rx[i].format == format0)) {
// UE could belong to more than one CBA group
// ue->Mod_id%ue->ulsch[eNB_id]->num_active_cba_groups]
#ifdef DEBUG_PHY_PROC
LOG_D(PHY,"[UE %d][PUSCH] Frame %d subframe %d: Found cba rnti %x, format 0, dci_cnt %d\n",
ue->Mod_id,frame_rx,subframe_rx,dci_alloc_rx[i].rnti,i);
/*
if (((frame_rx%100) == 0) || (frame_rx < 20))
dump_dci(&ue->frame_parms, &dci_alloc_rx[i]);
*/
#endif
ue->ulsch_no_allocation_counter[eNB_id] = 0;
...
...
@@ -3005,9 +3002,8 @@ int ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint
LOG_D(PHY,"[UE %d] Generate UE ULSCH CBA_RNTI format 0 (subframe %d)\n",ue->Mod_id,subframe_rx);
#endif
ue->ulsch[eNB_id]->num_cba_dci[(subframe_rx+4)%10]++;
}
}
}
*/
else
{
#ifdef DEBUG_PHY_PROC
LOG_D
(
PHY
,
"[UE %d] frame %d, subframe %d: received DCI %d with RNTI=%x (C-RNTI:%x, CBA_RNTI %x) and format %d!
\n
"
,
ue
->
Mod_id
,
frame_rx
,
subframe_rx
,
i
,
dci_alloc_rx
[
i
].
rnti
,
...
...
targets/SIMU/USER/oaisim_functions.c
View file @
4661138d
...
...
@@ -1400,9 +1400,10 @@ void init_openair1(void)
PHY_vars_UE_g
[
UE_id
][
CC_id
]
->
rx_total_gain_dB
=
100
;
// update UE_mode for each eNB_id not just 0
if
(
abstraction_flag
==
0
)
PHY_vars_UE_g
[
UE_id
][
CC_id
]
->
UE_mode
[
0
]
=
NOT_SYNCHED
;
else
{
if
(
abstraction_flag
==
0
)
{
if
(
phy_test
==
0
)
PHY_vars_UE_g
[
UE_id
][
CC_id
]
->
UE_mode
[
0
]
=
NOT_SYNCHED
;
else
PHY_vars_UE_g
[
UE_id
][
CC_id
]
->
UE_mode
[
0
]
=
PUSCH
;
}
else
{
// 0 is the index of the connected eNB
PHY_vars_UE_g
[
UE_id
][
CC_id
]
->
UE_mode
[
0
]
=
PRACH
;
}
...
...
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