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Commit 5737fafa authored by Niccolò Iardella's avatar Niccolò Iardella
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Add the first_rb_offset for each slice in UL scheduling

parent fc4d2fb2
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Showing with 205 additions and 131 deletions
openair2/COMMON/platform_types.h
View file @ 5737fafa
......@@ -115,7 +115,9 @@ typedef enum {
CRU_BUF = 1,
CRU_BTS = 2,
CRU_MCS = 3,
CRU_NUM = 4
CRU_LCP = 4,
CRU_HOL = 5,
CRU_NUM = 6
} sorting_criterion_ul_t;
typedef enum {
......@@ -123,6 +125,12 @@ typedef enum {
POL_GREEDY = 1,
POL_NUM = 2
} accounting_policy_t;
typedef enum {
CQI2MCS_TABLE = 0,
CQI2MCS_DUMMY = 1,
CQI2MCS_NUM = 2
} cqi2mcs_policy_t;
//-----------------------------------------------------------------------------
// PHY TYPES
//-----------------------------------------------------------------------------
......
openair2/LAYER2/MAC/defs.h
View file @ 5737fafa
......@@ -984,6 +984,8 @@ typedef struct {
uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM];
uint16_t sorting_criteria_ul[MAX_NUM_SLICES][CR_NUM];
uint16_t first_rb_offset[MAX_NUM_CCs][MAX_NUM_SLICES];
} UE_list_t;
/*! \brief eNB common channels */
......
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
View file @ 5737fafa
......@@ -593,7 +593,7 @@ schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, in
// Check for new accounting policy
if (slice_accounting_current[i] != slice_accounting[i]) {
if (slice_accounting[i] > 1 || slice_accounting[i] < 0) {
if (slice_accounting[i] > (POL_NUM - 1) || slice_accounting[i] < 0) {
LOG_W(MAC,
"[eNB %d][SLICE %d][DL] frame %d subframe %d: invalid accounting policy (%d), revert to its previous value (%d)\n",
module_idP, i, frameP, subframeP, slice_accounting[i], slice_accounting_current[i]);
......@@ -605,6 +605,20 @@ schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, in
}
}
// Check for new cqi2mcs conversion policy
if (slice_cqi2mcs_current[i] != slice_cqi2mcs[i]) {
if (slice_cqi2mcs[i] > (POL_NUM - 1) || slice_cqi2mcs[i] < 0) {
LOG_W(MAC,
"[eNB %d][SLICE %d][DL] frame %d subframe %d: invalid CQI/MCS conversion policy (%d), revert to its previous value (%d)\n",
module_idP, i, frameP, subframeP, slice_cqi2mcs[i], slice_cqi2mcs_current[i]);
slice_cqi2mcs[i] = slice_cqi2mcs_current[i];
} else {
LOG_N(MAC, "[eNB %d][SLICE %d][DL] frame %d subframe %d: CQI/MCS conversion policy has changed (%x-->%x)\n",
module_idP, i, frameP, subframeP, slice_cqi2mcs_current[i], slice_cqi2mcs[i]);
slice_cqi2mcs_current[i] = slice_cqi2mcs[i];
}
}
// Run each enabled slice-specific schedulers one by one
slice_sched_dl[i](module_idP, i, frameP, subframeP, mbsfn_flag/*, dl_info*/);
}
......
openair2/LAYER2/MAC/eNB_scheduler_dlsch.h
View file @ 5737fafa
......@@ -66,6 +66,8 @@ int slice_position_current[MAX_NUM_SLICES*2] = {0, N_RBG_MAX, 0, N_RBG_MAX
// MAX MCS for each slice for past and current time
int slice_maxmcs[MAX_NUM_SLICES] = { 28, 28, 28, 28 };
int slice_maxmcs_current[MAX_NUM_SLICES] = { 28, 28, 28, 28 };
int slice_cqi2mcs[MAX_NUM_SLICES] = {0, 0, 0, 0};
int slice_cqi2mcs_current[MAX_NUM_SLICES] = {0, 0, 0, 0};
// The lists of criteria that enforce the sorting policies of the slices
uint32_t slice_sorting[MAX_NUM_SLICES] = {0x012345, 0x012345, 0x012345, 0x012345};
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @ 5737fafa
......@@ -330,10 +330,10 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid] = BSR_TABLE[bsr];
UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer =
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[0] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[1] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[2] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[3];
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID0] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID1] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID2] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID3];
//UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer += UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer / 4;
RC.eNB[enb_mod_idP][CC_idP]->pusch_stats_bsr[UE_id][(frameP * 10) + subframeP] = (payload_ptr[0] & 0x3f);
......@@ -343,7 +343,10 @@ rx_sdu(const module_id_t enb_mod_idP,
[UE_id][(frameP * 10) + subframeP]);
if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[lcgid] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[lcgid] = frameP;
}
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max =
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[lcgid];
}
if (mac_eNB_get_rrc_status(enb_mod_idP,UE_RNTI(enb_mod_idP, UE_id)) < RRC_CONNECTED)
LOG_D(MAC,
"[eNB %d] CC_id %d MAC CE_LCID %d : estimated_ul_buffer = %d (lcg increment %d)\n",
......@@ -364,10 +367,10 @@ rx_sdu(const module_id_t enb_mod_idP,
int bsr2 = ((payload_ptr[1] & 0x0F) << 2) | ((payload_ptr[2] & 0xC0) >> 6);
int bsr3 = payload_ptr[2] & 0x3F;
lcgid_updated[0] = 1;
lcgid_updated[1] = 1;
lcgid_updated[2] = 1;
lcgid_updated[3] = 1;
lcgid_updated[LCGID0] = 1;
lcgid_updated[LCGID1] = 1;
lcgid_updated[LCGID2] = 1;
lcgid_updated[LCGID3] = 1;
// update buffer info
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID0] = BSR_TABLE[bsr0];
......@@ -376,10 +379,10 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID3] = BSR_TABLE[bsr3];
UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer =
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[0] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[1] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[2] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[3];
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID0] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID1] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID2] +
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID3];
//UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer += UE_list->UE_template[CC_idP][UE_id].estimated_ul_buffer / 4;
LOG_D(MAC,
......@@ -405,18 +408,27 @@ rx_sdu(const module_id_t enb_mod_idP,
} else if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID0] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID0] = frameP;
}
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max =
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID0];
if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID1] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID1] = 0;
} else if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID1] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID1] = frameP;
}
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max =
cmax(UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID1]);
if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID2] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID2] = 0;
} else if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID2] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID2] = frameP;
}
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max =
cmax(UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID2]);
if (UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[LCGID3] == 0) {
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID3] = 0;
......@@ -424,6 +436,9 @@ rx_sdu(const module_id_t enb_mod_idP,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID3] = frameP;
}
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max =
cmax(UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time_max,
UE_list->UE_template[CC_idP][UE_id].ul_buffer_creation_time[LCGID3]);
}
payload_ptr += 3; ////sizeof(LONG_BSR);
......@@ -1078,6 +1093,9 @@ schedule_ulsch_rnti(module_id_t module_idP,
int sched_frame = frameP;
int rvidx_tab[4] = { 0, 2, 3, 1 };
int first_rb_slice[MAX_NUM_CCs];
if (sched_subframeP < subframeP)
sched_frame++;
......@@ -1091,6 +1109,10 @@ schedule_ulsch_rnti(module_id_t module_idP,
//LOG_D(MAC, "entering ulsch preprocesor\n");
ulsch_scheduler_pre_processor(module_idP, slice_id, frameP, subframeP, first_rb);
for (n = 0; n < MAX_NUM_CCs; ++n) {
first_rb_slice[CC_id] = first_rb[CC_id] + UE_list->first_rb_offset[CC_id][slice_id];
}
//LOG_D(MAC, "exiting ulsch preprocesor\n");
hi_dci0_req->sfn_sf = (frameP << 4) + subframeP;
......@@ -1155,6 +1177,8 @@ schedule_ulsch_rnti(module_id_t module_idP,
}
continue;
}
// loop over all active UL CC_ids for this UE
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
// This is the actual CC_id in the list
......@@ -1176,7 +1200,8 @@ schedule_ulsch_rnti(module_id_t module_idP,
}
/* be sure that there are some free RBs */
if (first_rb[CC_id] >= N_RB_UL - 1) {
// if (first_rb[CC_id] >= N_RB_UL - 1) {
if (first_rb_slice[CC_id] >= N_RB_UL - 1) {
LOG_W(MAC,
"[eNB %d] frame %d subframe %d, UE %d/%x CC %d: dropping, not enough RBs\n",
module_idP, frameP, subframeP, UE_id, rnti, CC_id);
......@@ -1280,7 +1305,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
// buffer_occupancy = UE_template->ul_total_buffer;
while (((rb_table[rb_table_index] > (N_RB_UL - 1 - first_rb[CC_id]))
while (((rb_table[rb_table_index] > (N_RB_UL - 1 - first_rb_slice[CC_id]))
|| (rb_table[rb_table_index] > 45))
&& (rb_table_index > 0)) {
rb_table_index--;
......@@ -1297,7 +1322,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
T_INT(CC_id), T_INT(rnti), T_INT(frameP),
T_INT(subframeP), T_INT(harq_pid),
T_INT(UE_template->mcs_UL[harq_pid]),
T_INT(first_rb[CC_id]),
T_INT(first_rb_slice[CC_id]),
T_INT(rb_table[rb_table_index]),
T_INT(UE_template->TBS_UL[harq_pid]), T_INT(ndi));
......@@ -1307,14 +1332,14 @@ schedule_ulsch_rnti(module_id_t module_idP,
module_idP, harq_pid, rnti, CC_id, frameP,
subframeP, UE_id,
UE_template->mcs_UL[harq_pid],
first_rb[CC_id], rb_table[rb_table_index],
first_rb_slice[CC_id], rb_table[rb_table_index],
rb_table_index,
UE_template->TBS_UL[harq_pid], harq_pid);
// bad indices : 20 (40 PRB), 21 (45 PRB), 22 (48 PRB)
//store for possible retransmission
UE_template->nb_rb_ul[harq_pid] = rb_table[rb_table_index];
UE_template->first_rb_ul[harq_pid] = first_rb[CC_id];
UE_template->first_rb_ul[harq_pid] = first_rb_slice[CC_id];
UE_sched_ctrl->ul_scheduled |= (1 << harq_pid);
if (UE_id == UE_list->head)
......@@ -1346,7 +1371,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation;
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti;
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.transmission_power = 6000;
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = first_rb[CC_id];
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = first_rb_slice[CC_id];
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.number_of_resource_block = rb_table[rb_table_index];
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.mcs_1 = UE_template->mcs_UL[harq_pid];
hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cyclic_shift_2_for_drms = cshift;
......@@ -1414,13 +1439,13 @@ schedule_ulsch_rnti(module_id_t module_idP,
LOG_D(MAC,"[PUSCH %d] SFN/SF:%04d%d UL_CFG:SFN/SF:%04d%d CQI:%d for UE %d/%x\n", harq_pid,frameP,subframeP,ul_sched_frame,ul_sched_subframeP,cqi_req,UE_id,rnti);
// increment first rb for next UE allocation
first_rb[CC_id] += rb_table[rb_table_index];
first_rb_slice[CC_id] += rb_table[rb_table_index];
} else { // round > 0 => retransmission
T(T_ENB_MAC_UE_UL_SCHEDULE_RETRANSMISSION,
T_INT(module_idP), T_INT(CC_id), T_INT(rnti),
T_INT(frameP), T_INT(subframeP), T_INT(harq_pid),
T_INT(UE_template->mcs_UL[harq_pid]),
T_INT(first_rb[CC_id]),
T_INT(first_rb_slice[CC_id]),
T_INT(rb_table[rb_table_index]), T_INT(round));
// fill in NAK information
......
openair2/LAYER2/MAC/eNB_scheduler_ulsch.h
View file @ 5737fafa
......@@ -53,8 +53,8 @@ int slice_maxmcs_uplink[MAX_NUM_SLICES] = {20, 20, 20, 20};
int slice_maxmcs_current_uplink[MAX_NUM_SLICES] = {20,20,20,20};
// The lists of criteria that enforce the sorting policies of the slices
uint32_t slice_sorting_uplink[MAX_NUM_SLICES] = {0x0123, 0x0123, 0x0123, 0x0123};
uint32_t slice_sorting_uplink_current[MAX_NUM_SLICES] = {0x0123, 0x0123, 0x0123, 0x0123};
uint32_t slice_sorting_uplink[MAX_NUM_SLICES] = {0x012345, 0x012345, 0x012345, 0x012345};
uint32_t slice_sorting_uplink_current[MAX_NUM_SLICES] = {0x012345, 0x012345, 0x012345, 0x012345};
/*resource blocks allowed*/
uint16_t nb_rbs_allowed_slice_uplink[MAX_NUM_CCs][MAX_NUM_SLICES];
......
openair2/LAYER2/MAC/pre_processor.c
View file @ 5737fafa
......@@ -65,6 +65,7 @@ extern uint32_t slice_sorting_uplink[MAX_NUM_SLICES];
extern int slice_accounting[MAX_NUM_SLICES];
extern int slice_maxmcs[MAX_NUM_SLICES];
extern int slice_maxmcs_uplink[MAX_NUM_SLICES];
extern int slice_cqi2mcs[MAX_NUM_SLICES];
extern pre_processor_results_t pre_processor_results[MAX_NUM_SLICES];
extern int intraslice_share_active;
......@@ -177,8 +178,15 @@ store_dlsch_buffer(module_id_t Mod_id,
}
}
int cqi2mcs(int cqi) {
return cqi_to_mcs[cqi];
int cqi2mcs(int cqi, int slice_id) {
switch (slice_cqi2mcs[slice_id]) {
case CQI2MCS_TABLE :
return cqi_to_mcs[cqi];
case CQI2MCS_DUMMY :
return cqi_to_mcs[cqi]; // TODO: Add a different function here
default:
return cqi_to_mcs[cqi];
}
}
// This function returns the estimated number of RBs required by each UE for downlink scheduling
......@@ -210,7 +218,8 @@ assign_rbs_required(module_id_t Mod_id,
CC_id = UE_list->ordered_CCids[n][UE_id];
eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];
// eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]);
eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]), slice_maxmcs[slice_id]);
eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id], slice_id),
slice_maxmcs[slice_id]);
}
......@@ -418,6 +427,7 @@ static int ue_dl_compare(const void *_a, const void *_b, void *_params)
return -1;
if (cqi1 < cqi2)
return 1;
break;
case CR_LCP :
if (lcgid1 < lcgid2)
......@@ -494,7 +504,7 @@ void decode_sorting_policy_ul(module_id_t Mod_idP, slice_id_t slice_id) {
criterion = (uint16_t) (policy >> 4 * (CRU_NUM - 1 - i) & mask);
if (criterion >= CRU_NUM) {
LOG_W(MAC, "Invalid criterion in uplink slice %d policy, revert to default policy \n", slice_id);
slice_sorting_uplink[slice_id] = 0x123;
slice_sorting_uplink[slice_id] = 0x12345;
break;
}
UE_list->sorting_criteria_ul[slice_id][i] = criterion;
......@@ -1707,9 +1717,8 @@ dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id,
void
ulsch_scheduler_pre_processor(module_id_t module_idP,
slice_id_t slice_id, int frameP,
sub_frame_t subframeP, uint16_t * first_rb)
{
slice_id_t slice_id, int frameP,
sub_frame_t subframeP, uint16_t *first_rb) {
uint16_t UE_id, n;
uint8_t CC_id;
......@@ -1725,35 +1734,45 @@ ulsch_scheduler_pre_processor(module_id_t module_idP,
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
total_allocated_rbs[CC_id] = 0;
total_ue_count[CC_id] = 0;
UE_list->first_rb_offset[CC_id][slice_id] = 0;
}
LOG_D(MAC, "In ulsch_preprocessor: assign max mcs min rb\n");
// maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
assign_max_mcs_min_rb(module_idP, slice_id, frameP, subframeP, first_rb);
LOG_D(MAC, "In ulsch_preprocessor: sort ue \n");
// sort ues
sort_ue_ul(module_idP, slice_id, frameP, subframeP);
// we need to distribute RBs among UEs
ulsch_scheduler_pre_processor_accounting(module_idP,
slice_id,
frameP,
subframeP,
first_rb,
total_ue_count,
nb_allocated_rbs,
total_allocated_rbs);
ulsch_scheduler_pre_processor_allocation(module_idP,
slice_id,
frameP,
subframeP,
first_rb,
total_ue_count,
nb_allocated_rbs,
total_allocated_rbs);
LOG_D(MAC, "In ulsch_preprocessor: assign max mcs min rb\n");
// maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
assign_max_mcs_min_rb(module_idP, slice_id, frameP, subframeP, first_rb);
// The output from assign_max_mcs_min_rb() is:
// UE_template->pre_assigned_mcs_ul // MCS for each UE
// UE_template->pre_allocated_rb_table_index_ul // RB table index
// UE_template->pre_allocated_nb_rb_ul[slice_id] // Allocated RBs for each UE
LOG_D(MAC, "In ulsch_preprocessor: sort ue \n");
// sort ues
sort_ue_ul(module_idP, slice_id, frameP, subframeP);
// In short, the following function does:
// nb_allocated_rbs = min (pre_allocated_nb_rb_ul[slice_id], average_rbs_per_user)
ulsch_scheduler_pre_processor_accounting(module_idP,
slice_id,
frameP,
subframeP,
first_rb,
total_ue_count,
nb_allocated_rbs,
total_allocated_rbs);
ulsch_scheduler_pre_processor_intraslice_sharing(module_idP,
slice_id,
frameP,
subframeP,
first_rb,
total_ue_count,
nb_allocated_rbs,
total_allocated_rbs);
// The output of this is:
// UE_template->pre_allocated_nb_rb_ul[] updated
// LOG
for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
......@@ -1783,10 +1802,8 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
sub_frame_t subframeP, uint16_t * first_rb)
{
int i;
uint16_t n, UE_id;
uint8_t CC_id;
rnti_t rnti = -1;
int mcs;
int rb_table_index = 0, tbs, tx_power;
eNB_MAC_INST *eNB = RC.mac[module_idP];
......@@ -1796,21 +1813,17 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
UE_sched_ctrl *ue_sched_ctl;
int Ncp;
int N_RB_UL;
int bytes_to_schedule, bits_to_schedule;
int first_rb_offset, available_rbs;
for (i = 0; i < NUMBER_OF_UE_MAX; i++) {
if (UE_list->active[i] != TRUE)
continue;
rnti = UE_RNTI(module_idP, i);
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
continue;
if (!ue_slice_membership(i, slice_id))
continue;
if (UE_list->active[UE_id] != TRUE) continue;
if (UE_RNTI(module_idP, UE_id) == NOT_A_RNTI) continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue;
if (!ue_slice_membership(UE_id, slice_id)) continue;
if (UE_list->UE_sched_ctrl[i].phr_received == 1) {
if (UE_list->UE_sched_ctrl[UE_id].phr_received == 1) {
/* if we've received the power headroom information the UE, we can go to
* maximum mcs */
mcs = cmin(20, slice_maxmcs_uplink[slice_id]);
......@@ -1819,21 +1832,12 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
mcs = cmin(10, slice_maxmcs_uplink[slice_id]);
}
UE_id = i;
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
if (CC_id >= MAX_NUM_CCs) {
LOG_E(MAC, "CC_id %u should be < %u, loop n=%u < numactiveULCCs[%u]=%u",
CC_id, MAX_NUM_CCs, n, UE_id, UE_list->numactiveULCCs[UE_id]);
}
AssertFatal(CC_id < MAX_NUM_CCs,
"CC_id %u should be < %u, loop n=%u < numactiveULCCs[%u]=%u",
CC_id, MAX_NUM_CCs, n, UE_id,
UE_list->numactiveULCCs[UE_id]);
AssertFatal(CC_id < MAX_NUM_CCs, "CC_id %u should be < %u, loop n=%u < numactiveULCCs[%u]=%u",
CC_id, MAX_NUM_CCs, n, UE_id, UE_list->numactiveULCCs[UE_id]);
UE_template = &UE_list->UE_template[CC_id][UE_id];
UE_template->pre_assigned_mcs_ul = mcs;
......@@ -1841,12 +1845,12 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
Ncp = RC.mac[module_idP]->common_channels[CC_id].Ncp;
N_RB_UL = to_prb(RC.mac[module_idP]->common_channels[CC_id].ul_Bandwidth);
ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] =
nb_rbs_allowed_slice(slice_percentage_uplink[slice_id], N_RB_UL);
ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] = nb_rbs_allowed_slice(slice_percentage_uplink[slice_id], N_RB_UL);
int bytes_to_schedule = UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes;
if (bytes_to_schedule < 0) bytes_to_schedule = 0;
int bits_to_schedule = bytes_to_schedule * 8;
bytes_to_schedule = UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes;
if (bytes_to_schedule < 0)
bytes_to_schedule = 0;
bits_to_schedule = bytes_to_schedule * 8;
// if this UE has UL traffic
if (bits_to_schedule > 0) {
......@@ -1856,34 +1860,38 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
// fixme: set use_srs flag
tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
while ((((UE_template->phr_info - tx_power) < 0)
|| (tbs > bits_to_schedule))
&& (UE_template->pre_assigned_mcs_ul > 3)) {
// Adapt MCS -------------
while ((((UE_template->phr_info - tx_power) < 0) || (tbs > bits_to_schedule))
&& (UE_template->pre_assigned_mcs_ul > 3)) {
// LOG_I(MAC,"UE_template->phr_info %d tx_power %d mcs %d\n", UE_template->phr_info,tx_power, mcs);
UE_template->pre_assigned_mcs_ul--;
tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); // fixme: set use_srs
}
// -----------------------
// Adapt PRB size --------
first_rb_offset = UE_list->first_rb_offset[CC_id][slice_id];
available_rbs = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id] - first_rb_offset;
while ((tbs < bits_to_schedule)
&& (rb_table[rb_table_index] < (ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id]))
&& ((UE_template->phr_info - tx_power) > 0)
&& (rb_table_index < 32)) {
&& (rb_table[rb_table_index] < available_rbs)
&& ((UE_template->phr_info - tx_power) > 0)
&& (rb_table_index < 32)) {
rb_table_index++;
tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
}
UE_template->ue_tx_power = tx_power;
if (rb_table[rb_table_index] > (ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id] - 1)) {
if (rb_table[rb_table_index] > (available_rbs - 1)) {
rb_table_index--;
}
// 1 or 2 PRB with cqi enabled does not work well
if (rb_table[rb_table_index] < 3) {
rb_table_index = 2; //3PRB
}
// -----------------------
UE_template->ue_tx_power = tx_power;
UE_template->pre_allocated_rb_table_index_ul = rb_table_index;
UE_template->pre_allocated_nb_rb_ul[slice_id] = rb_table[rb_table_index];
LOG_D(MAC,
......@@ -1892,11 +1900,12 @@ assign_max_mcs_min_rb(module_id_t module_idP, int slice_id, int frameP,
UE_template->pre_assigned_mcs_ul,
UE_template->pre_allocated_rb_table_index_ul,
UE_template->pre_allocated_nb_rb_ul[slice_id],
UE_template->phr_info, tx_power);
UE_template->phr_info,
UE_template->ue_tx_power = tx_power);
} else {
/* if UE has pending scheduling request then pre-allocate 3 RBs */
//if (UE_template->ul_active == 1 && UE_template->ul_SR == 1) {
if (UE_is_to_be_scheduled(module_idP, CC_id, i)) {
if (UE_is_to_be_scheduled(module_idP, CC_id, UE_id)) {
/* use QPSK mcs */
UE_template->pre_assigned_mcs_ul = 10;
UE_template->pre_allocated_rb_table_index_ul = 2;
......@@ -1922,7 +1931,7 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
int n;
int CC_id, UE_id, N_RB_UL, harq_pid;
uint16_t available_rbs;
uint16_t available_rbs, first_rb_offset;
UE_TEMPLATE *UE_template;
UE_sched_ctrl *ue_sched_ctl;
rnti_t rnti;
......@@ -1939,8 +1948,7 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
if (!ue_slice_membership(UE_id, slice_id))
continue;
if (!ue_slice_membership(UE_id, slice_id)) continue;
if (UE_template->pre_allocated_nb_rb_ul[slice_id] > 0) {
total_ue_count[CC_id] += 1;
}
......@@ -1953,12 +1961,9 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
rnti = UE_RNTI(module_idP, UE_id);
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
if (!ue_slice_membership(UE_id, slice_id))
continue;
if (rnti == NOT_A_RNTI) continue;
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1) continue;
if (!ue_slice_membership(UE_id, slice_id)) continue;
LOG_D(MAC, "In ulsch_preprocessor: handling UE %d/%x\n", UE_id, rnti);
for (n = 0; n < UE_list->numactiveULCCs[UE_id]; ++n) {
......@@ -1973,7 +1978,8 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] =
nb_rbs_allowed_slice(slice_percentage_uplink[slice_id], N_RB_UL);
available_rbs = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id];
first_rb_offset = UE_list->first_rb_offset[CC_id][slice_id];
available_rbs = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id] - first_rb_offset;
if (total_ue_count[CC_id] == 0) {
average_rbs_per_user[CC_id] = 0;
......@@ -2012,8 +2018,7 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
nb_allocated_rbs[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid];
} else {
nb_allocated_rbs[CC_id][UE_id] =
cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_id],
average_rbs_per_user[CC_id]);
cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_id], average_rbs_per_user[CC_id]);
}
total_allocated_rbs[CC_id] += nb_allocated_rbs[CC_id][UE_id];
......@@ -2025,17 +2030,17 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
}
}
void ulsch_scheduler_pre_processor_allocation(module_id_t module_idP,
slice_id_t slice_id,
int frameP,
sub_frame_t subframeP,
uint16_t * first_rb,
uint16_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t total_allocated_rbs[MAX_NUM_CCs]) {
void ulsch_scheduler_pre_processor_intraslice_sharing(module_id_t module_idP,
slice_id_t slice_id,
int frameP,
sub_frame_t subframeP,
uint16_t *first_rb,
uint16_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t total_allocated_rbs[MAX_NUM_CCs]) {
int n;
int CC_id, UE_id;
uint16_t available_rbs;
uint16_t available_rbs, first_rb_offset;
UE_TEMPLATE *UE_template;
UE_sched_ctrl *ue_sched_ctl;
UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
......@@ -2060,7 +2065,8 @@ void ulsch_scheduler_pre_processor_allocation(module_id_t module_idP,
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
available_rbs = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id];
first_rb_offset = UE_list->first_rb_offset[CC_id][slice_id];
available_rbs = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id] - first_rb_offset;
total_remaining_rbs[CC_id] = available_rbs - total_allocated_rbs[CC_id];
if (total_ue_count[CC_id] == 1) {
......@@ -2070,8 +2076,7 @@ void ulsch_scheduler_pre_processor_allocation(module_id_t module_idP,
while ((UE_template->pre_allocated_nb_rb_ul[slice_id] > 0)
&& (nb_allocated_rbs[CC_id][UE_id] < UE_template->pre_allocated_nb_rb_ul[slice_id])
&& (total_remaining_rbs[CC_id] > 0)) {
nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id] + 1,
UE_template->pre_allocated_nb_rb_ul[slice_id]);
nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id] + 1, UE_template->pre_allocated_nb_rb_ul[slice_id]);
total_remaining_rbs[CC_id]--;
total_allocated_rbs[CC_id]++;
}
......@@ -2119,6 +2124,9 @@ static int ue_ul_compare(const void *_a, const void *_b, void *_params) {
if (bytes_to_schedule1 < 0) bytes_to_schedule1 = 0;
if (bytes_to_schedule2 < 0) bytes_to_schedule2 = 0;
long lcgid1 = min_lcgidpriority(params->module_idP, UE_id1);
long lcgid2 = min_lcgidpriority(params->module_idP, UE_id2);
for (i = 0; i < CRU_NUM; ++i) {
switch (UE_list->sorting_criteria_ul[slice_id][i]) {
......@@ -2154,6 +2162,21 @@ static int ue_ul_compare(const void *_a, const void *_b, void *_params) {
return 1;
break;
case CRU_LCP :
if (lcgid1 < lcgid2)
return -1;
if (lcgid1 > lcgid2)
return 1;
case CRU_HOL :
if (UE_list-> UE_template[pCCid1][UE_id1].ul_buffer_creation_time_max >
UE_list-> UE_template[pCCid2][UE_id2].ul_buffer_creation_time_max)
return -1;
if (UE_list-> UE_template[pCCid1][UE_id1].ul_buffer_creation_time_max <
UE_list-> UE_template[pCCid2][UE_id2].ul_buffer_creation_time_max)
return 1;
break;
default:
break;
}
......
openair2/LAYER2/MAC/proto.h
View file @ 5737fafa
......@@ -704,14 +704,14 @@ void ulsch_scheduler_pre_processor_accounting(module_id_t module_idP,
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t total_allocated_rbs[MAX_NUM_CCs]);
void ulsch_scheduler_pre_processor_allocation(module_id_t module_idP,
slice_id_t slice_id,
int frameP,
sub_frame_t subframeP,
uint16_t * first_rb,
uint16_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t total_allocated_rbs[MAX_NUM_CCs]);
void ulsch_scheduler_pre_processor_intraslice_sharing(module_id_t module_idP,
slice_id_t slice_id,
int frameP,
sub_frame_t subframeP,
uint16_t *first_rb,
uint16_t total_ue_count[MAX_NUM_CCs],
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t total_allocated_rbs[MAX_NUM_CCs]);
void adjust_bsr_info(int buffer_occupancy, uint16_t TBS,
UE_TEMPLATE * UE_template);
......
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