Commit 63989e8a authored by Robert Schmidt's avatar Robert Schmidt

Fix for F1 RFsim fail

We compute the preferred DL TDAs when receiving the cellGroup from the
RRC. However, in F1 and the RFsim, it seems that the scheduler tries to
access the preferred DL TDAs before they have been set after receiving
the cellGroup. In this commit, add a simple check to verify the
preferred TDA has been set up.
parent ff0fb530
......@@ -895,7 +895,10 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
/* This is temporary and it assumes all UEs have the same BWP and TDA*/
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
if (!RC.nrmac[module_id]->preferred_dl_tda[bwp_id])
return;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[bwp_id][slot];
int startSymbolIndex, nrOfSymbols;
const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = sched_ctrl->active_bwp ?
sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList :
......
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