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Commit 75ec3861 authored by francescomani's avatar francescomani
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moving decision on DCI format type from L1 to MAC

parent 3f3a9869
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Showing with 877 additions and 816 deletions
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
View file @ 75ec3861
......@@ -94,7 +94,7 @@ typedef struct {
typedef struct {
uint16_t rnti;
uint8_t dci_format;
nfapi_nr_dci_formats_e dci_format;
uint8_t coreset_type;
int ss_type;
// n_CCE index of first CCE for PDCCH reception
......@@ -426,7 +426,7 @@ typedef struct {
// needs to monitor only upto 2 DCI lengths for a given search space.
uint8_t num_dci_options; // Num DCIs the UE actually needs to decode (1 or 2)
uint8_t dci_length_options[2];
uint8_t dci_format_options[2];
nfapi_nr_dci_formats_e dci_format_options[2];
uint8_t ss_type_options[2];
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
......
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
View file @ 75ec3861
......@@ -240,9 +240,9 @@ typedef struct {
} nfapi_nr_config_request_t;
typedef enum {
NFAPI_NR_USS_FORMAT_0_0_AND_1_0,
NFAPI_NR_USS_FORMAT_0_1_AND_1_1,
} nfapi_nr_uss_dci_formats_e;
NFAPI_NR_FORMAT_0_0_AND_1_0,
NFAPI_NR_FORMAT_0_1_AND_1_1,
} nfapi_nr_dci_formats_e;
typedef enum {
NFAPI_NR_SEARCH_SPACE_TYPE_COMMON=0,
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ 75ec3861
......@@ -43,15 +43,6 @@
#include "assertions.h"
#include "T.h"
static const char nr_dci_format_string[8][30] = {"NR_DL_DCI_FORMAT_1_0",
"NR_DL_DCI_FORMAT_1_1",
"NR_DL_DCI_FORMAT_2_0",
"NR_DL_DCI_FORMAT_2_1",
"NR_DL_DCI_FORMAT_2_2",
"NR_DL_DCI_FORMAT_2_3",
"NR_UL_DCI_FORMAT_0_0",
"NR_UL_DCI_FORMAT_0_1"};
//#define DEBUG_DCI_DECODING 1
//#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs
......@@ -780,24 +771,22 @@ static uint16_t nr_dci_false_detection(uint64_t *dci,
int rnti,
int8_t messageType,
uint16_t messageLength,
uint8_t aggregation_level
) {
uint8_t aggregation_level)
{
uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
polar_encoder_fast(dci, (void*)encoder_output, rnti, 1,
messageType, messageLength, aggregation_level);
polar_encoder_fast(dci, (void *)encoder_output, rnti, 1, messageType, messageLength, aggregation_level);
uint8_t *enout_p = (uint8_t*)encoder_output;
uint16_t x = 0;
for (int i=0; i<encoded_length/8; i++) {
x += ( enout_p[i] & 1 ) ^ ( ( soft_in[i*8] >> 15 ) & 1);
x += ( ( enout_p[i] >> 1 ) & 1 ) ^ ( ( soft_in[i*8+1] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 2 ) & 1 ) ^ ( ( soft_in[i*8+2] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 3 ) & 1 ) ^ ( ( soft_in[i*8+3] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 4 ) & 1 ) ^ ( ( soft_in[i*8+4] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 5 ) & 1 ) ^ ( ( soft_in[i*8+5] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 6 ) & 1 ) ^ ( ( soft_in[i*8+6] >> 15 ) & 1 );
x += ( ( enout_p[i] >> 7 ) & 1 ) ^ ( ( soft_in[i*8+7] >> 15 ) & 1 );
x += (enout_p[i] & 1) ^ ((soft_in[i * 8] >> 15) & 1);
x += ((enout_p[i] >> 1) & 1) ^ ((soft_in[i * 8 + 1] >> 15) & 1);
x += ((enout_p[i] >> 2) & 1) ^ ((soft_in[i * 8 + 2] >> 15) & 1);
x += ((enout_p[i] >> 3) & 1) ^ ((soft_in[i * 8 + 3] >> 15) & 1);
x += ((enout_p[i] >> 4) & 1) ^ ((soft_in[i * 8 + 4] >> 15) & 1);
x += ((enout_p[i] >> 5) & 1) ^ ((soft_in[i * 8 + 5] >> 15) & 1);
x += ((enout_p[i] >> 6) & 1) ^ ((soft_in[i * 8 + 6] >> 15) & 1);
x += ((enout_p[i] >> 7) & 1) ^ ((soft_in[i * 8 + 7] >> 15) & 1);
}
return x;
}
......@@ -809,11 +798,11 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15)
{
//int gNB_id = 0;
int16_t tmp_e[16*108];
int16_t tmp_e[16 * 108];
rnti_t n_rnti;
int e_rx_cand_idx = 0;
for (int j=0;j<rel15->number_of_candidates;j++) {
for (int j = 0; j < rel15->number_of_candidates; j++) {
int CCEind = rel15->CCE[j];
int L = rel15->L[j];
......@@ -822,48 +811,75 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
for (int k = 0; k < rel15->num_dci_options; k++) {
// skip this candidate if we've already found one with the
// same rnti and format at a different aggregation level
int dci_found=0;
for (int ind=0;ind < dci_ind->number_of_dcis ; ind++) {
if (rel15->rnti== dci_ind->dci_list[ind].rnti &&
rel15->dci_format_options[k]==dci_ind->dci_list[ind].dci_format) {
dci_found=1;
break;
bool dci_found = false;
for (int ind = 0; ind < dci_ind->number_of_dcis; ind++) {
if (rel15->rnti == dci_ind->dci_list[ind].rnti && rel15->dci_format_options[k] == dci_ind->dci_list[ind].dci_format) {
dci_found = true;
break;
}
}
if (dci_found == 1)
if (dci_found)
continue;
int dci_length = rel15->dci_length_options[k];
uint64_t dci_estimation[2]= {0};
LOG_D(PHY, "(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %s\n",
proc->frame_rx, proc->nr_slot_rx, j, rel15->number_of_candidates, CCEind, e_rx_cand_idx, L, dci_length, nr_dci_format_string[rel15->dci_format_options[k]]);
nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e);
uint64_t dci_estimation[2] = {0};
LOG_D(PHY,
"(%i.%i) Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d, length %d, format %d\n",
proc->frame_rx,
proc->nr_slot_rx,
j,
rel15->number_of_candidates,
CCEind,
e_rx_cand_idx,
L,
dci_length,
rel15->dci_format_options[k]);
nr_pdcch_unscrambling(&pdcch_e_rx[e_rx_cand_idx],
rel15->coreset.scrambling_rnti,
L * 108,
rel15->coreset.pdcch_dmrs_scrambling_id,
tmp_e);
#ifdef DEBUG_DCI_DECODING
uint32_t *z = (uint32_t *) &e_rx[e_rx_cand_idx];
for (int index_z = 0; index_z < L*6; index_z++){
for (int i=0; i<9; i++) {
LOG_I(PHY,"z[%d]=(%d,%d) \n", (9*index_z + i), *(int16_t *) &z[9*index_z + i],*(1 + (int16_t *) &z[9*index_z + i]));
for (int index_z = 0; index_z < L * 6; index_z++) {
for (int i = 0; i < 9; i++) {
LOG_I(PHY, "z[%d]=(%d,%d) \n", (9 * index_z + i), *(int16_t *)&z[9 * index_z + i], *(1 + (int16_t *)&z[9 * index_z + i]));
}
}
#endif
uint16_t crc = polar_decoder_int16(tmp_e,
dci_estimation,
1,
NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
uint16_t crc = polar_decoder_int16(tmp_e, dci_estimation, 1, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
n_rnti = rel15->rnti;
LOG_D(PHY, "(%i.%i) dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx )\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length, *(unsigned long long*)dci_estimation);
LOG_D(PHY,
"(%i.%i) dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx )\n",
proc->frame_rx,
proc->nr_slot_rx,
n_rnti,
rel15->dci_format_options[k],
CCEind,
dci_length,
*(unsigned long long *)dci_estimation);
if (crc == n_rnti) {
LOG_D(PHY, "(%i.%i) Received dci indication (rnti %x,dci format %s,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,nr_dci_format_string[rel15->dci_format_options[k]],CCEind,dci_length,*(unsigned long long*)dci_estimation);
LOG_D(PHY,
"(%i.%i) Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx,
proc->nr_slot_rx,
n_rnti,
rel15->dci_format_options[k],
CCEind,
dci_length,
*(unsigned long long *)dci_estimation);
uint16_t mb = nr_dci_false_detection(dci_estimation,tmp_e,L*108,n_rnti, NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L);
ue->dci_thres = (ue->dci_thres + mb) / 2;
if (mb > (ue->dci_thres+30)) {
LOG_W(PHY,"DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n",j,mb,L*108,ue->dci_thres);
LOG_W(PHY,
"DCI false positive. Dropping DCI index %d. Mismatched bits: %d/%d. Current DCI threshold: %d\n",
j,
mb,
L * 108,
ue->dci_thres);
continue;
} else {
dci_ind->SFN = proc->frame_rx;
......@@ -878,15 +894,22 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
get_coreset_rballoc(rel15->coreset.frequency_domain_resource, &n_rb, &rb_offset);
dci_ind->dci_list[dci_ind->number_of_dcis].cset_start = rel15->BWPStart + rb_offset;
dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length;
memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8);
memcpy((void *)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits, (void *)dci_estimation, 8);
dci_ind->number_of_dcis++;
break; // If DCI is found, no need to check for remaining DCI lengths
}
} else {
LOG_D(PHY,"(%i.%i) Decoded crc %x does not match rnti %x for DCI format %d\n", proc->frame_rx, proc->nr_slot_rx, crc, n_rnti, rel15->dci_format_options[k]);
LOG_D(PHY,
"(%i.%i) Decoded crc %x does not match rnti %x for DCI format %d\n",
proc->frame_rx,
proc->nr_slot_rx,
crc,
n_rnti,
rel15->dci_format_options[k]);
}
}
e_rx_cand_idx += 9*L*6*2; //e_rx index for next candidate (L CCEs, 6 REGs per CCE and 9 REs per REG and 2 uint16_t per RE)
e_rx_cand_idx += 9 * L * 6 * 2; // e_rx index for next candidate (L CCEs, 6 REGs per CCE and 9 REs per REG and 2 uint16_t per
// RE)
}
return(dci_ind->number_of_dcis);
}
openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
View file @ 75ec3861
......@@ -39,8 +39,6 @@
extern const uint8_t nr_slots_per_frame[5];
extern dci_pdu_rel15_t *def_dci_pdu_rel15;
/* Scheduler */
extern RAN_CONTEXT_t RC;
extern uint8_t nfapi_mode;
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ 75ec3861
......@@ -260,18 +260,7 @@ int nr_get_sf_periodicBSRTimer(uint8_t bucketSize);
*/
int nr_get_sf_retxBSRTimer(uint8_t retxBSR_Timer);
int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
fapi_nr_dci_indication_pdu_t *dci_ind);
int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac,
int cc_id,
int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci);
nr_dci_format_t nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci);
int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac,
frame_t frame,
int slot,
......
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @ 75ec3861
......@@ -101,7 +101,6 @@ NR_ControlResourceSet_t *ue_get_coreset(const NR_BWP_PDCCH_t *config, const int
return coreset;
}
void config_dci_pdu(NR_UE_MAC_INST_t *mac,
fapi_nr_dl_config_request_t *dl_config,
const int rnti_type,
......@@ -154,36 +153,40 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
rel15->coreset.pdcch_dmrs_scrambling_id = mac->physCellId;
}
rel15->num_dci_options = (mac->ra.ra_state == WAIT_RAR || rnti_type == TYPE_SI_RNTI_) ? 1 : 2;
int temp_num_dci_options = (mac->ra.ra_state == WAIT_RAR || rnti_type == TYPE_SI_RNTI_) ? 1 : 2;
int dci_format[2] = {0};
if (ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) {
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats ==
NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) {
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0;
dci_format[0] = NR_DL_DCI_FORMAT_1_0;
dci_format[1] = NR_UL_DCI_FORMAT_0_0;
}
else {
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_1;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_1;
dci_format[0] = NR_DL_DCI_FORMAT_1_1;
dci_format[1] = NR_UL_DCI_FORMAT_0_1;
}
}
else { // common
AssertFatal(ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0,
"Only supporting format 10 and 00 for common SS\n");
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0;
dci_format[0] = NR_DL_DCI_FORMAT_1_0;
dci_format[1] = NR_UL_DCI_FORMAT_0_0;
}
NR_UE_ServingCell_Info_t *sc_info = &mac->sc_info;
// loop over RNTI type and configure resource allocation for DCI
for (int i = 0; i < rel15->num_dci_options; i++) {
// loop over DCI options and configure resource allocation
// need to configure mac->def_dci_pdu_rel15 for all possible format options
for (int i = 0; i < temp_num_dci_options; i++) {
rel15->ss_type_options[i] = ss->searchSpaceType->present;
const int dci_format = rel15->dci_format_options[i];
if (dci_format[i] == NR_DL_DCI_FORMAT_1_0 || dci_format[i] == NR_UL_DCI_FORMAT_0_0)
rel15->dci_format_options[i] = NFAPI_NR_FORMAT_0_0_AND_1_0;
else
rel15->dci_format_options[i] = NFAPI_NR_FORMAT_0_1_AND_1_1;
uint16_t alt_size = 0;
if(current_DL_BWP) {
// computing alternative size for padding
// computing alternative size for padding or truncation
dci_pdu_rel15_t temp_pdu;
if(dci_format == NR_DL_DCI_FORMAT_1_0)
if (dci_format[i] == NR_DL_DCI_FORMAT_1_0)
alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
......@@ -196,7 +199,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs,
0);
if(dci_format == NR_UL_DCI_FORMAT_0_0)
if (dci_format[i] == NR_UL_DCI_FORMAT_0_0)
alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
......@@ -215,8 +218,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
current_UL_BWP,
sc_info,
mac->pdsch_HARQ_ACK_Codebook,
&mac->def_dci_pdu_rel15[dl_config->slot][dci_format],
dci_format,
&mac->def_dci_pdu_rel15[dl_config->slot][dci_format[i]],
dci_format[i],
rnti_type,
coreset,
dl_bwp_id,
......@@ -225,6 +228,13 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
alt_size);
}
// DCI 0_0 and 1_0 are same size, L1 just needs to look for 1 option
// L2 decides format based on format indicator in payload
if (rel15->dci_format_options[0] == NFAPI_NR_FORMAT_0_0_AND_1_0)
rel15->num_dci_options = 1;
else
rel15->num_dci_options = 2;
rel15->BWPStart = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.cset_start_rb : current_DL_BWP->BWPStart;
rel15->BWPSize = coreset_id == 0 ? mac->type0_PDCCH_CSS_config.num_rbs : current_DL_BWP->BWPSize;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ 75ec3861
......@@ -164,14 +164,13 @@ const initial_pucch_resource_t initial_pucch_resource[16] = {
/* 14 */ { 1, 0, 14, 4, 4, { 0, 3, 6, 9 } },
/* 15 */ { 1, 0, 14, 0, 4, { 0, 3, 6, 9 } },
};
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nr_dci_format_t dci_format,
uint8_t dci_size,
uint16_t rnti,
int ss_type,
uint64_t *dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int slot);
static nr_dci_format_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nfapi_nr_dci_formats_e dci_format,
uint8_t dci_size,
uint16_t rnti,
int ss_type,
uint64_t *dci_pdu,
int slot);
int get_rnti_type(NR_UE_MAC_INST_t *mac, uint16_t rnti)
{
......@@ -368,29 +367,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
return 0;
}
int nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac,
int cc_id,
int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci)
{
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format];
LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits);
const int ret = nr_extract_dci_info(mac, dci->dci_format, dci->payloadSize, dci->rnti, dci->ss_type, (uint64_t *)dci->payloadBits, def_dci_pdu_rel15, slot);
if ((ret & 1) == 1)
return -1;
else if (ret == 2) {
dci->dci_format = (dci->dci_format == NR_UL_DCI_FORMAT_0_0) ? NR_DL_DCI_FORMAT_1_0 : NR_UL_DCI_FORMAT_0_0;
def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][dci->dci_format];
}
return nr_ue_process_dci(mac, cc_id, frame, slot, def_dci_pdu_rel15, dci);
}
static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
......@@ -446,7 +423,6 @@ static int nr_ue_process_dci_ul_00(NR_UE_MAC_INST_t *mac,
}
static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
......@@ -519,7 +495,6 @@ static int nr_ue_process_dci_ul_01(NR_UE_MAC_INST_t *mac,
}
static int nr_ue_process_dci_dl_10(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
......@@ -852,7 +827,6 @@ static inline uint16_t packBits(const uint8_t *toPack, const int nb)
}
static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
......@@ -1218,31 +1192,31 @@ static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac,
return 0;
}
int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
int cc_id,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
fapi_nr_dci_indication_pdu_t *dci_ind)
static int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
frame_t frame,
int slot,
dci_pdu_rel15_t *dci,
fapi_nr_dci_indication_pdu_t *dci_ind,
const nr_dci_format_t format)
{
const char *dci_formats[] = {"1_0", "1_1", "2_0", "2_1", "2_2", "2_3", "0_0", "0_1"};
LOG_D(MAC, "Processing received DCI format %s\n", dci_formats[dci_ind->dci_format]);
LOG_D(MAC, "Processing received DCI format %s\n", dci_formats[format]);
switch (dci_ind->dci_format) {
switch (format) {
case NR_UL_DCI_FORMAT_0_0:
return nr_ue_process_dci_ul_00(mac, cc_id, frame, slot, dci, dci_ind);
return nr_ue_process_dci_ul_00(mac, frame, slot, dci, dci_ind);
break;
case NR_UL_DCI_FORMAT_0_1:
return nr_ue_process_dci_ul_01(mac, cc_id, frame, slot, dci, dci_ind);
return nr_ue_process_dci_ul_01(mac, frame, slot, dci, dci_ind);
break;
case NR_DL_DCI_FORMAT_1_0:
return nr_ue_process_dci_dl_10(mac, cc_id, frame, slot, dci, dci_ind);
return nr_ue_process_dci_dl_10(mac, frame, slot, dci, dci_ind);
break;
case NR_DL_DCI_FORMAT_1_1:
return nr_ue_process_dci_dl_11(mac, cc_id, frame, slot, dci, dci_ind);
return nr_ue_process_dci_dl_11(mac, frame, slot, dci, dci_ind);
break;
case NR_DL_DCI_FORMAT_2_0:
......@@ -1264,10 +1238,29 @@ int8_t nr_ue_process_dci(NR_UE_MAC_INST_t *mac,
default:
break;
}
return -1;
}
nr_dci_format_t nr_ue_process_dci_indication_pdu(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci)
{
LOG_D(MAC,
"Received dci indication (rnti %x, dci format %d, n_CCE %d, payloadSize %d, payload %llx)\n",
dci->rnti,
dci->dci_format,
dci->n_CCE,
dci->payloadSize,
*(unsigned long long *)dci->payloadBits);
const nr_dci_format_t format =
nr_extract_dci_info(mac, dci->dci_format, dci->payloadSize, dci->rnti, dci->ss_type, (uint64_t *)dci->payloadBits, slot);
if (format == NR_DCI_NONE)
return NR_DCI_NONE;
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
int ret = nr_ue_process_dci(mac, frame, slot, def_dci_pdu_rel15, dci, format);
if (ret < 0)
return NR_DCI_NONE;
return format;
}
int8_t nr_ue_process_csirs_measurements(NR_UE_MAC_INST_t *mac,
frame_t frame,
int slot,
......@@ -2876,689 +2869,750 @@ void nr_ue_send_sdu(NR_UE_MAC_INST_t *mac, nr_downlink_indication_t *dl_info, in
}
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nr_dci_format_t dci_format,
uint8_t dci_size,
uint16_t rnti,
int ss_type,
uint64_t *dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int slot)
static void extract_10_ra_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size, int N_RB)
{
LOG_D(MAC,"nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *dci_pdu, dci_size, dci_format);
int pos = 0;
int fsize = 0;
int rnti_type = get_rnti_type(mac, rnti);
NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
int N_RB;
if(current_DL_BWP)
N_RB = get_rb_bwp_dci(dci_format,
ss_type,
mac->type0_PDCCH_CSS_config.num_rbs,
current_UL_BWP->BWPSize,
current_DL_BWP->BWPSize,
mac->sc_info.initial_dl_BWPSize,
mac->sc_info.initial_dl_BWPSize);
else
N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
if (N_RB == 0) {
LOG_E(MAC, "DCI configuration error! N_RB = 0\n");
return 1;
}
switch(dci_format) {
case NR_DL_DCI_FORMAT_1_0:
switch(rnti_type) {
case TYPE_RA_RNTI_:
// Freq domain assignment
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos = fsize;
dci_pdu_rel15->frequency_domain_assignment.val = *dci_pdu >> (dci_size - pos) & ((1 << fsize) - 1);
// Freq domain assignment
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos = fsize;
dci_pdu_rel15->frequency_domain_assignment.val = *dci_pdu >> (dci_size - pos) & ((1 << fsize) - 1);
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",
dci_pdu_rel15->frequency_domain_assignment.val,
fsize,
N_RB,
dci_size - pos,
*dci_pdu);
#endif
// Time domain assignment
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size-pos))&0xf;
// Time domain assignment
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",
dci_pdu_rel15->time_domain_assignment.val,
dci_size - pos,
*dci_pdu);
#endif
// VRB to PRB mapping
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&0x1;
// VRB to PRB mapping
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 0x1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
LOG_D(MAC, "vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n", dci_pdu_rel15->vrb_to_prb_mapping.val, dci_size - pos, *dci_pdu);
#endif
// MCS
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// MCS
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
LOG_D(MAC, "mcs %d (5 bits)=> %d (0x%lx)\n", dci_pdu_rel15->mcs, dci_size - pos, *dci_pdu);
#endif
// TB scaling
pos+=2;
dci_pdu_rel15->tb_scaling = (*dci_pdu>>(dci_size-pos))&0x3;
// TB scaling
pos += 2;
dci_pdu_rel15->tb_scaling = (*dci_pdu >> (dci_size - pos)) & 0x3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
LOG_D(MAC, "tb_scaling %d (2 bits)=> %d (0x%lx)\n", dci_pdu_rel15->tb_scaling, dci_size - pos, *dci_pdu);
#endif
break;
case TYPE_C_RNTI_:
}
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
static void extract_10_si_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size, int N_RB)
{
int pos = 0;
int fsize = 0;
// Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
// Time domain assignment 4 bit
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
// VRB to PRB mapping 1 bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 0x1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// Redundancy version 2 bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
// System information indicator 1 bit
pos++;
dci_pdu_rel15->system_info_indicator = (*dci_pdu >> (dci_size - pos)) & 0x1;
LOG_D(MAC, "N_RB = %i\n", N_RB);
LOG_D(MAC, "dci_size = %i\n", dci_size);
LOG_D(MAC, "fsize = %i\n", fsize);
LOG_D(MAC, "dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(MAC, "dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(MAC, "dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(MAC, "dci_pdu_rel15->system_info_indicator = %i\n", dci_pdu_rel15->system_info_indicator);
}
// switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
static void extract_10_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size, int N_RB)
{
int pos = 0;
int fsize = 0;
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
AssertFatal(dci_pdu_rel15->format_indicator == 1, "Invalid format indicator %d for DCI 10\n", dci_pdu_rel15->format_indicator);
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",
dci_pdu_rel15->format_indicator,
1,
N_RB,
dci_size - pos,
*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",
dci_pdu_rel15->frequency_domain_assignment.val,
fsize,
dci_size - pos,
*dci_pdu);
#endif
uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
is_ra = 0;
break;
}
if (is_ra) //fsize are all 1 38.212 p86
{
// ra_preamble_index 6 bits
pos+=6;
dci_pdu_rel15->ra_preamble_index = (*dci_pdu>>(dci_size-pos))&0x3f;
// UL/SUL indicator 1 bit
pos++;
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&1;
// SS/PBCH index 6 bits
pos+=6;
dci_pdu_rel15->ss_pbch_index = (*dci_pdu>>(dci_size-pos))&0x3f;
// prach_mask_index 4 bits
pos+=4;
dci_pdu_rel15->prach_mask_index = (*dci_pdu>>(dci_size-pos))&0xf;
} //end if
else {
// Time domain assignment 4bit
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
bool pdcch_order = true;
for (int i = 0; i < fsize; i++) {
if (!((dci_pdu_rel15->frequency_domain_assignment.val >> i) & 1)) {
pdcch_order = false;
break;
}
}
if (pdcch_order) { // Frequency domain resource assignment field are all 1 38.212 section 7.3.1.2.1
// ra_preamble_index 6 bits
pos += 6;
dci_pdu_rel15->ra_preamble_index = (*dci_pdu >> (dci_size - pos)) & 0x3f;
// UL/SUL indicator 1 bit
pos++;
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu >> (dci_size - pos)) & 1;
// SS/PBCH index 6 bits
pos += 6;
dci_pdu_rel15->ss_pbch_index = (*dci_pdu >> (dci_size - pos)) & 0x3f;
// prach_mask_index 4 bits
pos += 4;
dci_pdu_rel15->prach_mask_index = (*dci_pdu >> (dci_size - pos)) & 0xf;
LOG_E(NR_MAC, "PDCCH order to initiate RA procedure not implemented at UE\n");
} // end if
else {
// Time domain assignment 4bit
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",
dci_pdu_rel15->time_domain_assignment.val,
4,
dci_size - pos,
*dci_pdu);
#endif
// VRB to PRB mapping 1bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
// VRB to PRB mapping 1bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
LOG_D(MAC, "VRB to PRB %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->vrb_to_prb_mapping.val, 1, dci_size - pos, *dci_pdu);
#endif
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// MCS 5bit //bit over 32, so dci_pdu ++
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu);
LOG_D(MAC, "MCS %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->mcs, 5, dci_size - pos, *dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
LOG_D(MAC, "NDI %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->ndi, 1, dci_size - pos, *dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Redundancy version 2bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 0x3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
LOG_D(MAC, "RV %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->rv, 2, dci_size - pos, *dci_pdu);
#endif
// Downlink assignment index 2bit
pos+=2;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
LOG_D(MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 4, dci_size - pos, *dci_pdu);
#endif
// TPC command for scheduled PUCCH 2bit
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// Downlink assignment index 2bit
pos += 2;
dci_pdu_rel15->dai[0].val = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
LOG_D(MAC, "DAI %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->dai[0].val, 2, dci_size - pos, *dci_pdu);
#endif
// PUCCH resource indicator 3bit
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x7;
// TPC command for scheduled PUCCH 2bit
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu);
LOG_D(MAC, "TPC %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->tpc, 2, dci_size - pos, *dci_pdu);
#endif
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&0x7;
// PUCCH resource indicator 3bit
pos += 3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu >> (dci_size - pos)) & 0x7;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
LOG_D(MAC, "PUCCH RI %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->pucch_resource_indicator, 3, dci_size - pos, *dci_pdu);
#endif
} //end else
break;
case TYPE_P_RNTI_:
/*
// Short Messages Indicator  E2 bits
for (int i=0; i<2; i++)
dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++);
// Short Messages  E8 bits
for (int i=0; i<8; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
// TB scaling 2 bit
for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++);
*/
break;
case TYPE_SI_RNTI_:
// Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
// Time domain assignment 4 bit
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
// VRB to PRB mapping 1 bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 0x1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// Redundancy version 2 bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
// System information indicator 1 bit
pos++;
dci_pdu_rel15->system_info_indicator = (*dci_pdu >> (dci_size - pos)) & 0x1;
LOG_D(MAC, "N_RB = %i\n", N_RB);
LOG_D(MAC, "dci_size = %i\n", dci_size);
LOG_D(MAC, "fsize = %i\n", fsize);
LOG_D(MAC, "dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(MAC, "dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(MAC, "dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(MAC, "dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(MAC, "dci_pdu_rel15->system_info_indicator = %i\n", dci_pdu_rel15->system_info_indicator);
break;
case TYPE_TC_RNTI_:
// indicating a DL DCI format 1bit
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
// switch to DCI_0_0
if (dci_pdu_rel15->format_indicator == 0) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_UL_DCI_FORMAT_0_0];
return 2 + nr_extract_dci_info(mac, NR_UL_DCI_FORMAT_0_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
// Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment - 4 bits
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
// VRB to PRB mapping - 1 bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator - 1 bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
// Redundancy version - 2 bits
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number - 4 bits
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index - 2 bits
pos+=2;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
// TPC command for scheduled PUCCH - 2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// PUCCH resource indicator - 3 bits
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&7;
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
pos+=3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7;
LOG_D(NR_MAC,"N_RB = %i\n", N_RB);
LOG_D(NR_MAC,"dci_size = %i\n", dci_size);
LOG_D(NR_MAC,"fsize = %i\n", fsize);
LOG_D(NR_MAC,"dci_pdu_rel15->format_indicator = %i\n", dci_pdu_rel15->format_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC,"dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(NR_MAC,"dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC,"dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC,"dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC,"dci_pdu_rel15->dai[0].val = %i\n", dci_pdu_rel15->dai[0].val);
LOG_D(NR_MAC,"dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC,"dci_pdu_rel15->pucch_resource_indicator = %i\n", dci_pdu_rel15->pucch_resource_indicator);
LOG_D(NR_MAC,"dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = %i\n", dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val);
break;
}
break;
case NR_UL_DCI_FORMAT_0_0:
switch(rnti_type)
{
case TYPE_C_RNTI_:
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos += 3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu >> (dci_size - pos)) & 0x7;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,
3,
dci_size - pos,
*dci_pdu);
#endif
if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits;
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
} // end else
}
static void extract_00_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size)
{
int pos = 0;
int fsize = 0;
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
LOG_D(MAC, "Format indicator %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->format_indicator, 1, dci_size - pos, *dci_pdu);
#endif
// Time domain assignment 4bit
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
AssertFatal(dci_pdu_rel15->format_indicator == 0, "Invalid format indicator %d for DCI 00\n", dci_pdu_rel15->format_indicator);
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits;
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",
dci_pdu_rel15->frequency_domain_assignment.val,
fsize,
dci_size - pos,
*dci_pdu);
#endif
// Frequency hopping flag  E1 bit
pos++;
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// Time domain assignment 4bit
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu);
LOG_D(MAC,
"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",
dci_pdu_rel15->time_domain_assignment.val,
dci_size - pos,
*dci_pdu);
#endif
// MCS 5 bit
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
// Frequency hopping flag  E1 bit
pos++;
dci_pdu_rel15->frequency_hopping_flag.val = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
LOG_D(MAC, "frequency_hopping %d (1 bit)=> %d (0x%lx)\n", dci_pdu_rel15->frequency_hopping_flag.val, dci_size - pos, *dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
LOG_D(MAC, "mcs %d (5 bits)=> %d (0x%lx)\n", dci_pdu_rel15->mcs, dci_size - pos, *dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
LOG_D(MAC, "NDI %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->ndi, 1, dci_size - pos, *dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Redundancy version 2bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
LOG_D(MAC, "RV %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->rv, 2, dci_size - pos, *dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
LOG_D(MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 4, dci_size - pos, *dci_pdu);
#endif
// UL/SUL indicator  E1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break;
case TYPE_TC_RNTI_:
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
// TPC command for scheduled PUSCH  E2 bits
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Format indicator %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,dci_size-pos,*dci_pdu);
LOG_D(MAC, "TPC %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->tpc, 2, dci_size - pos, *dci_pdu);
#endif
// UL/SUL indicator  E1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
}
//switch to DCI_1_0
if (dci_pdu_rel15->format_indicator == 1) {
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][NR_DL_DCI_FORMAT_1_0];
return 2 + nr_extract_dci_info(mac, NR_DL_DCI_FORMAT_1_0, dci_size, rnti, ss_type, dci_pdu, dci_pdu_rel15, slot);
}
static void extract_10_tc_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size, int N_RB)
{
int pos = 0;
int fsize = 0;
// indicating a DL DCI format 1bit
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
AssertFatal(dci_pdu_rel15->format_indicator == 1, "Invalid format indicator %d for DCI 10\n", dci_pdu_rel15->format_indicator);
// Freq domain assignment 0-16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
// Time domain assignment - 4 bits
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
// VRB to PRB mapping - 1 bit
pos++;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & 1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// New data indicator - 1 bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 1;
// Redundancy version - 2 bits
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
// HARQ process number - 4 bits
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
// Downlink assignment index - 2 bits
pos += 2;
dci_pdu_rel15->dai[0].val = (*dci_pdu >> (dci_size - pos)) & 3;
// TPC command for scheduled PUCCH - 2 bits
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 3;
// PUCCH resource indicator - 3 bits
pos += 3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu >> (dci_size - pos)) & 7;
// PDSCH-to-HARQ_feedback timing indicator - 3 bits
pos += 3;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu >> (dci_size - pos)) & 7;
LOG_D(NR_MAC, "N_RB = %i\n", N_RB);
LOG_D(NR_MAC, "dci_size = %i\n", dci_size);
LOG_D(NR_MAC, "fsize = %i\n", fsize);
LOG_D(NR_MAC, "dci_pdu_rel15->format_indicator = %i\n", dci_pdu_rel15->format_indicator);
LOG_D(NR_MAC, "dci_pdu_rel15->frequency_domain_assignment.val = %i\n", dci_pdu_rel15->frequency_domain_assignment.val);
LOG_D(NR_MAC, "dci_pdu_rel15->time_domain_assignment.val = %i\n", dci_pdu_rel15->time_domain_assignment.val);
LOG_D(NR_MAC, "dci_pdu_rel15->vrb_to_prb_mapping.val = %i\n", dci_pdu_rel15->vrb_to_prb_mapping.val);
LOG_D(NR_MAC, "dci_pdu_rel15->mcs = %i\n", dci_pdu_rel15->mcs);
LOG_D(NR_MAC, "dci_pdu_rel15->rv = %i\n", dci_pdu_rel15->rv);
LOG_D(NR_MAC, "dci_pdu_rel15->harq_pid = %i\n", dci_pdu_rel15->harq_pid);
LOG_D(NR_MAC, "dci_pdu_rel15->dai[0].val = %i\n", dci_pdu_rel15->dai[0].val);
LOG_D(NR_MAC, "dci_pdu_rel15->tpc = %i\n", dci_pdu_rel15->tpc);
LOG_D(NR_MAC, "dci_pdu_rel15->pucch_resource_indicator = %i\n", dci_pdu_rel15->pucch_resource_indicator);
LOG_D(NR_MAC,
"dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = %i\n",
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val);
}
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits;
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
static void extract_00_tc_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size)
{
int pos = 0;
int fsize = 0;
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
LOG_I(MAC, "Format indicator %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->format_indicator, 1, dci_size - pos, *dci_pdu);
#endif
// Time domain assignment 4bit
pos+=4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
AssertFatal(dci_pdu_rel15->format_indicator == 0, "Invalid format indicator %d for DCI 00\n", dci_pdu_rel15->format_indicator);
// Frequency domain assignment
fsize = dci_pdu_rel15->frequency_domain_assignment.nbits;
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
LOG_I(MAC,
"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",
dci_pdu_rel15->frequency_domain_assignment.val,
fsize,
dci_size - pos,
*dci_pdu);
#endif
// Frequency hopping flag  E1 bit
pos++;
dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// Time domain assignment 4bit
pos += 4;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"frequency_hopping %d (1 bit)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_hopping_flag.val,dci_size-pos,*dci_pdu);
LOG_I(MAC,
"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",
dci_pdu_rel15->time_domain_assignment.val,
dci_size - pos,
*dci_pdu);
#endif
// MCS 5 bit
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
// Frequency hopping flag  E1 bit
pos++;
dci_pdu_rel15->frequency_hopping_flag.val = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
LOG_I(MAC, "frequency_hopping %d (1 bit)=> %d (0x%lx)\n", dci_pdu_rel15->frequency_hopping_flag.val, dci_size - pos, *dci_pdu);
#endif
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
LOG_I(MAC, "mcs %d (5 bits)=> %d (0x%lx)\n", dci_pdu_rel15->mcs, dci_size - pos, *dci_pdu);
#endif
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 1;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
LOG_I(MAC, "NDI %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->ndi, 1, dci_size - pos, *dci_pdu);
#endif
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Redundancy version 2bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
LOG_I(MAC, "RV %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->rv, 2, dci_size - pos, *dci_pdu);
#endif
// TPC command for scheduled PUSCH  E2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
LOG_I(MAC, "HARQ_PID %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->harq_pid, 4, dci_size - pos, *dci_pdu);
#endif
break;
}
break;
// TPC command for scheduled PUSCH  E2 bits
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 3;
#ifdef DEBUG_EXTRACT_DCI
LOG_I(MAC, "TPC %d (%d bits)=> %d (0x%lx)\n", dci_pdu_rel15->tpc, 2, dci_size - pos, *dci_pdu);
#endif
}
case NR_DL_DCI_FORMAT_1_1:
switch(rnti_type)
{
case TYPE_C_RNTI_:
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
if (dci_pdu_rel15->format_indicator == 0)
return 1; // discard dci, format indicator not corresponding to dci_format
// Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits;
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1);
// BWP Indicator
pos+=dci_pdu_rel15->bwp_indicator.nbits;
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1);
// Frequency domain resource assignment
pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1);
// Time domain resource assignment
pos+=dci_pdu_rel15->time_domain_assignment.nbits;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1);
// VRB-to-PRB mapping
pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1);
// PRB bundling size indicator
pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
dci_pdu_rel15->prb_bundling_size_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1);
// Rate matching indicator
pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
dci_pdu_rel15->rate_matching_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1);
// ZP CSI-RS trigger
pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1);
//TB1
// MCS 5bit
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator 1bit
pos+=1;
dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&0x1;
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
//TB2
// MCS 5bit
pos+=dci_pdu_rel15->mcs2.nbits;
dci_pdu_rel15->mcs2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->mcs2.nbits)-1);
// New data indicator 1bit
pos+=dci_pdu_rel15->ndi2.nbits;
dci_pdu_rel15->ndi2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ndi2.nbits)-1);
// Redundancy version 2bit
pos+=dci_pdu_rel15->rv2.nbits;
dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rv2.nbits)-1);
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
// TPC command for scheduled PUCCH 2bit
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&0x3;
// PUCCH resource indicator 3bit
pos+=3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x3;
// PDSCH-to-HARQ_feedback timing indicator
pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1);
// Antenna ports
pos+=dci_pdu_rel15->antenna_ports.nbits;
dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->antenna_ports.nbits)-1);
// TCI
pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
dci_pdu_rel15->transmission_configuration_indication.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1);
// SRS request
pos+=dci_pdu_rel15->srs_request.nbits;
dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_request.nbits)-1);
// CBG transmission information
pos+=dci_pdu_rel15->cbgti.nbits;
dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgti.nbits)-1);
// CBG flushing out information
pos+=dci_pdu_rel15->cbgfi.nbits;
dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgfi.nbits)-1);
// DMRS sequence init
pos+=1;
dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&0x1;
break;
static void extract_11_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size)
{
int pos = 0;
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
AssertFatal(dci_pdu_rel15->format_indicator == 1, "Invalid format indicator %d for DCI 11\n", dci_pdu_rel15->format_indicator);
// Carrier indicator
pos += dci_pdu_rel15->carrier_indicator.nbits;
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->carrier_indicator.nbits) - 1);
// BWP Indicator
pos += dci_pdu_rel15->bwp_indicator.nbits;
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->bwp_indicator.nbits) - 1);
// Frequency domain resource assignment
pos += dci_pdu_rel15->frequency_domain_assignment.nbits;
dci_pdu_rel15->frequency_domain_assignment.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->frequency_domain_assignment.nbits) - 1);
// Time domain resource assignment
pos += dci_pdu_rel15->time_domain_assignment.nbits;
dci_pdu_rel15->time_domain_assignment.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->time_domain_assignment.nbits) - 1);
// VRB-to-PRB mapping
pos += dci_pdu_rel15->vrb_to_prb_mapping.nbits;
dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->vrb_to_prb_mapping.nbits) - 1);
// PRB bundling size indicator
pos += dci_pdu_rel15->prb_bundling_size_indicator.nbits;
dci_pdu_rel15->prb_bundling_size_indicator.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->prb_bundling_size_indicator.nbits) - 1);
// Rate matching indicator
pos += dci_pdu_rel15->rate_matching_indicator.nbits;
dci_pdu_rel15->rate_matching_indicator.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->rate_matching_indicator.nbits) - 1);
// ZP CSI-RS trigger
pos += dci_pdu_rel15->zp_csi_rs_trigger.nbits;
dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->zp_csi_rs_trigger.nbits) - 1);
// TB1
// MCS 5bit
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// New data indicator 1bit
pos += 1;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 0x1;
// Redundancy version 2bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 0x3;
// TB2
// MCS 5bit
pos += dci_pdu_rel15->mcs2.nbits;
dci_pdu_rel15->mcs2.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->mcs2.nbits) - 1);
// New data indicator 1bit
pos += dci_pdu_rel15->ndi2.nbits;
dci_pdu_rel15->ndi2.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->ndi2.nbits) - 1);
// Redundancy version 2bit
pos += dci_pdu_rel15->rv2.nbits;
dci_pdu_rel15->rv2.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->rv2.nbits) - 1);
// HARQ process number 4bit
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
// Downlink assignment index
pos += dci_pdu_rel15->dai[0].nbits;
dci_pdu_rel15->dai[0].val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->dai[0].nbits) - 1);
// TPC command for scheduled PUCCH 2bit
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 0x3;
// PUCCH resource indicator 3bit
pos += 3;
dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu >> (dci_size - pos)) & 0x3;
// PDSCH-to-HARQ_feedback timing indicator
pos += dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits) - 1);
// Antenna ports
pos += dci_pdu_rel15->antenna_ports.nbits;
dci_pdu_rel15->antenna_ports.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->antenna_ports.nbits) - 1);
// TCI
pos += dci_pdu_rel15->transmission_configuration_indication.nbits;
dci_pdu_rel15->transmission_configuration_indication.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->transmission_configuration_indication.nbits) - 1);
// SRS request
pos += dci_pdu_rel15->srs_request.nbits;
dci_pdu_rel15->srs_request.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->srs_request.nbits) - 1);
// CBG transmission information
pos += dci_pdu_rel15->cbgti.nbits;
dci_pdu_rel15->cbgti.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->cbgti.nbits) - 1);
// CBG flushing out information
pos += dci_pdu_rel15->cbgfi.nbits;
dci_pdu_rel15->cbgfi.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->cbgfi.nbits) - 1);
// DMRS sequence init
pos += 1;
dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu >> (dci_size - pos)) & 0x1;
}
static void extract_01_c_rnti(dci_pdu_rel15_t *dci_pdu_rel15, uint64_t *dci_pdu, uint8_t dci_size, int N_RB)
{
int pos = 0;
int fsize = 0;
// Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu >> (dci_size - pos)) & 1;
AssertFatal(dci_pdu_rel15->format_indicator == 0, "Invalid format indicator %d for DCI 01\n", dci_pdu_rel15->format_indicator);
// Carrier indicator
pos += dci_pdu_rel15->carrier_indicator.nbits;
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->carrier_indicator.nbits) - 1);
// UL/SUL Indicator
pos += dci_pdu_rel15->ul_sul_indicator.nbits;
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->ul_sul_indicator.nbits) - 1);
// BWP Indicator
pos += dci_pdu_rel15->bwp_indicator.nbits;
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->bwp_indicator.nbits) - 1);
// Freq domain assignment max 16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos += fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu >> (dci_size - pos)) & ((1 << fsize) - 1);
// Time domain assignment
// pos+=4;
pos += dci_pdu_rel15->time_domain_assignment.nbits;
dci_pdu_rel15->time_domain_assignment.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->time_domain_assignment.nbits) - 1);
// Not supported yet - skip for now
// Frequency hopping flag – 1 bit
// pos++;
// dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos += 5;
dci_pdu_rel15->mcs = (*dci_pdu >> (dci_size - pos)) & 0x1f;
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi = (*dci_pdu >> (dci_size - pos)) & 1;
// Redundancy version 2bit
pos += 2;
dci_pdu_rel15->rv = (*dci_pdu >> (dci_size - pos)) & 3;
// HARQ process number 4bit
pos += 4;
dci_pdu_rel15->harq_pid = (*dci_pdu >> (dci_size - pos)) & 0xf;
// 1st Downlink assignment index
pos += dci_pdu_rel15->dai[0].nbits;
dci_pdu_rel15->dai[0].val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->dai[0].nbits) - 1);
// 2nd Downlink assignment index
pos += dci_pdu_rel15->dai[1].nbits;
dci_pdu_rel15->dai[1].val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->dai[1].nbits) - 1);
// TPC command for scheduled PUSCH – 2 bits
pos += 2;
dci_pdu_rel15->tpc = (*dci_pdu >> (dci_size - pos)) & 3;
// SRS resource indicator
pos += dci_pdu_rel15->srs_resource_indicator.nbits;
dci_pdu_rel15->srs_resource_indicator.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->srs_resource_indicator.nbits) - 1);
// Precoding info and n. of layers
pos += dci_pdu_rel15->precoding_information.nbits;
dci_pdu_rel15->precoding_information.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->precoding_information.nbits) - 1);
// Antenna ports
pos += dci_pdu_rel15->antenna_ports.nbits;
dci_pdu_rel15->antenna_ports.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->antenna_ports.nbits) - 1);
// SRS request
pos += dci_pdu_rel15->srs_request.nbits;
dci_pdu_rel15->srs_request.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->srs_request.nbits) - 1);
// CSI request
pos += dci_pdu_rel15->csi_request.nbits;
dci_pdu_rel15->csi_request.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->csi_request.nbits) - 1);
// CBG transmission information
pos += dci_pdu_rel15->cbgti.nbits;
dci_pdu_rel15->cbgti.val = (*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->cbgti.nbits) - 1);
// PTRS DMRS association
pos += dci_pdu_rel15->ptrs_dmrs_association.nbits;
dci_pdu_rel15->ptrs_dmrs_association.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->ptrs_dmrs_association.nbits) - 1);
// Beta offset indicator
pos += dci_pdu_rel15->beta_offset_indicator.nbits;
dci_pdu_rel15->beta_offset_indicator.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->beta_offset_indicator.nbits) - 1);
// DMRS sequence initialization
pos += dci_pdu_rel15->dmrs_sequence_initialization.nbits;
dci_pdu_rel15->dmrs_sequence_initialization.val =
(*dci_pdu >> (dci_size - pos)) & ((1 << dci_pdu_rel15->dmrs_sequence_initialization.nbits) - 1);
// UL-SCH indicator
pos += 1;
dci_pdu_rel15->ulsch_indicator = (*dci_pdu >> (dci_size - pos)) & 0x1;
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
}
static int get_nrb_for_dci(NR_UE_MAC_INST_t *mac, nr_dci_format_t dci_format, int ss_type)
{
NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
int N_RB;
if(current_DL_BWP)
N_RB = get_rb_bwp_dci(dci_format,
ss_type,
mac->type0_PDCCH_CSS_config.num_rbs,
current_UL_BWP->BWPSize,
current_DL_BWP->BWPSize,
mac->sc_info.initial_dl_BWPSize,
mac->sc_info.initial_dl_BWPSize);
else
N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
if (N_RB == 0)
LOG_E(MAC, "DCI configuration error! N_RB = 0\n");
return N_RB;
}
static nr_dci_format_t nr_extract_dci_00_10(NR_UE_MAC_INST_t *mac,
uint8_t dci_size,
int rnti_type,
uint64_t *dci_pdu,
int slot,
int ss_type)
{
nr_dci_format_t format = NR_DCI_NONE;
dci_pdu_rel15_t *dci_pdu_rel15 = NULL;
int format_indicator = -1;
int n_RB = 0;
switch (rnti_type) {
case TYPE_RA_RNTI_ :
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_ra_rnti(dci_pdu_rel15, dci_pdu, dci_size, n_RB);
break;
case TYPE_P_RNTI_ :
AssertFatal(false, "DCI for P-RNTI not handled yet\n");
break;
case TYPE_SI_RNTI_ :
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_si_rnti(dci_pdu_rel15, dci_pdu, dci_size, n_RB);
break;
case TYPE_C_RNTI_ :
format_indicator = (*dci_pdu >> (dci_size - 1)) & 1;
if (format_indicator == 1) {
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
int n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_c_rnti(dci_pdu_rel15, dci_pdu, dci_size, n_RB);
}
else {
format = NR_UL_DCI_FORMAT_0_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
extract_00_c_rnti(dci_pdu_rel15, dci_pdu, dci_size);
}
break;
case NR_UL_DCI_FORMAT_0_1:
switch(rnti_type)
{
case TYPE_C_RNTI_:
//Identifier for DCI formats
pos++;
dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
if (dci_pdu_rel15->format_indicator == 1)
return 1; // discard dci, format indicator not corresponding to dci_format
// Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits;
dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1);
// UL/SUL Indicator
pos+=dci_pdu_rel15->ul_sul_indicator.nbits;
dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ul_sul_indicator.nbits)-1);
// BWP Indicator
pos+=dci_pdu_rel15->bwp_indicator.nbits;
dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1);
// Freq domain assignment max 16 bit
fsize = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
pos+=fsize;
dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment
//pos+=4;
pos+=dci_pdu_rel15->time_domain_assignment.nbits;
dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1);
// Not supported yet - skip for now
// Frequency hopping flag – 1 bit
//pos++;
//dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
// New data indicator 1bit
pos++;
dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
// Redundancy version 2bit
pos+=2;
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos+=4;
dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// 1st Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits;
dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
// 2nd Downlink assignment index
pos+=dci_pdu_rel15->dai[1].nbits;
dci_pdu_rel15->dai[1].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[1].nbits)-1);
// TPC command for scheduled PUSCH – 2 bits
pos+=2;
dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// SRS resource indicator
pos+=dci_pdu_rel15->srs_resource_indicator.nbits;
dci_pdu_rel15->srs_resource_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_resource_indicator.nbits)-1);
// Precoding info and n. of layers
pos+=dci_pdu_rel15->precoding_information.nbits;
dci_pdu_rel15->precoding_information.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->precoding_information.nbits)-1);
// Antenna ports
pos+=dci_pdu_rel15->antenna_ports.nbits;
dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->antenna_ports.nbits)-1);
// SRS request
pos+=dci_pdu_rel15->srs_request.nbits;
dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_request.nbits)-1);
// CSI request
pos+=dci_pdu_rel15->csi_request.nbits;
dci_pdu_rel15->csi_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->csi_request.nbits)-1);
// CBG transmission information
pos+=dci_pdu_rel15->cbgti.nbits;
dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgti.nbits)-1);
// PTRS DMRS association
pos+=dci_pdu_rel15->ptrs_dmrs_association.nbits;
dci_pdu_rel15->ptrs_dmrs_association.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ptrs_dmrs_association.nbits)-1);
// Beta offset indicator
pos+=dci_pdu_rel15->beta_offset_indicator.nbits;
dci_pdu_rel15->beta_offset_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->beta_offset_indicator.nbits)-1);
// DMRS sequence initialization
pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits;
dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dmrs_sequence_initialization.nbits)-1);
// UL-SCH indicator
pos+=1;
dci_pdu_rel15->ulsch_indicator = (*dci_pdu>>(dci_size-pos))&0x1;
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break;
case TYPE_TC_RNTI_ :
format_indicator = (*dci_pdu >> (dci_size - 1)) & 1;
if (format_indicator == 1) {
format = NR_DL_DCI_FORMAT_1_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_10_tc_rnti(dci_pdu_rel15, dci_pdu, dci_size, n_RB);
}
break;
default: // other DCI formats
break;
else {
format = NR_UL_DCI_FORMAT_0_0;
dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
extract_00_tc_rnti(dci_pdu_rel15, dci_pdu, dci_size);
}
break;
default :
AssertFatal(false, "Invalid RNTI type\n");
}
return format;
}
return 0;
static nr_dci_format_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
nfapi_nr_dci_formats_e dci_format,
uint8_t dci_size,
uint16_t rnti,
int ss_type,
uint64_t *dci_pdu,
int slot)
{
LOG_D(MAC,"nr_extract_dci_info : dci_pdu %lx, size %d, format %d\n", *dci_pdu, dci_size, dci_format);
int rnti_type = get_rnti_type(mac, rnti);
nr_dci_format_t format = NR_DCI_NONE;
switch(dci_format) {
case NFAPI_NR_FORMAT_0_0_AND_1_0 :
format = nr_extract_dci_00_10(mac, dci_size, rnti_type, dci_pdu, slot, ss_type);
break;
case NFAPI_NR_FORMAT_0_1_AND_1_1 :
if (rnti_type == TYPE_C_RNTI_) {
int format_indicator = (*dci_pdu >> (dci_size - 1)) & 1;
if (format_indicator == 1) {
format = NR_DL_DCI_FORMAT_1_1;
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
extract_11_c_rnti(def_dci_pdu_rel15, dci_pdu, dci_size);
}
else {
format = NR_UL_DCI_FORMAT_0_1;
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[slot][format];
int n_RB = get_nrb_for_dci(mac, format, ss_type);
if (n_RB == 0)
return NR_DCI_NONE;
extract_01_c_rnti(def_dci_pdu_rel15, dci_pdu, dci_size, n_RB);
}
}
else {
LOG_E(NR_MAC, "RNTI type not supported for formats 01 or 11\n");
return NR_DCI_NONE;
}
break;
default :
LOG_E(NR_MAC, "DCI format not supported\n");
}
return format;
}
///////////////////////////////////
// brief: nr_ue_process_mac_pdu
// function: parsing DL PDU header
......
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @ 75ec3861
......@@ -1064,14 +1064,9 @@ static int handle_bcch_dlsch(NR_UE_MAC_INST_t *mac,
}
// L2 Abstraction Layer
static int handle_dci(NR_UE_MAC_INST_t *mac,
int cc_id,
unsigned int gNB_index,
frame_t frame,
int slot,
fapi_nr_dci_indication_pdu_t *dci)
static nr_dci_format_t handle_dci(NR_UE_MAC_INST_t *mac, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci)
{
return nr_ue_process_dci_indication_pdu(mac, cc_id, gNB_index, frame, slot, dci);
return nr_ue_process_dci_indication_pdu(mac, frame, slot, dci);
}
static void handle_ssb_meas(NR_UE_MAC_INST_t *mac, uint8_t ssb_index, int16_t rsrp_dbm)
......@@ -1165,26 +1160,18 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info)
LOG_T(MAC, "[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
for (int i = 0; i < dl_info->dci_ind->number_of_dcis; i++) {
LOG_T(MAC, ">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n", i, dl_info->dci_ind->number_of_dcis);
int8_t ret = handle_dci(mac,
dl_info->cc_id,
dl_info->gNB_index,
dl_info->frame,
dl_info->slot,
dl_info->dci_ind->dci_list + i);
if (ret < 0)
continue;
fapi_nr_dci_indication_pdu_t *dci_index = dl_info->dci_ind->dci_list + i;
nr_dci_format_t dci_format = handle_dci(mac, dl_info->frame, dl_info->slot, dl_info->dci_ind->dci_list + i);
/* The check below filters out UL_DCIs which are being processed as DL_DCIs. */
if (dci_index->dci_format != NR_DL_DCI_FORMAT_1_0 && dci_index->dci_format != NR_DL_DCI_FORMAT_1_1) {
if (dci_format != NR_DL_DCI_FORMAT_1_0 && dci_format != NR_DL_DCI_FORMAT_1_1) {
LOG_D(NR_MAC, "We are filtering a UL_DCI to prevent it from being treated like a DL_DCI\n");
continue;
}
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[dl_info->slot][dci_index->dci_format];
dci_pdu_rel15_t *def_dci_pdu_rel15 = &mac->def_dci_pdu_rel15[dl_info->slot][dci_format];
g_harq_pid = def_dci_pdu_rel15->harq_pid;
LOG_T(NR_MAC, "Setting harq_pid = %d and dci_index = %d (based on format)\n", g_harq_pid, dci_index->dci_format);
LOG_T(NR_MAC, "Setting harq_pid = %d and dci_index = %d (based on format)\n", g_harq_pid, dci_format);
ret_mask |= (ret << FAPI_NR_DCI_IND);
ret_mask |= (1 << FAPI_NR_DCI_IND);
AssertFatal(nr_ue_if_module_inst[dl_info->module_id] != NULL, "IF module is NULL!\n");
fapi_nr_dl_config_request_t *dl_config = get_dl_config_request(mac, dl_info->slot);
nr_scheduled_response_t scheduled_response = {.dl_config = dl_config,
......@@ -1196,70 +1183,70 @@ static uint32_t nr_ue_dl_processing(nr_downlink_indication_t *dl_info)
memset(def_dci_pdu_rel15, 0, sizeof(*def_dci_pdu_rel15));
}
dl_info->dci_ind = NULL;
}
}
if (dl_info->rx_ind != NULL) {
for (int i = 0; i < dl_info->rx_ind->number_pdus; ++i) {
fapi_nr_rx_indication_body_t rx_indication_body = dl_info->rx_ind->rx_indication_body[i];
LOG_D(NR_MAC,
"slot %d Sending DL indication to MAC. 1 PDU type %d of %d total number of PDUs \n",
dl_info->slot,
rx_indication_body.pdu_type,
dl_info->rx_ind->number_pdus);
switch(rx_indication_body.pdu_type){
case FAPI_NR_RX_PDU_TYPE_SSB:
handle_rlm(rx_indication_body.ssb_pdu.radiolink_monitoring,
dl_info->frame,
mac);
if(rx_indication_body.ssb_pdu.decoded_pdu) {
handle_ssb_meas(mac,
rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.rsrp_dBm);
ret_mask |= (handle_bcch_bch(mac,
dl_info->cc_id,
dl_info->gNB_index,
dl_info->phy_data,
rx_indication_body.ssb_pdu.pdu,
rx_indication_body.ssb_pdu.additional_bits,
rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.ssb_length,
rx_indication_body.ssb_pdu.ssb_start_subcarrier,
rx_indication_body.ssb_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_SSB;
}
break;
case FAPI_NR_RX_PDU_TYPE_SIB:
ret_mask |= (handle_bcch_dlsch(mac,
dl_info->cc_id, dl_info->gNB_index,
rx_indication_body.pdsch_pdu.ack_nack,
rx_indication_body.pdsch_pdu.pdu,
rx_indication_body.pdsch_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB;
break;
case FAPI_NR_RX_PDU_TYPE_DLSCH:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
break;
case FAPI_NR_RX_PDU_TYPE_RAR:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_RAR;
if (!dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.ack_nack)
LOG_W(PHY, "Received a RAR-Msg2 but LDPC decode failed\n");
else
LOG_I(PHY, "RAR-Msg2 decoded\n");
break;
case FAPI_NR_CSIRS_IND:
ret_mask |= (handle_csirs_measurements(mac,
dl_info->frame,
dl_info->slot,
&rx_indication_body.csirs_measurements)) << FAPI_NR_CSIRS_IND;
break;
default:
break;
}
if (dl_info->rx_ind != NULL) {
for (int i = 0; i < dl_info->rx_ind->number_pdus; ++i) {
fapi_nr_rx_indication_body_t rx_indication_body = dl_info->rx_ind->rx_indication_body[i];
LOG_D(NR_MAC,
"slot %d Sending DL indication to MAC. 1 PDU type %d of %d total number of PDUs \n",
dl_info->slot,
rx_indication_body.pdu_type,
dl_info->rx_ind->number_pdus);
switch(rx_indication_body.pdu_type){
case FAPI_NR_RX_PDU_TYPE_SSB:
handle_rlm(rx_indication_body.ssb_pdu.radiolink_monitoring,
dl_info->frame,
mac);
if(rx_indication_body.ssb_pdu.decoded_pdu) {
handle_ssb_meas(mac,
rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.rsrp_dBm);
ret_mask |= (handle_bcch_bch(mac,
dl_info->cc_id,
dl_info->gNB_index,
dl_info->phy_data,
rx_indication_body.ssb_pdu.pdu,
rx_indication_body.ssb_pdu.additional_bits,
rx_indication_body.ssb_pdu.ssb_index,
rx_indication_body.ssb_pdu.ssb_length,
rx_indication_body.ssb_pdu.ssb_start_subcarrier,
rx_indication_body.ssb_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_SSB;
}
break;
case FAPI_NR_RX_PDU_TYPE_SIB:
ret_mask |= (handle_bcch_dlsch(mac,
dl_info->cc_id, dl_info->gNB_index,
rx_indication_body.pdsch_pdu.ack_nack,
rx_indication_body.pdsch_pdu.pdu,
rx_indication_body.pdsch_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB;
break;
case FAPI_NR_RX_PDU_TYPE_DLSCH:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
break;
case FAPI_NR_RX_PDU_TYPE_RAR:
ret_mask |= (handle_dlsch(mac, dl_info, i)) << FAPI_NR_RX_PDU_TYPE_RAR;
if (!dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.ack_nack)
LOG_W(PHY, "Received a RAR-Msg2 but LDPC decode failed\n");
else
LOG_I(PHY, "RAR-Msg2 decoded\n");
break;
case FAPI_NR_CSIRS_IND:
ret_mask |= (handle_csirs_measurements(mac,
dl_info->frame,
dl_info->slot,
&rx_indication_body.csirs_measurements)) << FAPI_NR_CSIRS_IND;
break;
default:
break;
}
dl_info->rx_ind = NULL;
}
return ret_mask;
dl_info->rx_ind = NULL;
}
return ret_mask;
}
int nr_ue_dl_indication(nr_downlink_indication_t *dl_info)
......
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